FEDL64P168-01 Semiconductor ML64P168 This version: Sep. 27,1999 Previous version: Jun. 22,1999 4-Bit Microcontroller with Built-in RC Oscillation Type A/D Converter and LCD Driver GENERAL DESCRIPTION The ML64P168 is a one-time-programmable ROM-version product, which has one-time PROM (OTP) as internal program memory. On the other hand, the ML64168 is a mask ROM-version product, which has mask ROM as internal program memory. Unlike the mask ROM-version product (ML64168), the ML64P168 cannot be supplied in the form of a chip. The ML64P168 has two operation modes, microcontroller operation mode and PROM mode. The microcontroller operation mode is used to operate the ML64P168 like a ML64168 and the PROM mode is used to program or read the PROM. The ML64P168 is a low power 4-bit microcontroller incorporating the Oki’s original CPU core nX4/30. The ML64P168 provides a minimum instruction execution time of 4.3µs (@700kHz). The ML64P168 contains 8160-byte program memory, 512-nibble data memory, three 4-bit input-output ports, 4-bit input port, 4-bit output port, 2-channel RC oscillation type A/D converter, LCD driver for up to 120 segments, and buzzer output port. APPLICATION The ML64P168 is best suited for low power, high precision thermometers and hygrometers. FEATURES ∙ Processing speed Minimum instruction execution time : 4.3 µs @700 kHz 91.6 µs @32.768 kHz ∙ Clock generation circuit Low-speed clock : 32.768 kHz crystal oscillator High-speed clock : 700 kHz RC oscillator ( with an external resistor ) CPU clock is selectable as Low-speed clock / High-speed clock by software. ∙ Operating voltage : 1.5 V spec. / 3.0 V spec. ( selectable by mask option ) 1.45 to 1.70 V (1.5V spec.) 2.7 to 3.5 V (3.0V spec.) ∙ Operating temperature : 0 to +65°C The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 1/51 FEDL64P168-01 ML64P168 Semiconductor ∙ Memory space Internal program memory Internal data memory ∙ RC oscillation type A/D converter Counter A Counter B ∙ I/O port Input-output port Input port Output port : 8160 bytes : 512 nibbles : 2 channels Time division 2-channel method : 1 / ( 104 × 8 ) × 1 : 1 / 214 × 1 : 3 ports × 4 bits : 1 port × 4 bits : 1 port × 4 bits ( 8 out of the 34 LCD driver outputs can be used as output-only ports by mask option. ) ∙ LCD driver : 34 outputs (1) At 1/4 duty and 1/3 bias : 120 segments (max.) (2) At 1/3 duty and 1/3 bias : 93 segments (max.) (3) At 1/2 duty and 1/2 bias : 64 segments (max.) Voltage Regulator for LCD Driver (selectable by mask option) The LCD panel display is stable regardless of temporary supply voltage drop, because the voltage generated by the voltage regulator for LCD driver is supplied to the bias voltage generator as a reference voltage. LCD Operating Voltage When the voltage regulator for LCD driver is used : 3.6 V ( Duty cycle = 1/4 or 1/3 ) : 2.4 V ( Duty cycle = 1/2 ) When the voltage regulator for LCD driver is not used : 4.5 V ( Duty cycle = 1/4 or 1/3 ) : 3.0 V ( Duty cycle = 1/2 ) ∙ Buzzer driver : 1 output ( 4 output modes selectable ) ∙ Serial port : Synchronous 8-bit transfer Selectable as external clock / internal clock Selectable as MSB first / LSB first ∙ Capture circuit : 2 channels ( 32Hz, 64Hz, 128Hz, 256Hz ) ∙ Battery check circuit : 1 ( incorporated into the input-only port ) ∙ Watchdog timer ∙ Interrupt External interrupt : 2 sources Internal interrupt : 8 sources ∙ Package: 80-pin plastic QFP ( QFP80-P-1420-0.80-BK ) Product name : ML64P168 - xxxGP ( written PROM ) ML64P168 - NGP ( blanked PROM ) 80-pin plastic QFP ( QFP80-P-1414-0.65-K ) Product name : ML64P168 - xxxGA ( written PROM ) ML64P168 - NGA ( blanked PROM ) xxx indicates a code number. 2/51 FEDL64P168-01 ML64P168 Semiconductor PROGRAM DEVELOPMENT ENVIRONMENT ∙ Structured Assembler ∙ In Circuit Emulator ∙ Debugger : : : SASM64K EASE64168 DT64K 3/51 FEDL64P168-01 ML64P168 Semiconductor BLOCK DIAGRAM CPU CORE: nX-4/30 VPP IR DECORDER DATA BUS ( 8 ) TR2 BSR MIEF C TR0 TR1 PCH ALU IR PROM 8160 Bytes ROMR PCM PCL HALT H L B A X Y DATA BUS ( 8 ) TIMING CONTROLLER SP RAM 512 Nibbles BC INT 5 2CLK RST RSTC TBC SIOP INT BD BD ADDRESS BUS OSC1 OSC2 XT XT BIAS TST1 TST2 L0 L1 to LCD VDD1 VDD2 VDD3 C1 C2 L33 TST VDDI INTC P2 P3 P4 WDT VDDI P1 P1.0 P1.1 P1.2 P1.3 VDDI ADC P0 INT P4.3 INT INT IN0 CS0 RS0 CRT0 RT0 IN1 CS1 RS1 RT1 P2.0 P2.1 to CAPR P0.0 P0.1 P0.2 P0.3 INT 4/51 FEDL64P168-01 ML64P168 Semiconductor P0.3 P0.2 P0.1 P0.0 P1.3 P1.2 P1.1 P1.0 TST2 TST1 RESET XT XT VDD OSC1 OSC2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PIN CONFIGURATION (TOP VIEW) L0 1 64 L33 / P6.3 L1 2 63 L32 / P6.2 L2 3 62 L31 / P6.1 L3 4 61 L30 / P6.0 L4 5 60 L29 / P5.3 L5 6 59 L28 / P5.2 L6 7 58 L27 / P5.1 L7 8 57 L26 / P5.0 L8 9 56 L25 L9 10 55 L24 L10 11 54 L23 L11 12 53 L22 L12 13 52 L21 L13 14 51 L20 L14 15 50 L19 L15 16 49 L18 36 37 38 39 40 CS0 IN0 IN1 CS1 RS1 P3.2 RT1 35 VDD1 41 RS0 42 24 34 23 CRT0 P3.1 33 VDDI 32 43 VSS 22 RT0 P3.0 31 VDD2 VPP VDD3 44 30 45 21 29 20 P2.3 BD P2.2 P4.3 C1 28 46 P4.2 19 27 P2.1 P4.1 C2 26 L17 47 P4.0 48 18 25 17 P3.3 L16 P2.0 ( GP : QFP80-P-1420-0.80-BK ) 80-Pin Plastic QFP 5/51 FEDL64P168-01 ML64P168 Semiconductor L1 L0 P0.3 P0.2 P0.1 P0.0 P1.3 P1.2 P1.1 P1.0 TST2 TST1 RESET XT XT VDD OSC1 OSC2 L33 / P6.3 L32 / P6.2 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ( continued ) 80 PIN CONFIGURATION (TOP VIEW) L17 P2.0 16 45 C2 P2.1 17 44 C1 P2.2 18 43 VDD3 P2.3 19 42 VDD2 P3.0 20 41 VDDI 40 L18 46 VDD1 47 15 39 14 L16 RT1 L15 37 L19 38 48 RS1 13 CS1 L20 L14 36 49 IN1 12 35 L21 L13 IN0 L12 50 CS0 L22 11 34 L23 51 33 52 10 32 9 L11 RS0 L10 CRT0 L24 31 L9 RT0 L25 53 30 54 8 29 7 VSS L8 VPP L26 / P5.0 28 55 BD 6 27 L7 26 L27 / P5.1 P4.3 56 P4.2 5 25 L28 / P5.2 L6 24 L29 / P5.3 57 P4.1 58 4 P4.0 3 L5 P3.3 L4 23 L30 / P6.0 22 L31 / P6.1 59 21 60 2 P3.2 1 L3 P3.1 L2 ( GA : QFP80-P-1414-0.65-K ) 80-Pin Plastic QFP 6/51 FEDL64P168-01 ML64P168 Semiconductor PIN DESCRIPTIONS The basic functions of each pin of the ML64P168 is described in Table 1. A symbol with a slash ( / ) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For Type, “ - ” denotes a power supply pin, “ I ” an input pin, “O” an output pin, and “I/O” an inputoutput pin. Table 1 Function Power Supply Oscillation Test Reset Symbol Pin No. Pin Descriptions ( Basic Functions ) Type Description GP GA VSS 32 30 - 0V power supply VDD 67 65 - Positive power supply VDD1 42 40 - Bias output for driving LCD (+1.5 V, +1.2 V* ) VDD2 44 42 - Bias output for driving LCD (+3.0 V, +2.4 V* ) VDD3 45 43 - Bias output for driving LCD (+4.5 V, +3.6 V* ) VDDI 43 41 - Positive power supply for I/O port interface VPP 31 29 - Power supply (+12.5 V) for PROM writing C1 46 44 - C2 47 45 - Pins for connecting a capacitor for generating LCD driving bias XT 69 67 I XT 68 66 O OSC1 66 64 I OSC2 65 63 O TST1 71 69 I TST2 72 70 I RESET 70 68 I Low-speed clock oscillation input and output pins. Connect to a crystal ( 32.768 kHz ). High-speed clock oscillation input and output pins. Connect to an external resistor for oscillation ( ROS ). Input pins for testing. A pull-up resistor is internally connected to these pins. System reset input pin. Setting this pin to ″ L ″ level puts this device into a reset state. Then, setting this pin to ″ H ″ level starts executing an instruction from address 0000H. *When the voltage regulator for LCD driver is used. 7/51 FEDL64P168-01 ML64P168 Semiconductor Table 1 Function Symbol P0.0/ INT1/ CAPIN0 P0.1/ INT1/ CAPIN1 P0.2/ INT1 P0.3/ INT1/ CMP P1.0 Ports Pin Descriptions ( Basic Functions ) Pin No. GP GA 77 75 78 76 Description 4-bit input port ( Port 0 ) Selectable as pull-up resistor input, pull-down resistor input, or high impedance input by the port 01 control register ( P01CON ). I 79 77 80 78 73 71 P1.1 74 72 P1.2 75 73 P1.3 76 74 18 16 19 17 20 18 21 19 22 20 23 21 24 22 25 23 26 24 27 25 P2.0/ INT0 P2.1/ INT0 P2.2/ INT0 P2.3/ INT0 P3.0/ INT0 P3.1/ INT0 P3.2/ INT0 P3.3/ INT0/ SIN P4.0/ INT0/ SOUT P4.1/ INT0/ SPR P4.2/ INT0/ SCLK P4.3/ INT0/ MON Type ( continued ) O I/O I/O I/O 28 26 29 27 4-bit output port ( Port 1 ) Selectable as NMOS open drain output or CMOS output by the port 01 control register ( P01CON ). P1.0 is a high current drive output port. 4-bit input-output port ( Port 2 ) Fllowing can be specified for each bit by the port 2 control registers 0 to 3 ( P20CON to P23CON ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) NMOS open drain output or CMOS output 4-bit input-output port ( Port 3 ) Following can be specified for each bit by the port 3 control registers 0 to 3 ( P30CON to P33CON ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) NMOS open drain output or CMOS output 4-bit input-output port ( Port 4 ) Following can be specified for each bit by the port 4 control registers 0 to 3 ( P40CON to P43CON ). (1) input or output (2) pull-up/pull-down resistor input or high impedance input (3) NMOS open drain output or CMOS output 8/51 FEDL64P168-01 ML64P168 Semiconductor Table 1 Function Symbol Buzzer A/D Converter Pin Descriptions ( Basic Functions ) Pin No. Type GP GA BD 30 28 O RT0 33 31 O CRT0 34 32 O RS0 35 33 O CS0 36 34 O IN0 37 35 I RT1 41 39 O RS1 40 38 O CS1 39 37 O IN1 38 36 I ( continued ) Description Output pin for the buzzer driver. Resistance temperature sensor connection pin ( for channel 0 ) Resistance/capacitance temperature sensor connection pin ( for channel 0 ) Reference resistor connection pin ( for channel 0 ) Reference capacitor connection pin ( for channel 0 ) Input pin for RC oscillator circuit ( for channel 0 ) Resistance temperature sensor connection pin ( for channel 1 ) Reference resistor connection pin ( for channel 1 ) Reference capacitor connection pin ( for channel 1 ) Input pin for RC oscillator circuit ( for channel 1 ) 9/51 FEDL64P168-01 ML64P168 Semiconductor Table 1 Function LCD Driver Symbol Pin Descriptions ( Basic Functions ) Pin No. Type GP GA L0 1 79 O L1 2 80 O L2 3 1 O L3 4 2 O L4 5 3 O L5 6 4 O L6 7 5 O L7 8 6 O L8 9 7 O L9 10 8 O L10 11 9 O L11 12 10 O L12 13 11 O L13 14 12 O L14 15 13 O L15 16 14 O L16 17 15 O L17 48 46 O L18 49 47 O L19 50 48 O L20 51 49 O L21 52 50 O L22 53 51 O L23 54 52 O L24 55 53 O L25 56 54 O L26 / P5.0 57 55 O L27 / P5.1 58 56 O L28 / P5.2 59 57 O L29 / P5.3 60 58 O L30 / P6.0 61 59 O L31 / P6.1 62 60 O L32 / P6.2 63 61 O L33 / P6.3 64 62 O ( continued ) Description LCD segment and common signals output pins. LCD segment and common signals output pins. These pins can be configured to be output ports by a mask option. 10/51 FEDL64P168-01 ML64P168 Semiconductor Table 2 Function Symbol External Interrupt P2.0/ INT0 P2.1/ INT0 P2.2/ INT0 P2.3/ INT0 P3.0/ INT0 P3.1/ INT0 P3.2/ INT0 P3.3/ INT0 P4.0/ INT0 P4.1/ INT0 P4.2/ INT0 P4.3/ INT0 P0.0/ INT1 P0.1/ INT1 P0.2/ INT1 P0.3/ INT1 Capture trigger Serial port P0.0/ CAPIN0 Pin No. GP GA 18 16 19 17 20 18 21 19 22 20 23 21 24 22 25 23 26 24 27 25 28 26 29 27 77 75 78 76 79 77 80 78 77 75 Pin Descriptions ( Secondary Functions ) Type I P3.3/ SIN P4.0/ SOUT P4.1/ SPR P4.2/ SCLK Secondary functions of P2.0 to P2.3, P3.0 to P3.3, and P4.0 to P4.3: Level-triggered external 0 interrupt input pins. The change of input signal level causes an interrupt to occur. I I Secondary functions of P0.0 to P0.3: Level-triggered external 1 interrupt input pins. The change of input signal level causes an interrupt to occur. I I P0.1/ CAPIN1 Description 78 76 25 23 I 26 24 O 27 25 O 28 26 I/O Secondary functions of P0.0: This pin is assigned the capture circuit trigger input pin of CAPR0 function . Secondary functions of P0.1: This pin is assigned the capture circuit trigger input pin of CAPR1 function . Secondary functions of P3.3: This pin is assigned the data input of a serial port. Secondary functions of P4.0: This pin is assigned the data output of a serial port. Secondary functions of P4.1: This pin is assigned the ready output of a serial port. Secondary functions of P4.2: This pin is assigned the clock input-output of a serial port. 11/51 FEDL64P168-01 ML64P168 Semiconductor Table 2 Pin Descriptions ( Secondary Functions ) Pin No. Function Symbol RC Oscillation Monitor P4.3/ MON 29 27 O Battery Check P0.3/ CMP 80 78 I GP GA Type ( continued ) Description Secondary functions of P4.3: This pin is a monitor output of the RC oscillation clock for an A/D converter and a 700kHz RC oscillation clock for a system clock. Secondary functions of P0.3: This pin is an analog comparator input pin for battery check circuit. 12/51 FEDL64P168-01 ML64P168 Semiconductor MEMORY MAPS Program Memory ( PROM ) Test program area 1FFFH 32 bytes 1FE0H Contents of interrupt area 8160 bytes 003EH Interrupt area 0020H 003BH 0038H 0035H 0032H 002FH 002CH 0029H 0026H 0023H 0020H Watchdog interrupt External 0 interrupt Serial port interrupt External 1 interrupt A/D converter interrupt 256Hz interrupt 32Hz interrupt 16Hz interrupt 1Hz interrupt 0.1Hz interrupt CZP area 0010H 0000H Start address 8 bits Program Memory Map Address 0000H is the instruction execution start address by the system reset. The CZP area from address 0010H to address 001FH is the start address for the CZP subroutine of 1byte call instruction. The start address of interrupt subroutine is assigned to the interrupt address from address 0020H to 003DH. The user area has 8160 bytes of address 0000H to 1FDFH. No program can be stored in the test program area. 13/51 FEDL64P168-01 ML64P168 Semiconductor Data Memory The data memory area consists of 8 banks and each bank has 256 nibbles ( 256 × 4 bits ). The data RAM is assigned to BANK 6, BANK 7 and peripheral ports are assigned to BANK 0. 7FFH 780H 700H 6FFH BANK7 Data RAM area ( 256 nibbles ) BANK6 Data RAM area ( 256 nibbles ) Data / Stack area ( 128 nibbles ) 512 nibbles 600H 07FH Contents of 000H to 07FH Inaccessible area SFR area 100H 0FFH 080H 07FH Unused area BANK0 000H 000H 4 bits Data Memory Map Half the BANK 7 of Data RAM area ( 128 nibbles ) is shared by the stack area. The stack is a memory starting from address 7FFH toward the low-order addresses where 4 nibbles are used by Subroutine Call Instruction and 8 nibbles are used by an interrupt. The addresses 080H to 0FFH of BANK 0 are not assigned as the data memory, so access to these addresses has no effect. Moreover, it is impossible to access BANK 1 to BANK 5. 14/51 FEDL64P168-01 ML64P168 Semiconductor ABSOLUTE MAXIMUM RATINGS ( 1.5 V Spec. ) (VSS = 0V) Symbol Condition Rating Unit Power supply voltage 1 Parameter VDD1 Ta = 25°C -0.3 to + 2.0 V Power supply voltage 2 VDD2 Ta = 25°C -0.3 to + 4.0 V Power supply voltage 3 VDD3 Ta = 25°C -0.3 to + 5.5 V Power supply voltage 4 VDDI Ta = 25°C -0.3 to + 5.5 V Power supply voltage 5 VDD Ta = 25°C -0.3 to + 2.0 V Input voltage 1 VIN1 VDD input, Ta = 25°C -0.3 to VDD+ 0.3 V Input voltage 2 VIN2 VDDI input, Ta = 25°C -0.3 to VDDI+ 0.3 V Output voltage 1 VOUT1 VDD1 output, Ta = 25°C -0.3 to VDD1+ 0.3 V Output voltage 2 VOUT2 VDD2 output, Ta = 25°C -0.3 to VDD2+ 0.3 V Output voltage 3 VOUT3 VDD3 output, Ta = 25°C -0.3 to VDD3+ 0.3 V Output voltage 4 VOUT4 VDD output, Ta = 25°C -0.3 to VDD+ 0.3 V Output voltage 5 VOUT5 VDDI output, Ta = 25°C Ta = 0 to + 65°C QFP80-P-1420-0.80-BK Ta = 0 to + 65°C QFP80-P-1414-0.65-K - -0.3 to VDD+ 0.3 V 381 mW 334 mW -55 to + 150 °C Power Dissipation Storage temperature PD TSTG RECOMMENDED OPERATING CONDITIONS ( 1.5V Spec. ) (VSS = 0V) Parameter Operating Temperature* Operating Voltage* External 700kHz RC Oscillator Resistance* Crystal oscillation frequency* Symbol Condition Rating Unit Top - 0 to + 65 °C VDD,VDD1 - 1.45 to 1.70 V VDDI - 2.70 to 5.25 V ROS - 60 to 200 kΩ fXT - 30 to 35 kHz * : At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.37/51. 15/51 FEDL64P168-01 ML64P168 Semiconductor ELECTRICAL CHARACTERISTICS ( 1.5 V Spec. ) DC Characteristics ( 1.5 V Spec. ) (VSS=0V, VDD1=VDD=1.5V, VDDI=2.7V, Ta=0 to +65°C unless otherwise specified ) Parameter Symbol Condition VDD2 Voltage* VDD2 Ca, Cb, C12=0.1µF VDD3 Voltage* VDD3 Ca, Cb, C12=0.1µF VSTA Oscillation start time: within 5 seconds Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage Crystal Oscillation Stop Detection Time Internal Crystal Oscillator Capacitance External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance Internal 700kHz RC Oscillator Capacitance 700kHz RC Oscillation Frequency POR Generation Voltage POR Non-generation Voltage Battery Check Reference Voltage VRB Temperature Variation Notes: +100% -50% +100% -50% Min. Typ. Max. Unit 2.8 3.0 3.2 V 4.3 4.5 4.7 V 1.47 - - V VHOLD - 1.40 - - V TSTOP - 0.1 - 1000 ms CG - 10 15 20 pF 10 - 30 pF CGEX When external CG used CD - 10 15 20 pF COS - 8 12 16 pF 80 280 350 kHz 0 - 0.4 V 1.4 - 1.5 V 0.50 0.60 0.70 V - -2 - mV/°C fOSC VPOR1 VPOR2 VRB External resistor ROS=160kΩ VDD = 1.45 to 1.70V When VDD is between VPOR1 and 1.5V No POR when VDD is between VPOR2 and 1.5V Ta = 25°C Measuring Circuit 1 2 ∆VRB - 1.”POR” denotes Power On Reset. 2.”TSTOP” indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs. * : At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.37/51. 16/51 FEDL64P168-01 ML64P168 Semiconductor DC Characteristics ( 1.5V Spec. ) ( Continued ) (VSS=0V, VDD1=VDD=1.5V, VDDI=2.7V, Ta=0 to +65°C unless otherwise specified ) Parameter Symbol Supply current 1* IDD1 Supply current 2* IDD2 Supply current 3 IDD3 Supply current 4 IDD4 Supply current 5 Supply current 6 IDD5 IDD6 Condition CPU in halt state (700kHz RC oscillation stop) CPU in operating state (700kHz RC oscillation stop) CPU in operating state (700kHz RC oscillation in operation) Serial transfer, fSCK=300kHz, CPU in operating state (700kHz RC oscillation stop) CPU in halt state RT0=10kΩ (700kHz RC oscillation stop) RC oscillation for A/D converter is in operating RT0=2kΩ state Battery check circuit in operating state, CPU in operating state (700kHz RC oscillation stop) Min. Typ. Max . Unit - 2 5 µA - 15 30 µA - 200 300 µA - 60 100 µA - 150 230 µA - 600 900 µA - 25 125 µA Measuring Circuit 1 * : At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.37/51. 17/51 FEDL64P168-01 ML64P168 Semiconductor DC Characteristics (1.5 V Spec. ) ( Continued ) (VSS=0V, VDD1=VDD=1.5V, VDD2=3.0V, VDD3=4.5V, VDDI=2.7V, Ta=0 to +65°C unless otherwise specified ) Parameter Symbol Condition Min. Typ. Max. IOH1 VOH1 = VDDI - 0.5V -6.0 -1.7 -0.7 IOL1 VOL1 = 0.5V 2 5 20 IOH1S VDDI = 5.0V, VOH1S = VDDI - 0.5V -9 -3.0 -1 IOL1S VDDI = 5.0V, VOL1S = 0.5V 4 8 25 IOH2 VOH2 = VDDI - 0.5V -6.0 -2.0 -0.7 IOL2 VOL2 = 0.5V 0.7 2.0 6.0 IOH2S VDDI = 5.0V, VOH2S = VDDI - 0.5V -9 -3 -1 IOL2S VDDI= 5.0V, VOL2S = 0.5V 1 3 9 Output current 3 ( BD ) IOH3 VOH3 = VDD - 0.7V -1.8 -0.6 -0.1 IOL3 VOL3 = 0.7V 0.2 2 4 Output current 4 ( RT0, RT1, RS0, RS1, CRT0, CS0, CS1 ) IOH4 VOH4 = VDD - 0.1V -1.1 -0.6 -0.2 IOL4 VOL4 = 0.1V 0.3 0.6 1.1 Output current 5 ( When the pins L26 to L33 are configured as output ports ) IOH5 VOH5 = VDDI - 0.5V -1.5 -0.8 -0.15 IOL5 VOL5 = 0.5V 0.15 1.0 4 IOH5S VDDI = 5V, VOH5S = VDDI - 0.5V -2.0 -1.5 -0.2 IOL5S VDDI = 5V, VOL5S = 0.5V 0.2 3.0 5.0 IOH6 VOH6 = VDD - 0.5V -2.1 -0.7 -0.15 IOL6 VOL6 = 0.5V 0.15 0.7 2.1 IOH7 VOH7 = VDD3 - 0.2V - - -4 4 - - Output current 1 ( P1.0 ) Output current 2 ( P1.1 to P1.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Output current 6 ( OSC2 ) Output current 7 ( L0 to L33 ) Output Leakage Current ( P1.0 to P1.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) (RT0, RT1, RS0, RS1, CRT0, CS0, CS1 ) (VDD3 level) IOMH7 VOMH7 = VDD2 + 0.2V (VDD2 level) IOMH7S VOMH7S = VDD2 - 0.2V (VDD2 level) - - -4 IOML7 VOML7 = VDD1 + 0.2V (VDD1 level) 4 - - IOML7S VOML7S = VDD1 - 0.2V (VDD1 level) - - -4 IOL7 VOL7 = VSS + 0.2V 4 - - IOOH VOH = VDD - - 0.3 IOOL VOL = VSS -0.3 - - (VSS level) Unit Measuring Circuit mA 2 µA - 18/51 FEDL64P168-01 ML64P168 Semiconductor DC Characteristics (1.5 V Spec. ) ( Continued ) ( VSS=0V, VDD1=VDD=1.5V, VDD2=3.0V, VDD3=4.5V, VDDI=2.7V, Ta=0 to +65°C unless otherwise specified ) Parameter Input Current 1 ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Input Current 2 ( IN0, IN1 ) Input Current 3 ( OSC1 ) Symbol Condition IIH1 VIH1 = VDDI ( when pulled down ) IIL1 VIL1 = VSS ( when pulled up ) IIH1S VIH1 = VDDI = 5V ( when pulled down ) Min. Typ. Max. 30 90 300 -300 -90 -30 80 250 800 IIL1S VIL1 = VSS, VDDI = 5V ( when pulled up ) -800 -250 -80 IIH1Z VIH1 = VDDI ( in a high impedance ) 0 - 1 IIL1Z VIL1 = VSS (in a high impedance ) -1 - 0 IIH2 VIH2 = VDD ( when pulled down ) 2 8 60 IIH2Z VIH2 = VDD ( in a high impedance ) 0 - 1 IIL2Z VIL2 = VSS ( in a high impedance ) -1 - 0 IIL3 VIL3 = VSS ( when pulled up ) -60 -18 -5 IIH3Z VIH3 = VDD ( in a high impedance ) 0 - 1 IIL3Z VIL3 = VSS ( in a high impedance ) -1 - 0 Input Current 4 ( RESET, TST1, TST2 ) IIH4 VIH = VDD 0 - 1 IIL4 VIL4 = VSS -1.0 -0.3 -0.05 Input Voltage 1 ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) VIH1 1.2 - 1.5 - 0 - 0.3 VIH1S VIL1 VDDI = 5.0V - 4 - 5 VIL1S VDDI = 5.0V 0 - 1 Input Voltage 2 ( IN0, IN1, OSC1 ) VIH2 - 1.2 - 1.5 VIL2 - 0 - 0.3 Input Voltage 3 ( RESET, TST1, TST2 ) VIH3 - 1.2 - 1.5 VIL3 - 0 - 0.3 Unit µA Measuring Circuit 3 mA V 4 19/51 FEDL64P168-01 ML64P168 Semiconductor DC Characteristics (1.5 V Spec. ) ( Continued ) (VSS=0V, VDD1=VDD=1.5V, VDD2=3.0V, VDD3=4.5V, VDDI=2.7V, Ta=0 to +65°C unless otherwise specified ) Parameter Hysteresis Width ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Hysteresis Width ( RESET, TST1, TST2 ) Input Pin Capacitance ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Symbol Condition Min. Typ. Max. ∆VT1 - 0.05 0.1 0.3 0.25 1.0 1.5 ∆VT1S VDDI = 5.0V ∆VT2 - 0.05 0.1 0.3 CIN - - - 5 Unit Measuring Circuit V 4 pF 1 20/51 FEDL64P168-01 ML64P168 Semiconductor Measuring circuit 1 RT0 OSC1 CS0 RT0 RI0 CS0 IN0 XT ROS XT OSC2 C1 32.768kHz Crystal C12 C2 VSS VDD A VDD1 CA VDD2 V CB VDD3 V CC VDDI CA,CB,CC,C12 ROS RT0 CS0 RI0 V : : : : : 0.1µF 160kΩ 10kΩ/2kΩ 820pF 10kΩ Measuring circuit 2 *1 VIL INPUT OUTPUT VIH VSS VDD1 VDD2 VDD3 VDD *2 A VDDI 21/51 FEDL64P168-01 ML64P168 Semiconductor OUTPUT Measuring circuit 3 INPUT *3 A VSS VDD1 VDD2 VDD3 VDD VDDI OUTPUT Measuring circuit 4 *3 VIL INPUT VIH VSS VDD1 VDD2 VDD3 VDD Waveform Monitoring VDDI *1 Input logic circuit to determine the specified measuring conditions. *2 Measured at the specified output pins. *3 Measured at the specified input pins. 22/51 FEDL64P168-01 ML64P168 Semiconductor A/D Converter Characteristics (1.5 V Spec. ) Parameter Symbol Resistor for Oscillation RS0, RS1, RT0, RT0-1, RT1 Input Current Limiting Resistor RI0, RI1 Oscillation Frequency RS•RT Oscillation Frequency Ratio (*) ( VSS=0V, VDD1=VDD=1.5V, VDDI=2.7V, Ta=0 to +65°C unless otherwise specified ) MeasurCondition Min. Typ. Max. Unit ing Circuit CS0, CT0, CS1 ≥ 740pF - 2 - - kΩ 1 10 - kΩ fOSC1 Resistor for oscillation =2 kΩ 165 221 256 kHz fOSC2 Resistor for oscillation =10 kΩ 41.8 52.2 60.6 kHz fOSC3 Resistor for oscillation =200 kΩ 2.55 3.04 3.53 kHz Kf1 RT0, RT0-1, RT1 = 2 kΩ 3.89 4.18 4.35 - Kf2 RT0, RT0-1, RT1 = 10 kΩ 0.990 1.000 1.010 - Kf3 RT0, RT0-1, RT1 = 200 kΩ 0.0561 0.0584 0.0637 - 5 * Kfx is the ratio of the oscillation frequency by a sensor resistor to the oscillation frequency by a reference resistor in the same condition. Kfx= fOSCX(RT0 - CS0 Oscillation) fOSCX(RS0 - CS0 Oscillation) , (X = 1, 2, 3) fOSCX(RT0-1 - CS0 Oscillation) fOSCX(RS0 - CS0 Oscillation) , fOSCX(RT1 - CS1 Oscillation) fOSCX(RS1 - CS1 Oscillation) 23/51 FEDL64P168-01 ML64P168 Semiconductor Measuring circuit 5 Oscillation Mode Designation RT1 RS1 CS1 IN1 RESET TST1 TST2 P0.0 P0.1 P0.2 P0.3 VSS IN0 CS0 RS0 RT0 RT0-1 CT0 RS0 CS0 (CROSC0) RI0 RI1 CS1 RS1 RT1 (CROSC1) CRT0 RT0 P4.3 D.U.T VDD VDDI Frequency Measurement (fOSCX) RT0,RT0-1,RT1=2kΩ/10kΩ/200kΩ RS0,RS1=10kΩ RI0,RI1=10kΩ CS0,CT0,CS1=820pF 24/51 FEDL64P168-01 ML64P168 Semiconductor AC Characteristics (1.5 V Spec. ) ( Serial Interface ) ( VSS=0v, VDD=1.5V , VDDI=2.7V, Ta=0 to +65°C unless otherwise specified Parameter ) Symbol Condition Min. Typ. Max. Unit SCLK Input Fall Time tf - - 15 50 ns SCLK Input Rise Time tr - - 15 50 ns SCLK Input “L” Level Pulse Width tCWL - 0.8 - - µs SCLK Input “H” Level Pulse Width tCWH - 0.8 - - µs SCLK Input Cycle Time tCYC 2.0 - - µs - 30.5 - µs - 1.43 - µs SCLK Output Cycle Time tCYC1(O) SCLK Output Cycle Time tCYC2(O) CPU is operating at 32.768kHz CPU is operating at 700kHz SOUT Output Delay Time tDDR - - - 0.4 µs SIN Input Setup Time tDS - 0.5 - - µs SIN Input Hold Time tDH - 0.8 - - µs Synchronous communication timing ( “H” level = 4.0V, “L” level = 1.0V ) tCYC 5V SCLK (P4.2) tr tf tCWH tDDR tCWL tDDR 5V SOUT (P4.0) tDS SIN (P3.3) tDH tDS 5V 25/51 FEDL64P168-01 ML64P168 Semiconductor ABSOLUTE MAXIMUM RATINGS (3.0 V Spec. ) (VSS = 0V) Symbol Condition Rating Unit Power supply voltage 1 Parameter VDD1 Ta = 25°C -0.3 to + 2.0 V Power supply voltage 2 VDD2 Ta = 25°C -0.3 to + 4.0 V Power supply voltage 3 VDD3 Ta = 25°C -0.3 to + 5.5 V Power supply voltage 4 VDDI Ta = 25°C -0.3 to + 5.5 V Power supply voltage 5 VDD Ta = 25°C -0.3 to + 4.0 V Input voltage 1 VIN1 VDD input, Ta = 25°C -0.3 to VDD + 0.3 V Input voltage 2 VIN2 VDDI input, Ta = 25°C -0.3 to VDDI + 0.3 V Output voltage 1 VOUT1 VDD1 output, Ta = 25°C -0.3 to VDD2+ 0.3 V Output voltage 2 VOUT2 VDD2 output, Ta = 25°C -0.3 to VDD3+ 0.3 V Output voltage 3 VOUT3 VDD3output, Ta = 25°C -0.3 to VDD+ 0.3 V Output voltage 4 VOUT4 VDD output, Ta = 25°C -0.3 to VDD+ 0.3 V Output voltage 5 VOUT5 VDDI output, Ta = 25°C Ta = 0 to + 65°C QFP80-P-1420-0.80-BK Ta = 0 to + 65°C QFP80-P-1414-0.65-K - -0.3 to VDD+ 0.3 V 381 mW 334 mW -55 to + 150 °C Power Dissipation Storage temperature PD TSTG RECOMMENDED OPERATING CONDITIONS ( 3.0V Spec. ) (VSS = 0V) Parameter Operating Temperature*1 Operating Voltage*1 External 700kHz RC oscillator Resistance*1 Crystal oscillation frequency*1 Symbol Condition Rating Unit Top - 0 to + 65 °C VDD - 2.7 to 3.5 V VDDI - VDD to 5.25 V ROS - 60 to 200 kΩ fXT - 30 to 66 kHz *1: At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.37/51. 26/51 FEDL64P168-01 ML64P168 Semiconductor ELECTRICAL CHARACTERISTICS ( 3.0V Spec. ) DC Characteristics ( 3.0V Spec. ) (VSS=0V, VDD2=VDDI=VDD=3.0V, Ta=0 to +65°C unless otherwise specified ) Parameter Symbol Condition VDD1 Voltage* VDD1 Ca, Cb, C12=0.1µF VDD3 Voltage* VDD3 Ca, Cb, C12=0.1µF VSTA Oscillation start time: within 5 seconds Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage Crystal Oscillation Stop Detection Time Internal Crystal Oscillator Capacitance External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance Internal 700kHz RC Oscillator Capacitance 700kHz RC Oscillation Frequency POR Generation Voltage POR Non-generation Voltage Battery Check Reference Voltage VRB Temperature Variation Notes: +100% -50% +100% -50% Min. Typ. Max. Unit 1.3 1.5 1.7 V 4.3 4.5 4.7 V 2.7 - - V VHOLD - 2.7 - - V TSTOP - 0.1 - 1000 ms CG - 10 15 20 pF 10 - 30 pF CGEX When external CG used CD - 10 15 20 pF COS - 8 12 16 pF 600 700 1000 kHz 0 - 0.7 V 2.7 - 3 V 0.50 0.60 0.70 V - -2 - mV/°C fOSC VPOR1 VPOR2 VRB External resistor ROS=60kΩ VDD = 2.7 to 3.5V When VDD is between VPOR1 and 3.0V No POR when VDD is between VPOR2 and 3.0V Ta = 25°C Measuring Circuit 1 2 ∆VRB 1.”POR” denotes Power On Reset. 2.”TSTOP” indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs. *: At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.37/51. 27/51 FEDL64P168-01 ML64P168 Semiconductor DC Characteristics ( 3.0V Spec. ) ( Continued ) (VSS=0V, VDD2=VDDI=VDD=3.0V, Ta=0 to +65°C unless otherwise specified ) Parameter Symbol Supply current 1* IDD1 Supply current 2* IDD2 Supply current 3 IDD3 Supply current 4 IDD4 Supply current 5 IDD5 Supply current 6 IDD6 Condition CPU in halt state (700kHz RC oscillation stop) CPU in operating state (700kHz RC oscillation stop) CPU in operating state (700kHz RC oscillation in operation) Serial transfer, fSCK=300kHz, CPU in operating state (700kHz RC oscillation stop) CPU in halt state (700kHz RC oscillation stop) RT0=10kΩ RC oscillation for A/D converter is in operating state RT0=2kΩ Battery check circuit in operating state, CPU in operating state (700kHz RC oscillation stop) Min. Typ. Max. Unit - 7 12 µA - 35 50 µA - 800 1400 µA - 40 70 µA - 300 450 µA - 1200 1800 µA - 55 150 µA Measuring Circuit 1 *: At Non-regulated LCD driver. In case of select a voltage regulated LCD driver, see P.37/51. 28/51 FEDL64P168-01 ML64P168 Semiconductor DC Characteristics (3.0 V Spec. ) ( Continued ) ( VSS=0V, VDD1=1.5V, VDD2=VDDI=VDD=3.0V, VDD3=4.5V, Ta=0 to +65°C unless otherwise specified ) Parameter Symbol Condition Min. Typ. Max. IOH1 VOH1 = VDDI - 0.5V -6.0 -1.7 -0.7 IOL1 VOL1 = 0.5V 2 5 20 IOH1S VDDI = 5.0V, VOH1S = VDDI - 0.5V -9 -3 -1 IOL1S VDDI = 5.0V, VOL1S = 0.5V 4 8 25 IOH2 VOH2 = VDDI - 0.5V -6.0 -2.0 -0.7 IOL2 VOL2 = 0.5V 0.7 2.0 6.0 IOH2S VDDI = 5.0V, VOH2S = VDDI - 0.5V -9 -3 -1 IOL2S VDDI = 5.0V, VOL2S = 0.5V 1 3 9 Output current 3 ( BD ) IOH3 VOH3 = VDD - 0.7V -6.0 -2.0 -0.7 IOL3 VOL3 = 0.7V 0.7 6.0 10.0 Output current 4 ( RT0, RT1, RS0, RS1, CRT0, CS0, CS1 ) IOH4 VOH4 = VDD - 0.1V -2.5 -0.8 -0.3 IOL4 VOL4 = 0.1V 0.7 1.3 2.5 Output current 5 ( When the pins L26 to L33 are configured as output ports ) IOH5 VOH5 = VDDI - 0.5V -1.5 -0.8 -0.15 IOL5 VOL5 = 0.5V 0.15 2.0 4.0 IOH5S VDDI = 5V, VOH5S = VDDI - 0.5V -2.0 -1.5 -0.2 IOL5S VDDI = 5V, VOL5S = 0.5V 0.2 3.0 5.0 IOH6 VOH6 = VDD - 0.5V -4.0 -0.8 -0.3 IOL6 VOL6 = 0.5V 0.7 3.0 6.0 IOH7 VOH7 = VDD3 - 0.2V - - -4 4 - - Output current 1 ( P1.0 ) Output current 2 ( P1.1 to P1.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Output current 6 ( OSC2 ) Output current 7 ( L0 to L33 ) Output Leakage Current ( P1.0 to P1.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) (RT0, RT1, RS0, RS1, CRT0, CS0, CS1 ) (VDD3 level) IOMH7 VOMH7 = VDD2 + 0.2V (VDD2 level) IOMH7S VOMH7S = VDD2 - 0.2V (VDD2 level) - - -4 IOML7 VOML7 = VDD1 + 0.2V (VDD1 level) 4 - - IOML7S VOML7S = VDD1 - 0.2V (VDD1 level) - - -4 IOL7 VOL7 = VSS + 0.2V 4 - - IOOH VOH = VDD - - 0.3 IOOL VOL = VSS -0.3 - - (VSS level) Unit Measuring Circuit mA 2 µA - 29/51 FEDL64P168-01 ML64P168 Semiconductor DC Characteristics (3.0 V Spec. ) ( Continued ) (VSS=0V, VDD1=1.5V, VDD2=VDDI=VDD=3.0V, VDD3=4.5V, Ta=0 to +65°C unless otherwise specified ) Parameter Input Current 1 ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Input Current 2 ( IN0, IN1 ) Input Current 3 ( OSC1 ) Symbol Condition IIH1 VIH1 = VDDI ( when pulled down ) IIL1 VIL1 = VSS ( when pulled up ) IIH1S Min. Typ. Max. 30 90 300 -300 -90 -30 VIH1 = VDDI = 5V ( when pulled down ) 80 250 800 IIL1S VIL1 = VSS, VDD = 5V ( when pulled up ) -800 -250 -80 IIH1Z VIH1 = VDDI ( in a high impedance ) 0 - 1 IIL1Z VIL1 = VSS (in a high impedance ) -1 - 0 IIH2 VIH2 = VDD ( when pulled down ) 30 90 300 IIH2Z VIH2 = VDD ( in a high impedance ) 0 - 1 IIL2Z VIL2 = VSS ( in a high impedance ) -1 - 0 IIL3 VIL3 = VSS ( when pulled up ) -300 -110 -10 IIH3Z VIH3 = VDD ( in a high impedance ) 0 - 1 IIL3Z VIL3 = VSS ( in a high impedance ) -1 - 0 Input Current 4 ( RESET, TST1, TST2 ) IIH4 VIH4 = VDD 0 - 1 IIL4 VIL4 = VSS -3.00 -1.50 -0.75 Input Voltage 1 ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) VIH1 2.4 - 3.0 - 0 - 0.6 VIH1S VIL1 VDDI = 5.0V - 4 - 5 VIL1S VDDI = 5.0V 0 - 1 Input Voltage 2 ( IN0, IN1, OSC1 ) VIH2 - 2.4 - 3.0 VIL2 - 0 - 0.6 Input Voltage 3 ( RESET, TST1, TST2 ) VIH3 - 2.4 - 3.0 VIL3 - 0 - 0.6 Unit µA Measuring Circuit 3 mA V 4 30/51 FEDL64P168-01 ML64P168 Semiconductor DC Characteristics (3.0 V Spec. ) ( Continued ) (VSS=0V, VDD1=1.5V, VDD2=VDDI=VDD=3.0V, VDD3=4.5V, Ta=0 to +65°C unless otherwise specified) Parameter Hysteresis Width ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Hysteresis Width ( RESET, TST1, TST2 ) Input Pin Capacitance ( P0.0 to P0.3 ) ( P2.0 to P2.3 ) ( P3.0 to P3.3 ) ( P4.0 to P4.3 ) Symbol Condition Min. Typ. Max. ∆VT1 - 0.2 0.5 1.0 0.25 1.00 1.50 ∆VT1S VDDI=5.0V ∆VT2 - 0.2 0.5 1.0 CIN - - - 5 Unit Measuring Circuit V 4 pF 1 31/51 FEDL64P168-01 ML64P168 Semiconductor Measuring circuit 1 RT0 OSC1 CS0 RT0 RI0 CS0 IN0 XT ROS XT OSC2 C1 32.768kHz Crystal C12 C2 VSS VDD A VDD1 CA VDD2 V CB VDD3 V CC VDDI CA,CB,CC,C12 ROS RT0 CS0 RI0 V : : : : : 0.1µF 60kΩ 10kΩ/2kΩ 820pF 10kΩ Measuring circuit 2 *1 VIL INPUT OUTPUT VIH VSS VDD1 VDD2 VDD3 VDD *2 A VDDI 32/51 FEDL64P168-01 ML64P168 Semiconductor OUTPUT Measuring circuit 3 INPUT *3 A VSS VDD1 VDD2 VDD3 VDD VDDI OUTPUT Measuring circuit 4 *3 VIL INPUT VIH VSS VDD1 VDD2 VDD3 VDD Waveform Monitoring VDDI *1 Input logic circuit to determine the specified measuring conditions. *2 Measured at the specified output pins. *3 Measured at the specified input pins. 33/51 FEDL64P168-01 ML64P168 Semiconductor A/D Converter Characteristics (3.0 V Spec. ) Parameter Resistor for Oscillation Input Current Limiting Resistor Oscillation Frequency RS•RT Oscillation Frequency Ratio(*) ( VSS=0V, VDDI=VDD=3.0V, Ta=0 to +65°C unless otherwise specified) MeasurCondition Min. Typ. Max. Unit ing Circuit Symbol RS0, RS1, RT0, RT0-1, RT1 RI0, RI1 fOSC1 CS0, CT0, CS1 ≥ 740pF - 1 - - kΩ 1 10 - kΩ Resistor for oscillation =2 kΩ 200 239 277 kHz fOSC2 Resistor for oscillation =10 kΩ 46.5 55.4 64.3 kHz fOSC3 Resistor for oscillation =200 kΩ 2.79 3.32 3.85 kHz Kf1 RT0, RT0-1, RT1 = 2 kΩ 4.272 4.380 4.490 - Kf2 RT0, RT0-1, RT1 = 10 kΩ 0.990 1.000 1.010 - Kf3 RT0, RT0-1, RT1 = 200 kΩ 0.0573 0.0616 0.0659 - 5 * Kfx is the ratio of the oscillation frequency by a sensor resistor to the oscillation frequency by a reference resistor in the same condition. Kfx= fOSCx(RT0 - CS0 Oscillation) fOSCx(RS0 - CS0 Oscillation) (x=1, 2, 3) fOSCx(RT0-1 - CS0 Oscillation) , fOSCx(RS0 - CS0 Oscillation) fOSCx(RT1 - CS1 Oscillation) , fOSCx(RS1 - CS1 Oscillation) 34/51 FEDL64P168-01 ML64P168 Semiconductor Measuring circuit 5 Oscillation Mode Designation RT1 RS1 CS1 IN1 RESET TST1 TST2 P0.0 P0.1 P0.2 P0.3 VSS IN0 CS0 RS0 RT0 RT0-1 CT0 RS0 CS0 (CROSC0) RI0 RI1 CS1 RS1 RT1 (CROSC1) CRT0 RT0 P4.3 D.U.T VDD VDDI Frequency Measurement (fOSCX) RT0,RT0-1,RT1=2kΩ/10kΩ/200kΩ RS0,RS1=10kΩ RI0,RI1=10kΩ CS0,CT0,CS1=820pF 35/51 FEDL64P168-01 ML64P168 Semiconductor AC Characteristics ( 3.0V Spec. ) ( Serial Interface ) ( VSS=0V, VDD2=VDD=3.0V, VDDI=5.0V , Ta=0 to +65°C unless otherwise specified) Parameter Symbol SCLK Input Fall Time SCLK Input Rise Time SCLK Input “L” Level Pulse Width SCLK Input “H” Level Pulse Width SCLK Input Cycle Time tf tr tCWL tCWH tCYC SCLK Output Cycle Time tCYC1(O) SCLK Output Cycle Time SOUT Output Delay Time SIN Input Setup Time SIN Input Hold Time tCYC2(O) tDDR tDS tDH Condition CPU is operating at 32.768kHz CPU is operating at 700kHz - Min. Typ. Max. Unit 0.8 0.8 2.0 15 15 - 50 50 - ns ns µs µs µs - 30.5 - µs 0.5 0.8 1.43 - 0.4 - µs µs µs µs Synchronous communication timing ( “H” level = 4.0V, “L” level = 1.0V ) tCYC 5V SCLK (P4.2) tr tf tCWH tDDR tCWL tDDR 5V SOUT (P4.0) tDS SIN (P3.3) tDH tDS 5V 36/51 FEDL64P168-01 ML64P168 Semiconductor RECOMMENDED OPERATING CONDITIONS ( When Voltage Regulator for LCD Driver Used ) (VSS = 0V) Parameter Symbol Condition Rating Unit Operating Temperature Top - 0 to + 65 °C Operating Voltage VDD - 2.7 to 3.5 V Crystal oscillation frequency fXT - 30 to 66 kHz ELECTRICAL CHARACTERISTICS ( When Voltage Regulator for LCD Driver Used ) DC Characteristics (VSS=0V, VDD=3.0V, Ta=0 to +65°C unless otherwise specified ) Parameter VDD1 Voltage Symbol Condition VDD1 VDD=2.7 to 3.5, Ta=25°C Min. Typ. Max. Unit 1.00 1.2 1.4 V - -4 - mV/°C ∆VDD1 - VDD2 Voltage VDD2 VDD=2.7 to 3.5 Typ. - 0.1 2×VDD1 Typ. + 0.1 VDD3 Voltage VDD3 VDD=2.7 to 3.5 Typ. - 0.2 3×VDD1 Typ. + 0.2 Supply Current 1 IDD1 VDD=1.5V , CPU in halt state - 2 5 VDD=3.0V, CPU in halt state - 7 12 VDD=1.5V, CPU in operating state - 15 30 VDD=3.0V, CPU in operating state - 35 50 Supply Current 2 Notes: IDD2 Measuring Circuit V 1 µA The other electrical characteristics are the same as those for the 1.5V and 3.0V specifications. 37/51 FEDL64P168-01 ML64P168 Semiconductor Power Supply Circuit VDDI VDD C1 ML64P168 C2 VDD3 VDD2 CS CI C12 CC CB VDD1 1.5V VSS 2.7 to 5V ML64P168 1.5V Version VDDI VDD C1 ML64P168 C2 VDD3 VDD2 VDD1 VSS CS CI C12 CC CB 1.5V CA 2.7 to 5V ML64P168 1.5V Version (The LCD bias is regulated.) VDDI VDD C1 ML64P168 C2 VDD3 CS CI C12 CC VDD2 VDD1 3.0V CA VSS ML64P168 3.0V Version VDDI VDD C1 ML64P168 C2 VDD3 VDD2 VDD1 VSS CS CI C12 CC CB 3.0V CA ML64P168 3.0V Version (The LCD bias is regulated.) Note:CA,CB,CC,CS,CI,C12:0.1µF +100% -50% 38/51 FEDL64P168-01 ML64P168 Semiconductor PROM MODE ABSOLUTE MAXIMUM RATINGS (VSS = 0V) Parameter Symbol Condition Rating Unit PROM power supply voltage VCC VCC=VDD, Ta=25°C -0.3 to + 6.7 V Program voltage VPP Ta = 25°C -0.3 to + 14.0 V PROM input voltage VI VCC system input, Ta=25°C -0.3 to VCC + 0.3 V PROM output voltage VO VCC system output, Ta=25°C -0.3 to VCC + 0.3 V TSTG - -55 to + 150 °C Storage temperature RECOMMENDED OPERATING CONDITIONS (VSS = 0V) Symbol Condition Rating Unit Operating Temperature Parameter Top - 0 to + 65 °C VCC power supply voltage VCC VCC=VDD=VDDI 4.75 to 5.25 V VPP power supply voltage VPP Input voltage In read 4.75 to 5.25 V In write 12.0 to 13.0 V VIH VCC=VDD=VDDI 4 to VCC V VIL - 0 to 1 V 39/51 FEDL64P168-01 Semiconductor ML64P168 READ OPERATION ( PROM MODE ) DC Characteristics (VDD=VPP=5.0V±5%, Ta=25 ±5°C unless otherwise specified ) Parameter VCC power supply current (standby) VCC power supply current (operation) Symbol ICC1 ICC2 VIH Input voltage Condition VCC = VDD CE=VIH VCC = VDD CE=VIL VCC = VDD Typ. Max. Unit - - 35 mA - - 100 mA 4 - VCC V 0 - 1 V IOH VCC = VDD VOH = VCC - 0.5V -2.0 -0.7 -0.2 mA IOL VOL = 0.5V 0.2 0.7 2.0 mA - VIL Output voltage Min. AC Characteristics (VCC =5.0V±5%, VPP=VCC, Ta=0 to 65°C Parameter Address access time CE access time OE access time Output disable time unless otherwise specified) Symbol Condition Min. Typ. Max. Unit tACC tCE tOE tDF OE=CE=VIL OE=VIL CE=VIL CE=VIL 0 - 120 120 50 40 ns ns ns ns Measurement conditions: Input pulse level Input rise / fall time Timing judgement level 0.45 to 4.55V 5ns Input 0.8V, 2V / Output 0.8V , 2V Timing chart Address Input CE tCE OE tOE tDF tACC Data output 40/51 FEDL64P168-01 Semiconductor ML64P168 WRITE OPERATION ( PROM MODE ) DC Characteristics ( VSS=0V, VDD=5.0V ± 5%, VPP=12.5V ± 5V, Ta=25 ± 5°C unless otherwise specified ) Parameter Symbol Condition Min. Typ. Max. Unit VPP power supply current IPP CE=VIL - - 50 mA VCC power supply current ICC VCC = VDD - - 100 mA VIH VCC = VDD 4 - VCC V Input voltage 0 - 1 V IOH VCC = VDD VOH = VCC - 0.5V -2.0 -0.7 -0.2 mA IOL VOL = 0.5V 0.2 0.7 2.0 mA - VIL Output voltage AC Characteristics ( VSS=0V, VDD=5.0V ± 5%, VPP=12.5 ± 5V, Ta=25 ± 5°C Parameter unless otherwise specified ) Symbol Condition Min. Typ. Max. Unit Address set-up time OE set-up time Data set-up time Address hold time Data hold time OE output floating delay time VPP power supply set-up time tAS tOES tDS tAH tDH tDEP tVS 2 2 2 0 2 0 2 - 130 - µs µs µs µs µs ns µs Initial program pulse width tPW 0.95 1.0 1.05 ms Additional program pulse width tOPW 2.85 - 78.75 ms OE output effective delay time tOE VDD=VDDI 6V ± 0.25V VDD1=VDD2 6V ± 0.25V - - - 150 ns Measurement conditions: Input pulse level Input rise / fall time Timing judgement level 0.45 to 4.55V Less than 20ns Input 0.8V, 2V / Output 0.8V , 2V 41/51 FEDL64P168-01 Semiconductor ML64P168 Program timing chart Address Input Address N tAS Data Input/Output tAH Data Input Data Output tOE tDH tDS tDEP VPP tVS CE tPW tOES tOPW OE 42/51 FEDL64P168-01 Semiconductor ML64P168 FUNCTIONAL DESCRIPTION CPU Peripheral Function ∙ A/D converter ( ADC ) The ML64P168 has a built-in two-channel RC oscillation A/D converter. The A/D converter is composed of a two-cannel oscillation circuit, Counter A ( CNTA0-4, a 4.8-digit decade counter ), Counter B ( CNTB0-3, a 14-bit binary counter ), and A/D Converter Control Registers 0 and 1 ( ADCON0, ADCON1 ). By counting oscillation frequencies that vary depending on a resistor or capacitor connected to the RC oscillation circuit, the A/D converter converts resistance values or capacitance values to corresponding digital values. By using a thermistor or humidity sensor as a resistance, a thermometer or a hygrometer can be constructed. By applying a separate sensor to each cannel of the 2-channel RC oscillation circuit, it is also possible to extend measure ranges or measure at two places. ∙ Serial port ( SIOP ) The ML64P168 has an 8-bit synchronous serial port. Receive/transmit operation of the serial port is performed simultaneously and the serial transfer clock can select either internal or external mode. Direction of transfer data can be big endian or little endian. Each pin of the serial port is assigned as secondary functions of P3.3 and P4.0 to P4.2. Setting each bit of SIN,SOUT, SPR and SCLK of P33CON and P40CON to P42CON to “1” makes each pin valid. ∙ LCD driver ( LCD ) The ML64P168 has a built-in LCD driver for 34 outputs. The LCD driver consists of 31× 4-bit display registers ( DSPR0-30 ), the Display Control Register ( DSPCON ), a 34-output LCD driver circuit, and a bias generation circuit ( BIAS ). The bias generation circuit for LCD driver ( BIAS ) generates bias voltages for the LCD driver by rising or dropping the power supply voltage by externally installing capacitors. Alternatively, it generates bias voltages by rising the constant voltage ( VDD1 = 1.2V ) generated by the voltage regulator for LCD driver. Which way is to be used is specified by mask option. There are three types of driving methods: 1/4duty, 1/3duty and 1/2duty. Software selects the duty mode. A mask option can select either a common driver or a segment driver for each LCD driver pin. A mask option can also specify assignment of each bit of the display register to each segment. All the display registers must be selected by a mask option. L26 to L33 of the LCD driver can be configured to be output ports by a mask option. The relationship between the duty, the bias method, and the maximum segment number follows: 1/4duty, 1/3 bias method ----------- 120 segments 1/3duty, 1/3 bias method ----------- 93 segments 1/2duty, 1/2 bias method ----------- 64 segments ∙ Buzzer driver ( BD ) The ML64P168 has a built-in buzzer driver with 15 buzzer output frequencies and 4 buzzer output modes. Each buzzer output is selected by the Buzzer Control Register ( BDCON ) and the Buzzer Frequency Control Register ( BFCON ). 43/51 FEDL64P168-01 Semiconductor ML64P168 ∙ Capture circuit ( CAPR ) The ML64P168 captures 32Hz to 256Hz output of the time base counter at the falling of Port 0.0 or Port 0.1 ( P0.0 or P0.1 ) to “L” level when the pull-up resistor input is chosen, or at the rising to “H” level when the pull-down resistor input is chosen. The capture circuit is composed of the Capture Control Register ( CAPCON ) and the Capture Registers ( CAPR0, CAPR1 ) that fetch output from the time base counter. ∙ Watchdog timer ( WDT ) The ML64P168 has a built-in watchdog timer to detect CPU malfunction. The watchdog timer is composed of a 6-bit watchdog timer counter ( WDTC ) to count a 16Hz output and a watchdog timer control register ( WDTCON ) to reset WDTC. ∙ Clock generation circuit ( 2CLK ) The clock generation circuit ( 2CLK ) in the ML64P168 contains a 32.768kHz crystal oscillation circuit, a 700kHz RC oscillation circuit, and a clock control port. This circuit generates the system clock ( CLK ) and the time base clock ( 32.768kHz ). The system clock drives the CPU while the time base clock drives the time base counter and the buzzer driver. Via the contents of the Frequency Control Register ( FCON ), the system clock can be switched between 32.768kHz ( the output of the crystal oscillation circuit ) and 700kHz ( the output of the RC oscillation circuit ). Note: The oscillation frequency of the RC oscillation circuit varies depending on the value of an external resistor ( ROS ), operating power supply voltage ( VDD ), and ambient temperatures (Ta). ∙ Time base counter ( TBC ) The ML64P168 has a built-in time base counter ( TBC ) that generates clocks to be supplied to internal peripheral circuit. The time base counter is composed of 15 binary counters, and a 1/10 frequency dividing circuit. The count clock of the time base is driven by the oscillation clock ( 32.768kHz ) of the crystal oscillation circuit. The output of the time base counter is used for the buzzer driver, the system reset circuit, the watchdog timer, the time base interrupt, the sampling clocks of each port, and the capture circuit. ∙ I/O port Input-output ports ( P2, P3, P4 ) : 3 ports × 4bits Pull-up ( pull-down ) resistor input or high-impedance input, CMOS output or NMOS open drain output: these can be specified for each bit; external 0 interrupt Input port ( P0 ) : 1 port × 4bits Pull-up ( pull-down ) resistor input or high-impedance input; external 1 interrupt Output port ( P1 ) : 1 port × 4bits CMOS output or NMOS open drain output 44/51 FEDL64P168-01 Semiconductor ML64P168 ∙ Interrupt ( INTC ) The ML64P168 has 10 interrupt sources ( 10 vector address ), of which two are external interrupts from ports and eight are internal interrupts. Of the ten interrupt sources, only the watchdog timer interrupt cannot be disabled ( non-maskable interrupt ). The other nine interrupts are controlled by the master interrupt enable flag ( MI ) and the interrupt enable registers ( IE0, IE1, and IE2 ). When an interrupt condition is met, the CPU branches to a vector address corresponding to the interrupt source. ∙ Battery check circuit ( BC ) The battery check circuit ( BC ) detects the level of the supply voltage by comparing the voltage generated by an external supply-voltage dividing resistor ( RBLD ) with the internal reference voltage ( Vrb ). 45/51 Switch matrix ( 4 x 4 ) CGEX 32.768 kHz ROS P0.3 RBLD XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 OSC2 OSC1 L0 ML 64P168-xxxGA/GP ML 64P168-xxx (1.5V Spec.) L33 LCD IN1 CS1 RS1 RT1 BD Buzzer RS0 CS0 RI0 IN0 CS0 RS0 CRT0 RT0 RT1RS1CS1 RI1 RT0 TST2 TST1 VDD1 VSS VPP VDD3 VDD2 VDDI VDD C2 C1 C12 CB CC CS CI 5V - 5V Interface - Temperature measurement by two thermistors - Battery check circuit is used. - CGEX of crystal oscillator : External 1.5V FEDL64P168-01 Semiconductor ML64P168 APPLICATION CIRCUITS (1.5 V Spec. ) P4.3 P4.2 P4.1 P4.0 P3.3 P3.1 1.5V Spec. Application Circuit ( Voltage Regulator for LCD Driver not Used ) 46/51 Switch matrix ( 4 x 4 ) CGEX 32.768 kHz ROS RBLD XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3 OSC2 OSC1 L0 ML 64P168-xxxGA/GP (1.5V Spec.) L33 LCD IN1 CS1 RS1 RT1 BD Buzzer RS0 CS0 RI0 IN0 CS0 RS0 CRT0 RT0 RT1RS1CS1 RI1 RT0 TST2 TST1 VDDI VDD C2 C1 VDD3 VDD2 VDD1 VSS VPP C12 CA CB CC CS CI 5V - 5V Interface - Temperature measurement by two thermistors - Battery check circuit is used. - CGEX of crystal oscillator : External 1.5V FEDL64P168-01 Semiconductor ML64P168 APPLICATION CIRCUITS (1.5 V Spec. ) ( continued ) P4.3 P4.2 P4.1 P4.0 P3.3 P3.1 1.5V Spec. Application Circuit ( Voltage Regulator for LCD Driver Used ) 47/51 Switch matrix ( 4 x 4 ) CGEX 32.768 kHz ROS RBLD XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3 OSC2 OSC1 L0 ML 64P168-xxxGA/GP (3.0V Spec.) L33 LCD IN1 CS1 RS1 RT1 BD C12 CA CC CS 3V 5V - 5V Interface - Temperature measurement by two thermistors - Battery check circuit is used. - CGEX of crystal oscillator : External CI Semiconductor OSC monitor SCLK To the serial communication interface SPR ( 5V ( V DDI ) system ) SOUT SIN Buzzer RS0 CS0 RI0 IN0 CS0 RS0 CRT0 RT0 RT1RS1 CS1 RI1 RT0 TST2 TST1 VDDI VDD C2 C1 VDD3 VDD2 VDD1 VSS VPP FEDL64P168-01 ML64P168 APPLICATION CIRCUITS (3.0 V Spec. ) P4.3 P4.2 P4.1 P4.0 P3.3 P3.1 3.0V Spec. Application Circuit ( Voltage Regulator for LCD Driver not Used ) 48/51 Switch matrix ( 4 x 4 ) CGEX 32.768 kHz ROS RBLD XT XT RESET P1.0 P1.1 P1.2 P1.3 P0.0 P0.1 P0.2 P0.3 OSC2 OSC1 L0 ML 64P168-xxxGA/GP (3.0V Spec.) L33 LCD IN1 CS1 RS1 RT1 BD C12 OSC monitor SCLK To the serial communication interface SPR ( 5V ( V DDI ) system ) SOUT SIN Buzzer RS0 CS0 RI0 IN0 CS0 RS0 CRT0 RT0 RT1RS1 CS1 RI1 RT0 TST2 TST1 VDDI VDD C2 C1 VDD3 VDD2 VDD1 VSS VPP CA CB CC CS 3V 5V - 5V Interface - Temperature measurement by two thermistors - Battery check circuit is used. - CGEX of crystal oscillator : External CI FEDL64P168-01 Semiconductor ML64P168 APPLICATION CIRCUITS (3.0 V Spec. ) ( continued ) P4.3 P4.2 P4.1 P4.0 P3.3 P3.1 3.0V Spec. Application Circuit ( Voltage Regulator for LCD Driver Used ) 49/51 FEDL64P168-01 Semiconductor ML64P168 PACKAGE DIMENSIONS ML64P168-XXXGP 25.0±0.2 20.0±0.2 0.17±0.05 41 64 40 0.12 1.0TYP. 25 24 1 0.8TYP. 0.05~0.35 INDEX MARK 2.5TYP. 0.8 +0.08 0.32 -0.07 0.25 80 SEATING PLANE 2.5MAX. 2.1±0.2 14.0±0.2 19.0±0.2 65 0~10° 1.3TYP. 1.38±0.15 0.16 M Figure C-1 80-Pin QFP:GP Package Dimension Diagram Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 50/51 FEDL64P168-01 Semiconductor ML64P168 PACKAGE DIMENSIONS ML64P168-XXXGA 60 41 40 0.17±0.05 16.8±0.2 14.0±0.1 0.83TYP. 61 SEATING PLANE 20 1 0.83TYP. 0~0.25 21 0.65 +0.08 0.32 -0.07 0.25 2.4MAX. 2.1±0.2 1.4±0.2 80 INDEX MARK 0.10 0~10° 0.6TYP. 0.67±0.15 0.13 M Figure C-2 80-Pin QFP:GA Package Dimension Diagram Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 51/51