E2E0027-38-95
¡ Semiconductor
MSM63238
¡ Semiconductor
This version: MSM63238
Sep. 1998
Previous version: Mar. 1996
4-Bit Microcontroller with Built-in POCSAG Decoder and Melody Circuit, Operating at
0.9 V (Min.)
GENERAL DESCRIPTION
The MSM63238 is a CMOS 4-bit microcontroller with a built-in POCSAG (Post Office Code
Standardization Advisory Group) decoder.
The MSM63238 employs Oki's original nX-4/250 CPU core and is suitable for pager applications.
The MSM63P238 is a one-time-programmable ROM-version product having one-time PROM
(OTP) as internal program memory.
The specifications of the MSM63P238 are equal to those of the MSM63238 except for electrical
characteristics, packaging (only 80-pin flat package is available for the MSM63P238), and some
functions.
FEATURES
• Rich instruction set
439 instructions
Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, branch, conditional branch, call/return, control.
• Rich selection of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank
register, HL register and XY register.
Data memory bank internal direct addressing mode.
• Processing speed
Two clocks per machine cycle, with most instructions executed in one machine cycle.
Minimum instruction execution time : 61 ms (@ 32.768 kHz system clock)
1 ms (@ 2 MHz system clock)
• Clock generation circuit
Low-speed clock
High-speed clock
: 32.768 kHz/38.4 kHz/76.8 kHz crystal oscillator
: 2 MHz (Max.) RC or ceramic oscillator select
• Program memory space
16K words
Basic instruction length is 16 bits/1 word
• Data memory space
1K nibbles
• External data memory space
64 Kbytes (expandable by using an I/O port)
1/32
¡ Semiconductor
• Stack level
Call stack level
Register stack level
MSM63238
: 16 levels
: 16 levels
• POCSAG decoder
Data rate
: 512 bps/1200 bps/2400 bps
User frame
: 3 types
User address
: 6 types
Battery saving mode (for controlling intermittent operations of RF receiver)
• I/O ports
Input ports: Selectable as input with pull-up resistance/input with pull-down resistance/
high-impedance input
Output ports: Selectable as P-channel open drain output/N-channel open drain output/
CMOS output/high-impedance output
Input-output ports: Selectable as input with pull-up resistance/input with pull-down
resistance/high-impedance input
Selectable as P-channel open drain output/N-channel open drain
output/CMOS output/high-impedance output
Can be interfaced with external peripherals that use a different power supply than this device
uses.
Number of ports:
Input port
: 1 port ¥ 4 bits
Output port
: 6 ports ¥ 4 bits
Input-output port
: 5 ports ¥ 4 bits
1 port ¥ 2 bits
• Melody output function
Melody sound frequency
Tone length
Tempo
Note data
Buzzer drive signal output
:
:
:
:
:
529 to 2979 Hz
63 types
15 types
Resides in the program memory
4 kHz
• Reset function
Reset through RESET pin
Power-on reset
Reset by low-speed oscillation halt
• Battery check
Low-voltage supply check
Criterion voltage
: Can be selected as 1.05 ±0.10 V, 1.30 ±0.15 V,
2.20 ±0.20 V or 2.80 ±0.30 V
• Power supply backup
Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
2/32
¡ Semiconductor
MSM63238
• Timers and counter
8-bit timer ¥ 4
Selectable as auto-reload mode/capture mode/clock frequency measurement mode
Watchdog timer ¥ 1
15-bit time base counter ¥ 1
1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read
• Serial port
Mode
UART communication speed
Clock frequency in synchronous mode
Data length
• Interrupt sources
External interrupt
Internal interrupt
• Operating voltage
When backup used
When backup not used
: UART mode, synchronous mode
: 1200 bps, 2400 bps, 4800 bps, 9600 bps
: 32.768 kHz (internal clock mode), external
clock frequency
: 5 to 8 bits
: 3
: 15 (watchdog timer interrupt is a nonmaskable interrupt)
: 0.9 to 2.7 V
(Low-speed clock operating)
1.2 to 2.7 V
(Operating frequency: 300 to 500 kHz)
1.5 to 2.7 V
(Operating frequency: 200 kHz to 1 MHz)
: 1.8 to 5.5 V
(Operating frequency: 300 to 500 kHz)
2.2 to 5.5 V
(Operating frequency: 300 kHz to 1 MHz)
2.7 to 5.5 V
(Operating frequency: 200 kHz to 2 MHz)
• Package options:
80-pin plastic QFP (QFP80-P-1420-0.80-BK) : (Product name: MSM63238-xxxGS-BK)
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) : (Product name: MSM63238-xxxTS-K)
Chip
: MSM63238-xxx
xxx indicates a code number.
3/32
¡ Semiconductor
MSM63238
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
and
indicate that the power is
supplied from VDDI to the circuits corresponding to the signal names inside
, and from
VDDR to the circuits corresponding to signal names inside
. (VDDI and VDDR: power supply
for interface)
nX-4/250
TIMING
CONTROL
SP
CBR
H
L
RA
EBR
X
Y
A
C
ALU
RSP
G
MIE
STACK
INSTRUCTION
CAL.S: 16-level
DECODER
PC
Z
ROM
16KW
BUS
D0-7*
EXTMEM
CON-
A0-15*
TROL
RD*
WR*
IR
REG.S: 16-level
INT
4
RESET
RST
RAM
1024N
TM0CAP/TM1CAP*
TM0OVF/TM1OVF*
T02CK*
T13CK*
TIMER
8bit ¥ 4
INT
TST1
TST2
TST3
2
TST
INT
RXC*
TXC*
RXD*
TXD*
SIO
INT
INT
1
TBC
OSC
BLD
INT
OSC1
1
TBCCLK*
HSCLK*
P8.0, P8.1
P9.0-P9.3
I/O
PORT
WDT
PB.0-PB.3
PC.0-PC.3
3
PD.0-PD.3
INT
1
INPUT
PORT
BACKUP
P1.0-P1.3
P7.0-P7.3
INT
P6.0-P6.3
3
OUTPUT
PORT
Internal
PORT
POCSAG
Dec
P5.0-P5.3
P4.0-P4.3
P0.0-P0.3
P8.2, P8.3
PE.0-PE.3
PF.0-PF.3
SIGIN
BS1
BS2
PA.0-PA.3
INT
XTSEL0
XTSEL1
VDDH
VDD
VDDL
VDD2
CB1
CB2
MD
MELODY
DATA BUS
XTM0
XTM1
XT0
XT1
OSC0
4
P3.0-P3.3
P2.0-P2.3
VDDI
VDDR
4/32
¡ Semiconductor
MSM63238
65 P9.0
66 P9.1
67 P9.2
68 P9.3
69 PA.0
70 PA.1
71 PA.2
72 PA.3
73 P4.0
74 P4.1
75 P4.2
76 P4.3
78 P5.1
77 P5.0
2
64 P8.1
63 (NC)
3
62 P8.0
4
61 P3.3
5
60 P3.2
6
59 P3.1
7
58 P3.0
8
57 P2.3
9
56 P2.2
10
55 P2.1
11
54 P2.0
12
13
53 P1.3
52 P1.2
14
51 P1.1
15
16
50 P1.0
49 PB.3
17
48 PB.2
18
47 PB.1
19
46 PB.0
20
45 PC.3
44 PC.2
1
21
23
43 PC.1
42 PC.0
24
41 (NC)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
(NC) 25
22
VDD2
VDDL
VDDH
CB1
CB2
VDD
VSS
MD
RESET
(NC)
VDDI
PD.0
PD.1
PD.2
PD.3
(NC)
P6.0
P6.1
P6.2
P6.3
P7.0
P7.1
P7.2
P7.3
BS1
BS2
SIGIN
VDDR
XT0
XT1
TST1
TST2
TST3
OSC0
OSC1
XTSEL0
XTSEL1
XTM0
XTM1
79 P5.2
80 P5.3
PIN CONFIGURATION (TOP VIEW)
80-Pin Plastic QFP
Note: Pins marked as (NC) are no-connection pins which are left open.
5/32
,
¡ Semiconductor
MSM63238
76 (NC)
77 P8.1
78 (NC)
79 P9.0
80 P9.1
81 P9.2
82 P9.3
83 (NC)
84 PA.0
85 PA.1
86 PA.2
87 PA.3
88 (NC)
90 P4.1
89 P4.0
91 P4.2
92 P4.3
93 P5.0
94 P5.1
95 P5.2
96 (NC)
97 P5.3
98 (NC)
99 P6.0
100 (NC)
PIN CONFIGURATION (TOP VIEW) (continued)
59 P1.0
TST1 18
58 PB.3
TST2 19
57 PB.2
TST3 20
56 PB.1
OSC0 21
55 (NC)
OSC1 22
54 PB.0
XTSEL0 23
53 PC.3
XTSEL1 24
52 PC.2
(NC) 25
51 PC.1
(NC) 50
60 (NC)
(NC) 17
(NC) 49
61 P1.1
XT1 16
PC.0 48
62 P1.2
XT0 15
(NC) 47
63 (NC)
VDDR 14
PD.3 46
64 P1.3
(NC) 13
PD.2 45
65 P2.0
SIGIN 12
PD.1 44
66 (NC)
BS2 11
PD.0 43
67 P2.1
BS1 10
VDDI 42
9
(NC) 41
68 P2.2
(NC)
(NC) 40
8
MD 38
69 P2.3
P7.3
RESET 39
7
VSS 37
70 P3.0
P7.2
VDD 36
6
CB2 35
71 (NC)
(NC)
CB1 34
5
VDDH 33
72 P3.1
P7.1
VDDL 32
4
VDD2 31
73 P3.2
P7.0
(NC) 30
3
(NC) 29
74 P3.3
P6.3
XTM1 28
75 P8.0
2
(NC) 26
1
P6.2
XTM0 27
P6.1
100-Pin Plastic TQFP
Note: Pins marked as (NC) are no-connection pins which are left open.
6/32
¡ Semiconductor
MSM63238
PAD CONFIGURATION
41
42
43
44
45
46
47
48
49
50
51
52
53
54
P3.2
P3.3
P8.0
55
56
57
20 XTSEL1
22 XTM1
21 XTM0
PC.0
PD.3
PD.2
PD.1
PD.0
VDDI
RESET
MD
VSS
VDD
CB2
CB1
VDDH
VDDL
VDD2
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
75
PB.0
PB.1
PB.2
PB.3
P1.0
P1.1
P1.2
P1.3
P2.0
P2.1
P2.2
P2.3
P3.0
P3.1
19 XTSEL0
P6.0
39
40
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
PC.2
PC.3
P8.1
P9.0
P9.1
P9.2
P9.3
PA.0
PA.1
PA.2
PA.3
P4.0
P4.1
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
38 PC.1
Pad Layout
18
17
16
15
14
13
12
11
10
9
OSC1
OSC0
TST3
TST2
TST1
XT1
XT0
VDDR
SIGIN
BS2
8
7
6
5
4
BS1
P7.3
P7.2
P7.1
P7.0
3
2
1
P6.3
P6.2
P6.1
Y
X
Chip Size
Chip Thickness
Coordinate Origin
Pad Hole Size
Pad Size
Minimum Pad Pitch
:
:
:
:
:
:
4.55 mm ¥ 4.55 mm
350 mm (typ.)
Chip center
110 mm ¥ 110 mm
120 mm ¥ 120 mm
150 mm
Note: The chip substrate voltage is VSS.
7/32
¡ Semiconductor
MSM63238
Pad Coordinates
Pad No.
Pad Name
X (µm)
Y (µm)
Pad No.
Pad Name
X (µm)
Y (µm)
1
P6.1
2123.6
–1897.7
39
PC.2
–2123.6
1810.6
2
3
P6.2
2123.6
–1701.4
40
PC.3
–2123.6
1618.5
P6.3
2123.6
–1505.4
41
PB.0
–2123.6
1264.2
4
5
P7.0
2123.6
–1231.1
42
PB.1
–2123.6
1072.2
P7.1
2123.6
–1034.8
43
PB.2
–2123.6
880.1
6
7
P7.2
2123.6
–838.8
44
PB.3
–2123.6
688.0
P7.3
2123.6
–642.5
45
P1.0
–2123.6
496.0
8
9
BS1
2123.6
–446.2
46
P1.1
–2123.6
303.9
BS2
2123.6
–250.2
47
P1.2
–2123.6
111.8
10
11
SIGIN
2123.6
–54.0
48
P1.3
–2123.6
–80.6
VDDR
2123.6
142.0
49
P2.0
–2123.6
–272.7
12
13
XT0
2123.6
338.3
50
P2.1
–2123.6
–464.8
XT1
2123.6
495.0
51
P2.2
–2123.6
–656.8
14
TST1
2123.6
691.3
52
P2.3
–2123.6
–848.9
15
TST2
2123.6
887.2
53
P3.0
–2123.6
–1041.0
16
TST3
2123.6
1083.6
54
P3.1
–2123.6
–1233.1
17
OSC0
2123.6
1279.8
55
P3.2
–2123.6
–1529.1
18
OSC1
2123.6
1436.5
56
P3.3
–2123.6
–1721.2
19
XTSEL0
2123.6
1819.3
57
P8.0
–2123.6
–1913.3
20
XTSEL1
2031.2
2107.3
58
P8.1
–1552.5
–2107.3
21
XTM0
1609.4
2107.3
59
P9.0
–1370.2
–2107.3
22
XTM1
1452.8
2107.3
60
P9.1
–1187.6
–2107.3
23
VDD2
938.6
2107.3
61
P9.2
–1005.2
–2107.3
24
VDDL
782.0
2107.3
62
P9.3
–822.9
–2107.3
25
VDDH
625.3
2107.3
63
PA.0
–640.6
–2107.3
26
CB1
468.6
2107.3
64
PA.1
–458.2
–2107.3
27
CB2
312.0
2107.3
65
PA.2
–275.9
–2107.3
28
VDD
155.4
2107.3
66
PA.3
–93.6
–2107.3
29
VSS
–1.3
2107.3
67
P4.0
88.7
–2107.3
30
MD
–219.4
2107.3
68
P4.1
271.0
–2107.3
31
RESET
–405.6
2107.3
69
P4.2
453.4
–2107.3
32
VDDI
–592.2
2107.3
70
P4.3
635.7
–2107.3
33
PD.0
–778.4
2107.3
71
P5.0
818.0
–2107.3
34
PD.1
–964.9
2107.3
72
P5.1
1000.3
–2107.3
35
PD.2
–1151.2
2107.3
73
P5.2
1182.7
–2107.3
36
PD.3
–1337.7
2107.3
74
P5.3
1365.0
–2107.3
37
PC.0
–1523.9
2107.3
75
P6.0
2042.0
–2107.3
38
PC.1
–2031.2
2107.3
8/32
¡ Semiconductor
MSM63238
PIN DESCRIPTIONS
The basic functions of each pin of the MSM63238 are described in Table 1.
A symbol with a slash (/) denotes a pin that has a secondary function.
Refer to Table 2 for secondary functions.
For type, "—" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an inputoutput pin.
For pin, "GS-BK" denotes an 80-pin flat package (80QFP) and "TS-K" a 100-pin flat package
(100TQFP).
Table 1 Pin Descriptions (Basic Functions)
Function
Power
Supply
Symbol
Pin
GS-BK TS-K
Type
Description
VDD
31
36
—
Positive power supply
VSS
32
37
—
Negative power supply
VDDR
13
14
—
Interface power supply for SIGIN, BS1, BS2
VDDI
36
42
—
VDDL
27
32
—
VDD2
26
31
—
Positive power supply pin for external interface
(power supply for input, output, and I/O ports)
Positive power supply pin for internal logic (internally generated).
A capacitor (0.1 mF) should be connected between this pin and VSS.
Positive power supply pin for low-speed clock (internally generated)
Voltage multiplier pin for power supply backup
VDDH
28
33
—
(internally generated).
A capacitor (1.0 mF) should be connected between this pin
and VSS.
CB1
29
34
—
Pins to connect a capacitor for voltage multiplier.
CB2
30
35
—
A capacitor (1.0 mF) should be connected between CB1 and CB2.
XT0
14
15
I
XT1
15
16
O
should be connected to these pins.
XTM0
23
27
I
Low-speed clock oscillation pins for CPU.
XTM1
24
28
O
OSC0
19
21
I
OSC1
20
22
O
XTSEL0
21
23
Clock oscillation pins for POCSAG decoder.
A 32.768 kHz, 38.4 kHz, or 76.8 kHz crystal and capacitor (CG)
Oscillation
A 32.768 kHz crystal and capacitor (CGM) should be connected
to these pins.
High-speed clock oscillation pins.
A ceramic resonator and capacitors (CL0, CL1) or external
Low-speed CPU clock select pins.
I
Test
XTSEL1
22
24
TST1
16
18
TST2
17
19
TST3
18
20
oscillation resistor (ROS) should be connected to these pins.
These pins are used to select a low-speed CPU clock.
Because these are high impedance inputs, be sure to tie these
pins to VDD or VSS.
Input pins for testing.
I
Pull-down resistors are internally connected to these pins.
The user cannot use these pins.
9/32
¡ Semiconductor
MSM63238
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin
GS-BK TS-K
Type
Description
Reset input pin.
Setting this pin to "H" level puts this device into a reset state.
Reset
RESET
34
39
I
Then, setting this pin to "L" level starts executing an instruction
from address 0000H.
A pull-down resistor is internally connected to this pin.
Melody
POCSAG
Decoder
MD
33
38
BS1
10
10
BS2
11
11
SIGIN
12
12
P1.0/INT5
50
59
P1.1/INT5
51
61
O
O
I
Melody output pin (normal phase)
Battery saving outputs.
Signals to control intermittent operations of RF receiver.
Receive data input pin.
Input pin for receive data from RF receiver.
4-bit input port.
Pull-up resistor input, pull-down resistor input, or
I
Port
P1.2/INT5
52
62
P1.3/INT5
53
64
P2.0
54
65
P2.1
55
67
P2.2
56
68
P2.3
57
69
P3.0
58
70
P3.1
59
72
P3.2
60
73
P3.3
61
74
P4.0/A0
73
89
P4.1/A1
74
90
P4.2/A2
75
91
P4.3/A3
76
92
P5.0/A4
77
93
P5.1/A5
78
94
P5.2/A6
79
95
P5.3/A7
80
97
P6.0/A8
2
99
P6.1/A9
3
1
P6.2/A10
4
2
P6.3/A11
5
3
P7.0/A12
6
4
P7.1/A13
7
5
P7.2/A14
8
7
P7.3/A15
9
8
high-impedance input is selectable for each bit.
4-bit output ports.
O
P-channel open drain output, N-channel open drain output,
CMOS output, or high-impedance output is selectable for each
bit.
O
O
O
O
O
10/32
¡ Semiconductor
MSM63238
Table 1 Pin Descriptions (Basic Functions) (continued)
Function
Symbol
Pin
GS-BK TS-K
P8.0/RD
62
75
P8.1/WR
64
77
P9.0/D0
65
79
P9.1/D1
66
80
P9.2/D2
67
81
P9.3/D3
68
82
PA.0/D4
69
84
PA.1/D5
70
85
PA.2/D6
71
86
PA.3/D7
72
87
46
54
47
56
48
57
49
58
42
48
43
51
44
52
45
53
PD.0
37
43
PD.1
38
44
PD.2
39
45
PD.3
40
46
Type
I/O
Description
2-bit input-output port and 4-bit input-output ports.
In input mode, pull-up resistor input, pull-down resistor input,
or high-impedance input is selectable for each bit.
I/O
In output mode, P-channel open drain output, N-channel open
drain output, CMOS output, or high-impedance output is
selectable for each bit.
I/O
PB.0/INT0/
TM0CAP/
TM0OVF
PB.1/INT0/
TM1CAP/
Port
TM1OVF
PB.2/INT0/
T02CK
PB.3/INT0/
T13CK
PC.0/INT1/
RXD
PC.1/INT1/
TXC
PC.2/INT1/
RXC
PC.3/INT1/
TXD
I/O
I/O
I/O
11/32
¡ Semiconductor
MSM63238
Table 2 shows the secondary functions of each pin of the MSM63238.
Table 2 Pin Descriptions (Secondary Functions)
Function
Symbol
Pin
GS-BK TS-K
Type
Description
PB.0/INT0
46
54
PB.1/INT0
47
56
PB.2/INT0
48
57
PB.3/INT0
49
58
disables an interrupt for each bit.
PC.0/INT1
42
48
External 1 interrupt input pins.
External
PC.1/INT1
43
51
Interrupt
PC.2/INT1
44
52
PC.3/INT1
45
53
disables an interrupt for each bit.
P1.0/INT5
50
59
External 5 interrupt input pins.
P1.1/INT5
51
61
P1.2/INT5
52
62
Capture
External 0 interrupt input pins.
I
I
I
The change of input signal level causes an interrupt to occur.
The Port B Interrupt Enable register (PBIE) enables or
The change of input signal level causes an interrupt to occur.
The Port C Interrupt Enable register (PCIE) enables or
The change of input signal level causes an interrupt to occur.
The Port 1 Interrupt Enable register (P1IE) enables or
disables an interrupt for each bit.
P1.3/INT5
53
64
PB.0/TM0CAP
46
54
I
Timer 0 capture trigger input pin.
PB.1/TM1CAP
47
56
I
Timer 1 capture trigger input pin.
12/32
¡ Semiconductor
MSM63238
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
Timer
Symbol
Type
Description
PB.0/TM0OVF
46
54
O
Timer 0 overflow flag output pin.
PB.1/TM1OVF
47
56
O
Timer 1 overflow flag output pin.
PB.2/T02CK
48
57
I
External clock input pin for timer 0 and timer 2.
PB.3/T13CK
49
58
I
External clock input pin for timer 1 and timer 3.
39
45
O
Low-speed oscillation clock output pin
PD.3/HSCLK
40
46
O
High-speed oscillation clock output pin
PC.0/RXD
42
48
I
Serial port receive data input pin
Oscillation PD.2/TBCCLK
Output
Pin
GS-BK TS-K
Sync serial port clock input-output pin.
Transmit clock output when this device is used as a master
PC.1/TXC
43
51
I/O
processor.
Transmit clock input when this device is used as a slave
Serial
processor.
Port
Sync serial port clock input-output pin.
Receive clock output when this device is used as a master
PC.2/RXC
44
52
I/O
processor.
Receive clock input when this device is used as a slave
processor.
PC.3/TXD
45
53
O
Serial port transmit data output pin.
13/32
¡ Semiconductor
MSM63238
Table 2 Pin Descriptions (Secondary Functions) (continued)
Function
Symbol
Pin
GS-BK TS-K
P4.0/A0
73
89
P4.1/A1
74
90
P4.2/A2
75
91
P4.3/A3
76
92
P5.0/A4
77
93
P5.1/A5
78
94
P5.2/A6
79
95
P5.3/A7
80
97
P6.0/A8
2
99
P6.1/A9
3
1
P6.2/A10
4
2
Type
Description
Address output bus for external memory
O
P6.3/A11
5
3
External
P7.0/A12
6
4
Memory
P7.1/A13
7
5
P7.2/A14
8
7
P7.3/A15
9
8
P9.0/D0
65
79
P9.1/D1
66
80
P9.2/D2
67
81
P9.3/D3
68
82
PA.0/D4
69
84
PA.1/D5
70
85
PA.2/D6
71
86
PA.3/D7
72
87
P8.0/RD
62
75
O
Read signal output pin for external memory (negative logic)
P8.1/WR
64
77
O
Write signal output pin for external memory (negative logic)
Data bus for external memory
I/O
14/32
¡ Semiconductor
MSM63238
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V)
Parameter
Power Supply Voltage 1
Symbol
VDD
Condition
Rating
Backup used, Ta = 25°C
–0.3 to +3.0
Backup not used, Ta = 25°C
–0.3 to +6.0
Unit
V
Power Supply Voltage 2
VDDI
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 3
VDDR
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 4
VDDH
Ta = 25°C
–0.3 to +6.0
V
Power Supply Voltage 5
VDDL
Ta = 25°C
–0.3 to +6.0
V
Input Voltage 1
VIN1
VDD Input, Ta = 25°C
–0.3 to VDD + 0.3
V
Input Voltage 2
VIN2
VDDI Input, Ta = 25°C
–0.3 to VDDI + 0.3
V
VIN3
VDDR Input, Ta = 25°C
–0.3 to VDDR + 0.3
V
Output Voltage 1
VOUT1
VDD output, Ta = 25°C
–0.3 to VDD + 0.3
V
Output Voltage 2
VOUT2
VDDI output, Ta = 25°C
–0.3 to VDDI + 0.3
V
Output Voltage 3
VOUT3
VDDR output, Ta = 25°C
–0.3 to VDDR + 0.3
V
Output Voltage 4
VOUT4
VDDH output, Ta = 25°C
–0.3 to VDDH + 0.3
V
Storage Temperature
TSTG
—
–55 to +150
°C
Input Voltage 3
15/32
¡ Semiconductor
MSM63238
RECOMMENDED OPERATING CONDITIONS
• When backup is used
(VSS = 0 V)
Symbol
Condition
Range
Unit
Operating Temperature
Parameter
Top
—
–20 to +70
°C
VDD
—
0.9 to 2.7
V
Operating Voltage
VDDI
—
0.9 to 5.5
V
VDDR
Crystal Oscillation Frequency
—
0.9 to 5.5
V
fXT
—
30 to 80
kHz
fXTM
—
30 to 35
kHz
VDD = 1.2 to 2.7 V
300k to 500k
VDD = 1.5 to 2.7 V
200k to 1M
VDD = 1.2 to 2.7 V
100 to 300
VDD = 1.5 to 2.7 V
50 to 300
Symbol
Condition
Range
Unit
Ceramic Oscillation Frequency
fCM
External RC Oscillator Resistance
ROS
Hz
kW
• When backup is not used
(VSS = 0 V)
Parameter
Operating Temperature
Operating Voltage
Crystal Oscillation Frequency
Ceramic Oscillation Frequency
External RC Oscillator Resistance
Top
—
–20 to +70
°C
VDD
—
1.8 to 5.5
V
VDDI
—
1.8 to 5.5
V
VDDR
—
1.8 to 5.5
V
fXT
—
30 to 80
kHz
kHz
fXTM
fCM
ROS
—
30 to 35
VDD = 1.8 to 5.5 V
300k to 500k
VDD = 2.2 to 5.5 V
300k to 1M
VDD = 2.7 to 5.5 V
200k to 2M
VDD = 1.8 to 5.5 V
100 to 300
VDD = 2.2 to 5.5 V
50 to 300
VDD = 2.7 to 5.5 V
30 to 300
Hz
kW
16/32
¡ Semiconductor
MSM63238
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
(VDD = VDDI = VDDR = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
High speed clock stop
VDD = 1.5 V
2.8
—
3.0
V
2.0
—
2.7
V
1.0
1.5
2.0
V
1.2
—
5.5
V
1.0
1.5
2.0
V
1.2
—
—
V
Backup used (Ta = 25°C)
0.9
—
—
V
Backup used
1.0
—
—
V
Backup not used
1.7
—
—
V
Ch, C12 = 1 mF
VDDH Voltage (Backup used)
VDDH
High speed clock oscillation
(Ceramic oscillation, 1 MHz)
VDD = 1.5 V
Ch, C12 = 1 mF
High speed clock stop
VDDL Voltage
VDDL
High speed clock oscillation
(VDD = 1.2 to 5.5 V)
VDD2 Voltage
Crystal Oscillation Start
Voltage
VDD2
VSTA
Crystal Oscillation Hold Voltage VHOLD
Crystal Oscillation Stop Detect
Time
External Crystal Oscillator
Capacitance
Internal Crystal Oscillator
Capacitance
Internal RC Oscillator
Capacitance
—
Oscillation start time: within
5 seconds
TSTOP
—
0.1
—
5.0
ms
CG, CGM
—
5
—
25
pF
CD, CDM
—
20
25
30
pF
COS
—
8
12
16
pF
VDD = 1.5 V
0.0
—
0.4
V
VDD = 3.0 V
0.0
—
0.7
V
VDD = 1.5 V
1.2
—
1.5
V
VDD = 3.0 V
2.0
—
3.0
V
POR Voltage
VPOR1
Non-POR Voltage
VPOR2
1
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system
reset occurs.
2. "POR" denotes Power On Reset.
3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises
up to VDD.
4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and
again rises up to VDD.
17/32
¡ Semiconductor
MSM63238
DC Characteristics (continued)
• When backup is used
Parameter
Symbol
(VDD = VDDI = 1.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
CPU in HALT mode.
Supply Current 1
IDD1
(High-speed clock oscillation stop)
Decoder in HALT mode.
—
6.0
35
mA
—
35
80
mA
—
85
200
mA
(Decoder oscillation stop)
CPU in HALT mode.
Supply Current 2
IDD2
(High-speed clock oscillation stop)
Decoder in carrier on state.
(76.8 kHz operation)
CPU in HALT mode.
Supply Current 3
IDD3
(High-speed clock oscillation stop)
Decoder in data receiving state.
(76.8 kHz operation)
1
CPU in operation at 32 kHz.
Supply Current 4
IDD4
(High-speed clock oscillation stop)
Decoder in HALT mode.
—
22
40
mA
—
600
800
mA
—
700
900
mA
(Decoder oscillation stop)
CPU in operation at high speed.
Supply Current 5
IDD5
(RC oscillation, ROS = 51 kW)
Decoder in HALT mode.
(Decoder oscillation stop)
CPU in operation at high speed.
Supply Current 6
IDD6
(Ceramic oscillation, 1 MHz)
Decoder in HALT mode.
(Decoder oscillaiton stop)
18/32
¡ Semiconductor
MSM63238
DC Characteristics (continued)
• When backup is not used
Parameter
Symbol
(VDD = VDDI = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaCondition
Min. Typ. Max. Unit suring
Circuit
CPU in HALT mode.
Supply Current 1
IDD1
(High-speed clock oscillation stop)
Decoder in HALT mode.
—
3.0
20
mA
—
17
40
mA
—
42
100
mA
(Decoder oscillation stop)
CPU in HALT mode.
Supply Current 2
IDD2
(High-speed clock oscillation stop)
Decoder in carrier on state.
(76.8 kHz operation)
CPU in HALT mode.
Supply Current 3
IDD3
(High-speed clock oscillation stop)
Decoder in data receiving state.
(76.8 kHz operation)
1
CPU in operation at 32 kHz.
Supply Current 4
IDD4
(High-speed clock oscillation stop)
Decoder in HALT mode.
—
10
25
mA
—
450
600
mA
—
800
1000
mA
(Decoder oscillation stop)
CPU in operation at high speed.
Supply Current 5
IDD5
(RC oscillation, ROS = 51 kW)
Decoder in HALT mode.
(Decoder oscillation stop)
CPU in operation at high speed.
Supply Current 6
IDD6
(Ceramic oscillation, 2 MHz)
Decoder in HALT mode.
(Decoder oscillation stop)
19/32
¡ Semiconductor
MSM63238
DC Characteristics (continued)
Parameter
Output Current 1
(P2.0 to P2.3)
(P3.0 to P3.3)
(P4.0 to P4.3)
..
.
(PC.0 to PC.3)
(PD.0 to PD.3)
(VDD = VDDI = VDDH = VDDR = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
IOH1
IOL1
VDDI = 1.5 V
–2.5
–1.4
VOH1 = VDDI – 0.5 V VDDI = 3.0 V
–6.0
–3.5
–1.0
mA
VDDI = 5.0 V
–8.5
–5.0
–1.5
mA
VDDI = 1.5 V
0.4
1.4
2.5
mA
VDDI = 3.0 V
1.0
3.0
6.0
mA
VOL1 = 0.5 V
Output Current 2
(MD)
IOH2
IOL2
VOH2 = VDD – 0.7 V
VOL2 = 0.7 V
Output Current 3
(BS1, BS2)
IOL3
Output Current 4
(OSC1)
IOH4R
IOL4R
IOH4C
IOL4C
Output Leakage
(P2.0 to P2.3)
(P3.0 to P3.3)
(P4.0 to P4.3)
..
.
(PD.0 to PD.3)
mA
VDDI = 5.0 V
1.5
3.7
8.5
mA
VDD = 1.5 V
–4.0
–2.0
–0.5
mA
VDD = 3.0 V
–11.0
–6.0
–2.0
mA
VDD = VDDH = 5.0 V
–14.0
–9.0
–4.0
mA
VDD = 1.5 V
0.5
2.0
4.0
mA
VDD = 3.0 V
2.0
5.5
11.0
mA
VDD = VDDH = 5.0 V
4.0
7.0
14.0
mA
–7.0
VDDR = 1.5 V
IOH3
–0.4
–4.5
–1.0
mA
VOH3 = VDDR – 0.5 V VDDR = 3.0 V
–16.0 –10.0
–2.0
mA
VDDR = 5.0 V
–24.0 –14.0
–3.0
mA
7.0
mA
VOL3 = 0.5 V
VDDR = 1.5 V
1.0
4.0
VDDR = 3.0 V
2.0
8.0
16.0
mA
VDDR = 5.0 V
3.0
9.5
24.0
mA
VOH4R = VDDH – 0.5 V VDD = VDDH = 3.0 V
–2.5
–1.3
–0.25
mA
(RC oscillation)
VDD = VDDH = 5.0 V
–3.5
–1.7
–0.5
mA
VOL4R = 0.5 V
VDD = VDDH = 3.0 V
0.25
1.5
2.5
mA
(RC oscillation)
VDD = VDDH = 5.0 V
0.5
1.8
3.5
mA
VOH4C = VDDH – 0.5 V VDD = VDDH = 3.0 V
–300
–160
–60
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
–400
–240
–100
mA
VOL4C = 0.5 V
VDD = VDDH = 3.0 V
60
170
300
mA
(ceramic oscillation)
VDD = VDDH = 5.0 V
100
210
400
mA
IOOH
VOH = VDDI
—
—
1.0
mA
IOOL
VOL = VSS
–1.0
—
—
mA
2
20/32
¡ Semiconductor
MSM63238
DC Characteristics (continued)
Parameter
Input Current 1
(P1.0 to P1.3)
(P8.0, P8.1)
(P9.0 to P9.3)
..
.
(PD.0 to PD.3)
(VDD = VDDI = VDDH = VDDR = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaSymbol
Condition
Min. Typ. Max. Unit suring
Circuit
IIH1
IIL1
VIH1 = VDDI
(when pulled down)
VIL1 = VSS
(when pulled up)
VDDI = 1.5 V
2
20
45
mA
VDDI = 3.0 V
30
120
260
mA
VDDI = 5.0 V
70
350
650
mA
VDDI = 1.5 V
–45
–20
–2
mA
VDDI = 3.0 V
–260
–120
–30
mA
VDDI = 5.0 V
–650
–350
–70
mA
IIH1Z
VIH1 = VDDI (in a high impedance state)
0.0
—
1.0
mA
IIL1Z
VIL1 = VSS (in a high impedance state)
–1.0
—
0.0
mA
Input Current 2
IIH2Z
VIH2 = VDDR
0.0
—
1.0
mA
(SIGIN)
IIL2Z
VIL2 = VSS
Input Current 3
(OSC0)
IIL3
–1.0
—
0.0
mA
VIL3 = VSS
VDD = VDDH = 3.0 V
–350
–170
–30
mA
(when pulled up)
VDD = VDDH = 5.0 V
–750
–450
–200
mA
IIH3R
VIH3 = VDDH (RC oscillation)
0.0
—
1.0
mA
IIL3R
VIL3 = VSS (RC oscillation)
–1.0
—
0.0
mA
IIH3C
IIL3C
VDD = VDDH = 3.0 V
0.1
0.5
1.0
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
0.75
1.5
3.0
mA
VDD = VDDH = 3.0 V
–1.0
–0.5
–0.1
mA
(ceramic oscillation) VDD = VDDH = 5.0 V
–3.0
–1.5
–0.75
mA
VIH3 = VDDH
VIL3 = VSS
Input Current 4
(RESET)
IIH4
VIH4 = VDD
IIL4
VIL4 = VSS
IIH5
VIH5 = VDD
VDD = 1.5 V
10
180
350
mA
VDD = 3.0 V
150
1100
2400
mA
VDD = VDDH = 5.0 V
Input Current 5
(TST1, TST2, TST3)
0.5
2.7
5.0
mA
–1.0
—
0.0
mA
VDD = 1.5 V
50
750
1500
mA
VDD = 3.0 V
0.5
3.0
5.5
mA
VDD = VDDH = 5.0 V
0.25
6.5
11.0
mA
IIL5
VIL5 = VSS
–1.0
—
0.0
mA
Input Current 6
IIH6Z
VIH6 = VDD
0.0
—
1.0
mA
(XTSEL0, XTSEL1)
IIL6Z
VIL6 = VSS
–1.0
—
0.0
mA
3
21/32
¡ Semiconductor
MSM63238
DC Characteristics (continued)
(VDD = VDDI = VDDH = VDDR = 3.0 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
MeaParameter
Symbol
Condition
Min. Typ. Max. Unit suring
Circuit
Input Voltage 1
(P1.0 to P1.3)
(P8.0, P8.1)
(P9.0 to P9.3)
..
.
(PD.0 to PD.3)
Input Voltage 2
(SIGIN)
VIH1
VIL1
VIH2
VIL2
Input Voltage 3
(OSC0)
VIH3
VIL3
Input Voltage 4
(RESET, TST1, TST2, TST3,
XTSEL0, XTSEL1)
VIH4
VIL4
Hysteresis Width 1
(P1.0 to P1.3)
(P8.0, P8.1)
..
.
(PD.0 to PD.3)
DVT1
Hysteresis Width 2
(RESET, TST1, TST2, TST3,
XTSEL0, XTSEL1)
Input Pin Capacitance
(P1.0 to P1.3)
(P8.0, P8.1)
(P9.0 to P9.3)
..
.
(PD.0 to PD.3)
DVT2
CIN
VDDI = 1.5 V
1.2
—
1.5
V
VDDI = 3.0 V
2.4
—
3.0
V
VDDI = 5.0 V
4.0
—
5.0
V
VDDI = 1.5 V
0.0
—
0.3
V
VDDI = 3.0 V
0.0
—
0.6
V
VDDI = 5.0 V
0.0
—
1.0
V
VDDR = 1.5 V
1.2
—
1.5
V
VDDR = 3.0 V
2.4
—
3.0
V
VDDR = 5.0 V
4.0
—
5.0
V
VDDR = 1.5 V
0.0
—
0.3
V
VDDR = 3.0 V
0.0
—
0.6
V
VDDR = 5.0 V
0.0
—
1.0
V
VDD = VDDH = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = VDDH = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDD = 1.5 V
1.35
—
1.5
V
VDD = 3.0 V
2.4
—
3.0
V
VDD = VDDH = 5.0 V
4.0
—
5.0
V
VDD = 1.5 V
0.0
—
0.15
V
VDD = 3.0 V
0.0
—
0.6
V
VDD = VDDH = 5.0 V
0.0
—
1.0
V
VDDI = 1.5 V
0.05
0.1
0.3
V
VDDI = 3.0 V
0.2
0.5
1.0
V
VDDI = 5.0 V
0.25
1.0
1.5
V
VDD = 1.5 V
0.05
0.1
0.3
V
VDD = 3.0 V
0.2
0.5
1.0
V
VDD = VDDH = 5.0 V
0.25
1.0
1.5
V
—
—
—
5
pF
4
1
22/32
¡ Semiconductor
MSM63238
Measuring circuit 1
CB1
Cb12
XT0
CB2
XT1
XTM0
q
OSC0
w
OSC1
(*1)
VSS
VDD
VDDI VDDR
VDDH VDDL
A
Ch
Cl, C2
Ch, Cb12
CG, CGM
CL0
CL1
Ceramic Resonator
: 0.1 mF
: 1 mF
: 15 pF
: 30 pF
: 30 pF
: CSB1000J (1 MHz)
CSA2.00MG (2 MHz)
(Murata MFG.-make)
XTM1
VDD2
V
Cl
V
C2
CG
76.8 kHz
CGM Crystal
32.768 kHz
Crystal
V
*1 RC Oscillator
q
ROS
w
Ceramic Oscillator
q
CL0
Ceramic Resonator
w
CL1
Measuring circuit 2
(*3)
VIH
(*2)
VIL
INPUT
VSS
OUTPUT
VDD
VDDI
VDDR
VDDH
A
VDDL VDD2
*2 Input logic circuit to determine the specified measuring conditions.
*3 Measured at the specified output pins.
23/32
¡ Semiconductor
MSM63238
Measuring circuit 3
(*4)
A
INPUT
VSS
OUTPUT
VDD
VDDI
VDDR
VDDH VDDL
VDD2
Measuring circuit 4
VIH
Waveform
Monitoring
(*4)
VIL
INPUT
VSS
OUTPUT
VDD
VDDI
VDDR
VDDH VDDL
VDD2
*4 Measured at the specified input pins.
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¡ Semiconductor
MSM63238
AC Characteristics (Serial Interface, Serial Port)
(VDD = VDDR = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless
otherwise specified)
(1) Synchronous Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
TXC/RXC Input Fall Time
tf
—
—
—
1.0
ms
TXC/RXC Input Rise Time
tr
—
—
—
1.0
ms
TXC/RXC Input "L" Level
Pulse Width
tCWL
—
0.8
—
—
ms
TXC/RXC Input "H" Level
Pulse Width
tCWH
—
0.8
—
—
ms
TXC/RXC Input Cycle Time
tCYC
—
2.0
—
—
ms
tCYC1(O)
CPU in operation state at 32 kHz
—
30.5
—
ms
—
0.5
—
ms
TXC/RXC Output Cycle Time
CPU in operation at 2 MHz
tCYC2(O)
VDD = VDDH = 2.7 V to 5.5 V
TXD Output Delay Time
tDDR
Output load capacitance 10 pF
—
—
0.4
ms
RXD Input Setup Time
tDS
—
0.5
—
—
ms
RXD Input Hold Time
tDH
—
0.8
—
—
ms
Synchronous communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
tCYC
TXC (PC.1)/
RXC (PC.2)
5 V (VDDI)
tr
0 V (VSS)
tf
tCWH
tCWL
tDDR
tDDR
TXD (PC.3)
5 V (VDDI)
0 V (VSS)
tDS
RXD (PC.0)
tDH
tDS
5 V (VDDI)
0 V (VSS)
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¡ Semiconductor
MSM63238
(2) UART Communication
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Transmit Baud Rate
TBRT
TBRT = 1/fBRT
TCR = 1/fOSC
TBRT–TCR
TBRT
TBRT+TCR
s
Receive Baud Rate
RBRT
RBRT = 1/fBRT
RBRT¥0.97
RBRT
RBRT¥1.03
s
fBRT: Baud rates (1200, 2400, 4800, 9600 bps)
UART communication timing
("H" level = 4.0 V, "L" level = 1.0 V)
TBRT
5 V (VDDI)
TXD (PC.3)
0 V (VSS)
RBRT
RXD (PC.0)
5 V (VDDI)
0 V (VSS)
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¡ Semiconductor
MSM63238
AC Characteristics (External Memory Interface)
(VDD = VDDR = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = –20 to +70°C unless
otherwise specified)
(1) Reading from External Memory
(a) When CPU operates at 32.768 kHz
Symbol
Condition
Min.
Typ.
Read Cycle Time
Parameter
Max.
Unit
tRC
—
—
RD Output Delay Time
tOE
—
—
61.0
—
ms
—
5.0
ms
Output Valid Time
tOHA
—
External Memory Output Delay Time
tDO
—
—
—
5.0
ms
—
—
5.0
ms
Symbol
Condition
Min.
Typ.
Max.
Unit
Read Cycle Time
RD Output Delay Time
tRC
—
1.0
—
—
ms
tOE
—
—
—
100
ns
Output Valid Time
tOHA
—
—
—
100
ns
External Memory Output Delay Time
tDO
—
—
—
150
ns
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Parameter
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB obj, xadr16
MOVXB obj, [RA]
S1
S2
S1
S2
S1
S2
System clock
tRC
P7 - P4
(A15 - A0)
Port setup value
P8.0
(RD)
PA, P9
(D7 - D0)
Address output
tOE
Port setup value
Input data
tDO
Port setup value
tOHA
Port setup value
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
27/32
¡ Semiconductor
MSM63238
(2) Writing to External Memory
(a) When CPU operates at 32.768 kHz
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
tWC
—
—
61.0
—
ms
Address Setup Time
tAS
—
—
30.5
—
ms
Write Time
tW
—
—
15.3
—
ms
Write Recovery Time
tWR
—
—
15.3
—
ms
Data Setup Time
tDS
—
—
45.8
—
ms
Data Hold Time
tDH
—
—
15.3
—
ms
(b) When CPU operates at 2 MHz (VDDH = 2.7 to 5.5 V)
Symbol
Condition
Min.
Typ.
Max.
Unit
Write Cycle Time
Parameter
tWC
—
1.0
—
—
ms
Address Setup Time
tAS
—
0.4
—
—
ms
Write Time
tW
—
0.2
—
—
ms
Write Recovery Time
tWR
—
0.2
—
—
ms
Data Setup Time
tDS
—
0.7
—
—
ms
Data Hold Time
tDH
—
0.2
—
—
ms
AC characteristics timing
("H" level = 4.0 V, "L" level = 1.0 V)
MOVXB [RA], obj or MOVXB xadr16, obj
S1
S2
S1
S2
S1
S2
System clock
tWC
P7 - P4
(A15 - A0)
PA, P9
(D7 - D0)
Port setup value
Address output
Port setup value
Output data
tDS
tDH
Port setup value
Port setup value
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
5 V (VDDI)
0 V (VSS)
P8.1
(WR)
tAS
tW
tWR
28/32
¡ Semiconductor
MSM63238
APPLICATION CIRCUITS
• RC oscillation is selected as high-speed oscillation.
• Ports and RF section are powered from
external memory power source.
• CV is an IC power supply bypass capacitor.
• Values of Cl, C2, CG, CGM, Ch, Cb12, and CV are
for reference only.
76.8 kHz
Crystal
CG
5 to 25 pF
32.768 kHz
Crystal
CGM
5 to 25 pF
Ch
1.0 mF
OSC0
XT0
XT1
OSC1
VDDR
XTM0
SIGIN
BS1
BS2
VDD
0.1 mF
Cb12
1.0 mF
Cl
0.1 mF
C2
0.1 mF
CB1
VDD
MSM63238
P2
PC
PD
CB2
Push SW
Open
VDD
RF Section
VSS
XTM1
VDDH
1.5 V
CV
ROS
VDDL
VDD2
XTSEL0
XTSEL1
RESET
TST1
TST2
TST3
VDDI
VDD
P4-7
P9, PA
P8.0
P8.1
P3
VSS
Key Matrix
LED
Vibrator
UART
VSS
A15-0
D7-0 LCD Module
ROM
RD
SRAM
WR
EEPROM
5.0 V
External
Memory
VSS
Note: VDDI is the power supply pin for the input, output, and input-output ports. VDDR is the
interface power supply pin for SIGIN, BS1, and BS2.
Be sure to connect the VDDI and VDDR pins either to the positive power supply pin (VDD)
of this device or to the positive power supply pin of the external memory.
Application Circuit Example with Power Supply Backup
29/32
¡ Semiconductor
MSM63238
APPLICATION CIRCUITS (continued)
• Ceramic oscillation is selected as high-speed oscillation.
• Ports and RF section are powered from
external memory power source.
• CV is an IC power supply bypass capacitor.
• Values of Cl, C2, CG, CV, CL0, and CL1 are for
reference only.
32.768 kHz
Crystal
CG
5 to 25 pF
OSC0
XT0
OSC1
XT1
CL0
30 pF
Ceramic
Resonator
CL1
30 pF
VDDR
SIGIN
BS1
BS2
XTM0
XTM1
VDDH
3.0 V
VDD
CV
VDD
RF Section
VSS
0.1 mF
Open
CB1
VDD
MSM63238
P2
PC
PD
CB2
Cl
0.1 mF
C2
0.1 mF
VDDL
VDDI
VDD2
XTSEL0
XTSEL1
VDD
P4-7
P9, PA
Push SW
Open
Key Matrix
LED
Vibrator
UART
VSS
RESET
TST1
TST2
TST3
VSS
P8.0
P8.1
P3
A15-0
D7-0 LCD Module
ROM
RD
SRAM
WR
EEPROM
External
Memory
VSS
Note: VDDI is the power supply pin for the input, output, and input-output ports. VDDR is the
interface power supply pin for SIGIN, BS1, and BS2.
Be sure to connect the VDDI and VDDR pins either to the positive power supply pin (VDD)
of this device or to the positive power supply pin of the external memory.
Application Circuit Example with No Power Supply Backup
30/32
¡ Semiconductor
MSM63238
PACKAGE DIMENSIONS
(Unit : mm)
QFP80-P-1420-0.80-BK
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Epoxy resin
42 alloy
Solder plating
5 mm or more
Package weight (g)
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
31/32
¡ Semiconductor
MSM63238
PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
32/32