E2A0035-16-X0 ¡ Semiconductor MSM6882-3/6882-5 ¡ Semiconductor ThisMSM6882-3/6882-5 version: Jan. 1998 Previous version: Nov. 1996 2400/1200 bps Single Chip MSK Modem GENERAL DESCRIPTION The MSM6882-3/6882-5 is a single chip MSK (Minimum Shift Keying) modem which is fabricated by Oki’s low power consumption CMOS silicon gate technology. The demodulator receives the data to be transmitted (SD) synchronized with the transmit timing clock (ST) generated by the on-chip clock generator. The signal, which is modulated by MSK method, is output. The demodulator converts the received MSK signal to the received data (RD) by means of a delay detection technique after limiting the band of the received MSK signal. This signal is input to the digital PLL and the re-generated timing clock (RT) is output from the demodulator, synchronized with the RD. FEATURES • Signal power supply:+3.6 V (MSM6882-3) +5 V (MSM6882-5) • On-chip SCF (Switched Capacitor Filter) • The transmit filter can be also used as voice splatter filter. • The receive timing re-generator has two different lock-in time performance options to be chosen from. • Bit rate 2400/1200 bps • CCIR Rec. 623 • The modulation method can be selected from COS-FFSK and SIN-FFSK. • Built-in crystal oscillation circuit. • Package options: 22-pin plastic DIP (DIP22-P-400-2.54) (Product name: MSM6882-3RS) (Product name: MSM6882-5RS) 24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: MSM6882-3GS-K) (Product name: MSM6882-5GS-K) 1/15 ¡ Semiconductor MSM6882-3/6882-5 BLOCK DIAGRAM ST SD Modulator PRE 1 RC LPF FT Transmit LPF 1 RC LPF 0 SIN 0 0 Receive BPF LIM ME AO 1 BR TI PRE LPF Mixer RC LPF AI CF RT Timing Re-generator PDF * Delay Detector SH RD CT VDD MCS X1 X2 Clock Generator Signal Ground GND SG * Post Detection Filter 2/15 ¡ Semiconductor MSM6882-3/6882-5 PIN CONFIGURATION (TOP VIEW) X1 1 22 VDD X1 1 24 VDD X2 2 21 FT X2 2 23 FT MCS 3 22 CT MCS 3 20 CT ME 4 21 CF SD 5 20 RT ST 6 19 (NC) ME 4 19 CF SD 5 18 RT ST 6 17 RD SIN 7 16 CDO PRE 8 15 CDT BR 9 14 AI SG 10 13 AO GND 11 SIN 7 18 RD PRE 8 17 CDO BR 9 16 CDT SG 10 15 AI GND 11 14 AO GND 12 13 TI 12 TI 22-Pin Plastic DIP 24-Pin Plastic SOP NC : No connect pin 3/15 ¡ Semiconductor MSM6882-3/6882-5 PIN DESCRIPTION Name X1 X2 Description Crystal connection pins. A 3.6864 MHz or 7.3728 MHz crystal shall be connected. When an external clock is applied for MSM6882's oscillation source, it has to be input to X2. In this case, X2 has to be AC-coupled by the capacitor of 200 pF. X1 shall be left open. Master clock selection. MCS ME MCS Crystal or External Clock 0 3.6864 MHz 1 7.3728 MHz Modulator enable. When a "high" is input on this pin, MSK modulator output is connected to the input of transmit LPF. When a "low" is input on this pin, TI is connected to the input of transmit LPF. Send data input. The data on this pin is synchronized with the rising edge of ST and input to MSK modulator as an actual transmit data. SD SD ST MSK Modulated Data ST This timing signal is used to latch serial input data on the SD pin. The frequency of ST coincides with the transmission bit rate. Modulation method selection. Data put on this pin selects either SINE FAST FSK or COSINE FAST FSK. Data (2400 bps) 0 1 0 0 1 1 SIN Sine Fast FSK Cosine Fast FSK PRE Preamble or data transmission selection. When a "low" is input on this pin, the data put on the SD pin is output on the AO pin. When a "high" is input on this pin, the data put on the SD pin is neglected and preamble data is output. Data put on PRE is latched on the rising edge of ST. Preamble means to modulate as 010101...pattern. 4/15 ¡ Semiconductor MSM6882-3/6882-5 Name Description Baud rate selection. Master Clock (MHz) 7.3728 BR 3.6864 3.6864 SG GND TI Carrier Freq. (Hz) MCS BR Bit Rate (bps) Mark Space 1 1 2400 1200 2400 1 0 1200 1200 1800 0 0 1200 1200 1800 1 1 1200 600 1200 1 0 600 600 900 Built-in analog signal ground. The DC voltage is approximately half of VDD, so the analog interfaces signals of AI, AO, and TI with peripheral circuits which must be implemented by AC-coupling. To make this voltage source impedance lower and ensure the device performance of this device, more than 0.1 mF bypass capacitors should be connected from SG to GND and from SG to VDD. Ground. (0 V) Voice signal input. The signal input to this pin can be sent out to AO through the transmit LPF, the characteristics of which, gives the splatter filter for voice band signal. When this function is used, digital "0" must be input to ME. TI is biased to SG through internal resistor. Transmit analog signal output. The data put on ME and FT can set the status of AO as follows. FT ME "1" "1" "1" "0" "0" "1" "0" "0" Transmit LPF State of AO MSK Signal Power On Power Down Voice Signal The Output of Receive BPF No-signal (SG level) Power down TI Transmit LPF AO SD SG Modulator Receive BPF + – AO AI The state when FT and ME = "0" is shown above. When the input digital data on FT changes to "1" from "0", AO remains to be connected to SG during about 2 ms and after that, and AO is switched to transmit LPF. This delay time prevents AO from outputting meaningless signal during transient time from power down to on of LPF. 5/15 ¡ Semiconductor MSM6882-3/6882-5 Name AI Description Receive analog signal input. AI is biased internally to SG with about 100 kW same as TI. CDT Device test. This pin should be connected to GND. CDO Device test. This pin should be opened. RD Demodulated serial data output. This data is synchronized with the re-generated timing clock RT. Receive data timing clock output. This signal is re-generated by internal digital PLL. Synchronizing to negative edge of RT, RD is output. RT RT RD CF Receive data timing clock is re-generated by digital PLL of which phase correcting speed can be selected with CF. When a digital "1" is put on CF and phase difference between receive data timing and RT is more than 22.5 degree, phase correcting speed is high. In this case, as the phase difference enters within 22.5 degrees, that speed changes to low immediately. When digital "0" is input to CF, phase correcting speed of PLL remains low regardless of the phase difference. Usually, CF is connected to digital "1". PLL's lock-in characteristics can be selected with CT. When digital "1" is put on CT, PLL requires max. 50 bit alternative data pattern. On the other hand, when digital "0" is input to CT, PLL can be locked in below 18-bit data. CT CF CT MIN TYP MAX 1 0 — — 18 1 1 — — 50 UNIT bit FT Control signal for the internal connection of AO. Refer to column AO. When digital "0" is input to this pin, transmit LPF enters in power down mode, but the output buffer operational amplifier remains active. In this case, AO is at SG level. VDD Power supply. MSM6882-3: 3.6 V MSM6882-5: 5 V This device is sensitive to supply noise as switched capacitor techniques are utilized. A bypass capacitor of more than 2.2 mF between VDD and GND is indispensable to ensure the performance. 6/15 ¡ Semiconductor MSM6882-3/6882-5 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating VDD VI Ta = 25°C With respect to GND –0.3 to VDD + 0.3 Operating Temperature Top — –25 to 70 Storage Temperature TSTG — –55 to 150 Power Supply Voltage Input Voltage *1 Unit –0.3 to 7.0 V °C *1 MCS, ME, SD, SIN, PRE, BR, TI, AI, CDT, CF, CT, FT RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Symbol VDD GND Operating Temperature Crystal Resonant Frequency Top fX' TAL Condition With respect to GND — Min. Typ. Max. *1 3.0 3.6 4.0 *2 4.5 5 5.5 — 0 — — –25 25 70 MCS = "1" 7.3721 7.3728 7.3735 MCS = "0" 3.6860 3.6864 3.6868 MCS = "1", BR = "1" — 2400 — BR = "0" — 1200 — 2.2 — Data Speed TS C1 — — — C2 — — — 0.1 — C3 — — — 0.047 — C4 — RLX ≥ 40 kW — 0.047 — C5 — — — 0.047 — Crystal Crystal C6 — — — 0.1 — Oscillation Frequency — — — 7.3728 — Frequency Deviation — 25 ±5°C –100 — +100 Temperature Characteristics — At –30°C to +70°C –100 — +100 Equivalent Series Resistance — — — — 50 Unit V °C MHz bit/sec mF MHz ppm W Load Capacitance — — — 16 — pF Oscillation Frequency — — — 3.6864 — MHz Frequency Deviation — 25 ±5°C –100 — +100 Temperature Characteristics — At –30°C to +70°C –100 — +100 Equivalent Series Resistance — — — — 100 W Load Capacitance — — — 16 — pF ppm *1 MSM6882-3 *2 MSM6882-5 7/15 ¡ Semiconductor MSM6882-3/6882-5 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter (MSM6882-3: VDD = 3 V to 4 V, Ta = –25˚C to 70˚C) (MSM6882-5: VDD = 5 V ±0.5 V, Ta = –25˚C to 70˚C) Symbol IDD Power Supply Current *1 IDDS Input Leakage Current *2 Input Voltage Min. Typ. Max. — 4 8 FT = "1" — 5.5 11 Power Down Mode — 3.5 7 FT = "0" — 5.0 10 IIL VIN = 0 V –10 — 10 IIH VIN = VDD –10 — 10 VIL *1 0 — *2 VIH Output Voltage Condition Normal Operating Mode *1 *3 *1 1.8 2.2 — Unit mA mA 0.6 0.8 VDD V 0.3 VOL1 IOL = 10 mA/1.6 mA 0 — VOH1 IOH = 10 mA/400 mA 0.8VDD — VDD Min. Typ. Max. Unit 300 — — ns 0.4 *1 Upper is specified for the MSM6882-3, lower for the MSM6882-5 *2 MCS, ME, SD, SIN, PRE, BR, CF, CT, FT *3 ST, RD, RT Digital Interface Characteristics Parameter Symbol Input Data Set-up Time tS Input Data Hold Time tH Output Data Delay Time tD Condition See Fig.1 See Fig.2 300 — — ns –300 — 300 ns 8/15 ¡ Semiconductor MSM6882-3/6882-5 Analog Interface Characteristics Transmit signal output (AO) Parameter Carrier Frequency (MSM6882-3: VDD = 3 V to 4 V, Ta = –25˚C to 70˚C) (MSM6882-5: VDD = 5 V ±0.5 V, Ta = –25˚C to 70˚C) Symbol 1200 bps fM1 2400 bps fM2 fS1 fS2 Condition FT = "1" BR = "0" ME = "1" BR = "1" Carrier Level *1 VOX RL ≥ 40 kW Output Amplitude *1 VOPP CL £ 40 pF Min. Typ. Max. SD = "1" 1199 1200 1201 SD = "0" 1799 1800 1801 SD = "1" 1199 1200 1201 SD = "0" 2399 2400 2401 Unit Hz FT = "1" –7 –3 –1 dBm ME = "1" –3 0 2 *2 FT = "1" 1.4 2.0 — ME = "0" 2.2 3.0 — Vp-p Output Resistance ROX — — 50 — W Output Load Resistance RLX — 40 — — kW Output Load Capacitance CLX — — — 40 pF Output DC Voltage VOSX — 0.48VDD 0.50VDD 0.52VDD V Condition Min. Typ. Max. Unit –2 0 +2 dB –4 dBm 0 *2 Voice signal input (TI) Parameter Symbol Voltage Gain GT Input Signal Level *1 Input Resistance VAO/VTI FT = "1" ME = "0" VTI — RTI fTI £ 4 kHz — — 40 100 300 kW Min. Typ. Max. Unit 0.52VDD V Built-in signal ground (SG) Parameter Symbol Condition VSG Without DC Load Symbol Condition Min. Typ. Max. Unit RAI fAI £ 4 kHz 40 100 300 kW BR = "0" –30 — 0 dBm BR = "1" –24 — 0 *2 DC Voltage 0.48VDD 0.50VDD Receive signal input (AI) Parameter Input Resistance Receive Signal Level VIR1 VIR2 1200 bps BER Bit Error Rate 2400 bps — S/N at AI SIN = "1" S/N 10–3 — 7 dB — 2¥ 11 dB — 2 ¥ 10–5 — 10 dB — 2¥ 10–3 — 14 dB — 2 ¥ 10–5 — *1 Upper is specified for the MSM6882-3, lower for the MSM6882-5 *2 0 dBm = 0.775 Vrms 9/15 ¡ Semiconductor MSM6882-3/6882-5 Re-generated receive data timing clock output (RT) Parameter Data Bit Number for PLL' Lock-in Symbol NPLL1 NPLL2 Condition CF = "1" CT= "0" CT= "1" *3 Min. Typ. Max. — — 18 — — 50 Unit bit *3 Data bit number to lock-in within 22.5 degree 10/15 ¡ Semiconductor MSM6882-3/6882-5 TIMING DIAGRAM ST 50% 50% SD, PRE tS tH Figure 1 Input Data Timing RT 50% 50% RD tD Figure 2 Output Data Timing 11/15 ¡ Semiconductor MSM6882-3/6882-5 BUILT-IN FILTER FREQUENCY CHARACTERISTICS FREQ (kHz) 9 10 GAIN (dB) 1 2 3 4 5 6 2 2.5 7 8 0 –10 –20 –30 –40 –50 –60 Transmit Low-Pass Filter –70 GAIN (dB) 0.5 1 1.5 3 3.5 FREQ (kHz) 4 0 –10 –20 –30 –40 –50 –60 Receive Band-Pass Filter –70 Note: When BR = "1", frequency converter circuit (MIXER) is prepared before the receive BPF. Therefore, 1200 Hz input signal is converted to 3600 Hz at BPF output for example. 12/15 ¡ Semiconductor MSM6882-3/6882-5 APPLICATION CIRCUIT VDD Crystal 7.3728 MHz C6 C2 VDD 1 X1 V DD 22 2 X2 FT 21 3 MCS CT 20 4 ME CF 19 5 SD RT 18 6 ST RD 17 7 SIN CDO 16 8 PRE CDT 15 9 BR AI 14 10 SG AO 13 11 GND TI 12 C1 C3 C4 C5 13/15 ¡ Semiconductor MSM6882-3/6882-5 PACKAGE DIMENSIONS (Unit : mm) DIP22-P-400-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.90 TYP. 14/15 ¡ Semiconductor MSM6882-3/6882-5 (Unit : mm) SOP24-P-430-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.58 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/15