TI TLC2943IDBR

TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
D
D
D
D
Dual TLC2933 by Multichip Module
(MCM) Technology
Voltage-Controlled Oscillators (VCO)
Section
– Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
– Recommended Lock Frequency
Range
– 37 MHz to 60 MHz
(VDD = 3.3 V ± 0.15 V, TA = –20°C
to 75°C)
– 43 MHz to 100 MHz
(VDD = 5 V ± 0.25 V, TA = –20°C
to 75°C)
Includes a High Speed Edge-Triggered
Phase Frequency Detector (PFD) With
Internal Charge Pump
Independent VCO, PFD Power-Down
Mode
DB PACKAGE
(TOP VIEW)
LOGIC_1 VDD
TEST_1
VCO_1 OUT
FIN-A_1
FIN-B_1
PFD_1 OUT
LOGIC_1 GND
GND
NC
NC
NC
GND
LOGIC_2 VDD
TEST_2
VCO_2 OUT
FIN-A_2
FIN-B_2
PFD_2 OUT
LOGIC_2 GND
description
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
VCO_1 VDD
RBIAS _1
VCOIN_1
VCO_1 GND
VCO_1 INHIBIT
PFD_1 INHIBIT
NC
GND
NC
NC
NC
GND
VCO_2 VDD
RBIAS _2
VCOIN_2
VCO_2 GND
VCO_2 INHIBIT
PFD_2 INHIBIT
NC
The TLC2943 is a multichip module product that
uses two TLC2933 chips. The TLC2933 chip is
composed of a voltage-controlled oscillator (VCO) and an edge-triggered-type phase frequency detector
(PFD). The oscillation frequency range of the VCO is set by an external bias resistor (R BIAS ). The high-speed
PFD with internal charge pump detects the phase difference between the reference frequency input and signal
frequency input from the external counter. Both the VCO and the PFD have inhibit functions that can be used
as a power-down mode. The high-speed and stable VCO characteristics of the TLC2933 make the TLC2943
suitable for use in dual high-performance phase-locked loop (PLL) systems.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE (DB)
– 20°C to 75°C
TLC2943IDB
TLC2943IDBR (Tape and Reel)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
functional block diagram
VCO_1 OUT
VCOIN_1
FIN-A_1
VCO_2 OUT
VCO_1 INHIBIT
VCO_2 INHIBIT
VCO_1
VCO_2
PFD_1
PFD_2
FIN-B_1
FIN-A_2
FIN-B_2
PFD_1 INHIBIT
PFD_2 INHIBIT
PFD_1 OUT
2
VCOIN_2
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PFD_2 OUT
• DALLAS, TEXAS 75265
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
Terminal Functions
TERMINAL
NAME
GND
NO.
I/O
DESCRIPTION
8, 31
Common GND for chip 1
12, 27
Common GND for chip 2
FIN–A_1,
FIN–B_1
4
5
I
Reference frequency signal input and comparison frequency signal input for PFD_1. fREF–IN_1 inputs
to FIN-A_1, and comparison frequency input from external counter logic to FIN–B_1, for a lag-lead filter
use as LPF.
FIN–A_2,
FIN–B_2
16
17
I
Reference frequency signal input and comparison frequency signal input for PFD_2. fREF–IN_2 inputs
to FIN-A_2, and comparison frequency input from external counter logic to FIN-B_2, for a lag-lead filter use
as LPF.
LOGIC_1 GND
7
Ground for the internal logic of chip 1
LOGIC_2 GND
19
Ground for the internal logic of chip 2
LOGIC_1 VDD
1
Power supply for the internal logic of chip 1. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.
LOGIC_2 VDD
13
Power supply for the internal logic of chip 2. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.
NC
9, 10,
11, 20,
28, 29,
30, 32
No internal connection
PFD_1 INHIBIT
33
I
PFD inhibit control for chip 1. When PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state,
see Table 2.
PFD_2 INHIBIT
21
I
PFD inhibit control for chip 2. When PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state,
see Table 2.
PFD_1 OUT
6
O
PFD output of chip 1. When the PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state.
PFD_2 OUT
18
O
PFD output of chip 2. When the PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state.
RBIAS_1
37
I
Bias supply for VCO_1. An external resistor (RBIAS) between VCO_1 VDD and BIAS_1 supplies bias for
adjusting the oscillation frequency range of VCO_1.
RBIAS_2
25
I
Bias supply for VCO_2. An external resistor (RBIAS) between VCO_2 VDD and BIAS_2 supplies bias for
adjusting the oscillation frequency range of VCO_2.
TEST_1
2
Test terminal. TEST connects to LOGIC_1 GND for normal operation.
TEST_2
14
Test terminal. TEST connects to LOGIC_2 GND for normal operation.
VCO_1 GND
35
GND for VCO_1
VCO_2 GND
23
VCO_1 INHIBIT
34
I
VCO inhibit control for chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low (see Table 1).
VCO_2 INHIBIT
22
I
VCO inhibit control for chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low (see Table 1).
VCO_1 OUT
3
O
VCO output of chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low.
VCO_2 OUT
15
O
VCO output of chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low.
VCO_1 VDD
38
Power supply for VCO_1. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.
VCO_2 VDD
26
Power supply for VCO_2. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.
VCOIN_1
36
I
VCO_1 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
VCOIN_2
24
I
VCO_2 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
GND for VCO_2
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
detailed description
MCM (multichip module) technology for TLC2943
The TLC2943 is a multichip module (MCM) product that uses two TLC2933 chips. Inside the package, two chips
are completely isolated by a special formed lead-frame. Therefore,when using the TLC2943 in two
asynchronous PLL circuits, there is no performance degradation by electrical interference between chips inside
the package. So, the same performance as TLC2933 can be easily expected by using TLC2943.
The NC terminals in the middle on both sides of the package are to achieve complete isolation inside the
package. To get the best performance from this MCM technology, it is better to make a careful board layout of
the external power supply, ground, and signal lines.
voltage controlled oscillator (VCO)
VCO_1 and VCO_2 have the same typical characteristics. Each VCO oscillation frequency is determined by
an external resistor (RBIAS) connected between the VCO VDD and the BIAS terminals. The oscillation frequency
and range depend on this resistor value. The bias resistor value for the minimum temperature coefficient is
nominally 2.2 kΩ with VDD = 3.3 V and nominally 2.4 kΩ with VDD = 5 V. For the lock frequency range, refer to
the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control
voltage.
VCO Oscillation Frequency (fosc)
VCO Oscillation Frequency Range
BIAS Resistor (RBIAS)
VCO Control Voltage (VCOIN)
Figure 1. VCO_1 and VCO_2 Oscillation Frequency
VCO inhibit function
Each VCO has an externally controlled inhibit function that inhibits the VCO output. The VCO oscillation is
stopped during a high level on VCOINHIBIT, so the high level can also be used as the power-down mode. The
VCO output maintains a low level during the power-down mode (see Table 1 and Table 2).
Table 1. VCO_1 Inhibit Function
VCO_1 INHIBIT
VCO_1 OSCILLATOR
VCO_1 OUT
VCO_1 IDD
Low
Active
Active
Normal
High
Stop
Low
Power down
Table 2. VCO_2 Inhibit Function
4
VCO_2 INHIBIT
VCO_2 OSCILLATOR
VCO_2 OUT
Low
Active
Active
Normal
High
Stop
Low
Power down
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VCO_2 IDD
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
detailed description (continued)
phase frequency detector (PFD)
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN-A and FIN-B as shown in Figure 2. Nominally the
reference is supplied to FIN-A, and the frequency from the external counter output is fed to FIN-B. For clock
recovery PLL systems, other types of phase detectors should be used.
FIN-A_1, 2
FIN-B_1, 2
VOH
PFD_1, 2 OUT
HI-Z
VOL
Figure 2. PFD Function Timing Chart
PFD output control
A high level on PFD INHIBIT places the PFD OUT in the high impedance state and the PFD stops phase
detection as shown in Table 3 and Table 4. A high level on PFD inhibit also can be used as the power-down mode
for the PFD.
Table 3. PFD_1 Inhibit Function
PFD_1 INHIBIT
PFD_1
PFD_1 OUT
PFD_1 IDD
Low
Active
Active
Normal
High
Stop
Hi-Z
Power down
Table 4. PFD_2 Inhibit Function
PFD_2 INHIBIT
PFD_2
PFD_2 OUT
PFD_2 IDD
Low
Active
Active
Normal
High
Stop
Hi-Z
Power down
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
internal function block diagram
BIAS
Resistor
Output
Buffer
BIAS
Circuit
VCO Control
VCOIN
Figure 3. VCO Block Schematic (VCO_1, VCO_2)
Charge Pump
FIN-A
PFD OUT
Detector
FIN-B
Figure 4. PFD Block Schematic (PFD_1, PFD_2)
6
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VCO OUT
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage (each supply), VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range (each input), VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 to VDD + 0.5 V
Input current (each input), II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output current (each output), IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous total power dissipation at (or below) TA = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . 1160 mW
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20°C to 75°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 9.3 mW/°C.
recommended operating conditions
MIN
Supply voltage (each supply, see Notes 3 and 4 ), VDD
2.85
3
3.15
3.15
3.3
3.45
VDD = 5 V
4.75
5
5.25
0
Output current (each output), IO
0
Control voltage, VCOIN
1
VDD = 3 V
VDD = 3.3 V
VDD = 5 V
VDD = 3 V
Oscillation frequency range set resistor (each RBIAS), RBIAS VCO
MAX
VDD = 3 V
VDD = 3.3 V
Input voltage range (input except for VCOIN_1, 2), VI
Clock frequency, f
NOM
VDD = 3.3 V
VDD = 5 V
Top operating temperature range
VDD
±2
37
VDD
55
37
60
43
100
1.8
2.7
1.8
3.0
2.2
3.0
– 20
75
UNIT
V
V
mA
V
MHz
kΩ
_C
NOTES: 3. It is recommended that the logic supply terminal (LOGIC VDD) and the VCO supply terminal (VCO VDD) be at the same voltage and
separated from each other.
4. Insert bypass capacitors locating the nearest point to each power supply terminal.
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VDD = 3 V
(unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
IOH = – 2 mA
IOL = 2 mA
MIN
NOM
MAX
VOH
VOL
High-level output voltage
V(TH+)
II
Positive input threshold voltage
Z(VCOIN)
IDD(INH)
VCOIN input impedance
VI = VDD or GND
VCOIN = 1/2VDD
VCO supply current (inhibit) (for one chip)
See Note 5
0.01
1
µA
IDD(VCO)
VCO supply current (for one chip)
See Note 6
5.1
15
mA
Low-level output voltage
2.4
UNIT
0.9
Input current
V
1.5
0.3
V
2.1
V
±1
10
µA
MΩ
NOTES: 5. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
6. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD , RBIAS = 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
2.7
UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = – 2 mA
IOL = 2 mA
IOZ
VIH
High-impedance state output current
PFD INHIBIT = high,
VIL
Low-level input voltage at FIN–A, FIN–B
V(TH+)
Positive input threshold voltage at PFD
INHIBIT
CI
Input capacitance at FIN–A, FIN–B
5
pF
ZI
IDD(PFD)
Input impedance at FIN–A, FIN–B
10
MΩ
VO = VDD or GND
High-level input voltage at FIN–A, FIN–B
PFD supply current
V
0.2
V
±1
µA
2.1
0.9
See Note 7
V
1.5
0.7
0.9
V
2.1
V
4
mA
NOTE 7: The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (V I(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT open,
and VCO OUT is inhibited.
8
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VDD = 3.3 V
(unless otherwise noted) (continued)
VCO section
PARAMETER
TEST CONDITIONS
IOH = – 2 mA
IOL = 2 mA
MIN
NOM
MAX
VOH
VOL
High-level output voltage
V(TH+)
II
Positive input threshold voltage
Z(VCOIN)
IDD(INH)
VCOIN input impedance
VI = VDD or GND
VCOIN = 1/2VDD
VCO supply current (inhibit) (for one chip)
See Note 5
0.01
1
µA
IDD(VCO)
VCO supply current (for one chip)
See Note 6
6.2
16
mA
Low-level output voltage
2.7
UNIT
1
Input current
V
1.65
0.4
V
2.3
V
±1
10
µA
MΩ
NOTES: 5. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
6. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD , RBIAS = 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
3
UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = – 2 mA
IOL = 2 mA
IOZ
VIH
High-impedance state output current
PFD INHIBIT = high,
VIL
Low-level input voltage at FIN–A, FIN–B
V(TH+)
Positive input threshold voltage at PFD
INHIBIT
CI
Input capacitance at FIN–A, FIN–B
5
pF
ZI
IDD(PFD)
Input impedance at FIN–A, FIN–B
10
MΩ
VO = VDD or GND
High-level input voltage at FIN–A, FIN–B
PFD supply current
V
0.2
V
±1
µA
2.3
1
See Note 8
V
1.65
0.8
1
V
2.3
V
5
mA
NOTE 8: The current into LOGIC VDD when FIN–A and FIN–B = 30 MHz (V I(PP) = 3.3 V, rectangular wave), PFD INHIBIT = GND, PFD OUT
open, and VCO OUT is inhibited.
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V
(unless otherwise noted) (continued)
VCO section
PARAMETER
TEST CONDITIONS
IOH = – 2 mA
IOL = 2 mA
MIN
NOM
MAX
VOH
VOL
High-level output voltage
V(TH+)
II
Positive input threshold voltage
Z(VCOIN)
IDD(INH)
VCOIN input impedance
VI = VDD or GND
VCOIN = 1/2VDD
VCO supply current (inhibit) (for one chip)
See Note 5
0.01
1
µA
IDD(VCO)
VCO supply current (for one chip)
See Note 6
14
35
mA
Low-level output voltage
4.5
UNIT
1.5
Input current
V
2.5
0.5
V
3.5
V
±1
10
µA
MΩ
NOTES: 5. The current into VCO VDD and LOGIC VDD when VCO INHIBIT = VDD and PFD INHIBIT is high.
6. The current into VCO VDD and LOGIC VDD when VCO IN = 1/2 VDD , RBIAS = 2.4 kΩ, VCO INHIBIT = ground, and PFD INHIBIT
is high.
PFD section
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
4.5
UNIT
VOH
VOL
High-level output voltage
Low-level output voltage
IOH = – 2 mA
IOL = 2 mA
IOZ
VIH
High-impedance state output current
PFD INHIBIT = high,
VIL
Low-level input voltage at FIN–A, FIN–B
V(TH+)
Positive input threshold voltage at PFD
INHIBIT
CI
Input capacitance at FIN–A, FIN–B
7
pF
ZI
IDD(PFD)
Input impedance at FIN–A, FIN–B
10
MΩ
VO = VDD or GND
High-level input voltage at FIN–A, FIN–B
PFD supply current
V
0.2
V
±1
µA
3.5
1.5
See Note 9
V
2.5
2.6
1.5
V
3.5
V
8
mA
NOTE 9: The current into LOGIC VDD when FIN–A and FIN–B = 50 MHz (V I(PP) = 5 V, rectangular wave), PFD INHIBIT = GND, PFD OUT open,
and VCO OUT is inhibited.
10
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
operating characteristics at VDD = 3 V, TA = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
f(OSC)
t(STB)
Oscillation frequency
RBIAS = 2.4 kΩ ,
VCOIN = 1/2VDD
Time to stable oscillation
See Note 10
tr
tf
Output rise time
CL = 15 pF,
See Figure 5
Output fall time
CL = 15 pF,
See Figure 5
f(DUTY)
Duty cycle
RBIAS = 2.4 kΩ ,
VCOIN = 1/2VDD
f(TA)
Temperature coefficient of oscillation
frequency
RBIAS = 2.4 kΩ ,
Top = –20°C to 75°C
VCOIN = 1/2VDD
f(VDD)
Supply voltage coefficient of oscillation
frequency supply
RBIAS = 2.4 kΩ ,
VDD = 2.85 V to 3.15 V
VCOIN = 1.5 V,
MIN
NOM
MAX
UNIT
38
48
58
MHz
10
µs
3.3
10
ns
2
8
ns
50%
55%
45%
0.03
%/°C
0.04
%/mV
NOTE 10: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
PFD section
PARAMETER
TEST CONDITIONS
fMAX
tPLZ
Maximum operating frequency
tPHZ
tPZL
PFD output disable time from high level
tPZH
tr
PFD output enable time to high level
tf
Fall time
Rise time
NOM
MAX
20
40
18
40
4.1
18
4.8
18
3.1
9
1.5
9
30
PFD output disable time from low level
PFD output enable time to low level
MIN
See Figure 6 and Figure 7
7, and Table 5
CL = 15 pF,
pF
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UNIT
MHz
ns
ns
ns
11
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
operating characteristics at VDD = 3.3 V, TA = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
VCOIN = 1/2VDD
MIN
NOM
MAX
UNIT
42
52
62
MHz
10
µs
3
8
ns
1.9
7
ns
f(OSC)
t(STB)
Oscillation frequency
RBIAS = 2.4 kΩ ,
Time to stable oscillation
See Note 10
tr
tf
Output rise time
CL = 15 pF,
See Figure 5
Output fall time
CL = 15 pF,
See Figure 5
f(DUTY)
Duty cycle
RBIAS = 2.4 kΩ ,
VCOIN = 1/2VDD
50%
55%
f(TA)
Temperature coefficient of oscillation
frequency
RBIAS = 2.4 kΩ ,
Top = –20°C to 75°C
VCOIN = 1/2VDD
f(VDD)
Supply voltage coefficient of oscillation
frequency supply
RBIAS = 2.4 kΩ ,
VDD = 3.15 V to 3.45 V
VCOIN = 1.65 V,
45%
0.03
%/°C
0.04
%/mV
NOTE 10: The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
PFD section
PARAMETER
TEST CONDITIONS
fMAX
tPLZ
Maximum operating frequency
tPHZ
tPZL
PFD output disable time from high level
tPZH
tr
PFD output enable time to high level
tf
Fall time
12
Rise time
NOM
MAX
20
40
18
40
30
PFD output disable time from low level
PFD output enable time to low level
MIN
See Figure 6 and Figure 7
7, and Table 5
MHz
16
16
CL = 15 pF,
pF
POST OFFICE BOX 655303
See Figure 6
• DALLAS, TEXAS 75265
UNIT
8
8
ns
ns
ns
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
operating characteristics at VDD = 5 V, TA = 25°C (unless otherwise noted)
VCO section
PARAMETER
TEST CONDITIONS
f(OSC)
t(STB)
Oscillation frequency
RBIAS = 2.4 kΩ ,
VCOIN = 1/2VDD
Time to stable oscillation
See Note 10
tr
tf
Output rise time
CL = 15 pF,
See Figure 5
Output fall time
CL = 15 pF,
See Figure 5
f(DUTY)
Duty cycle
RBIAS = 2.4 kΩ ,
VCOIN = 1/2VDD
f(TA)
Temperature coefficient of oscillation
frequency
RBIAS = 2.4 kΩ ,
Top = –20°C to 75°C
VCOIN = 1/2VDD
f(VDD)
Supply voltage coefficient of oscillation
frequency supply
RBIAS = 2.4 kΩ ,
VDD = 4.75 V to 5.25 V
VCOIN = 2.5 V,
MIN
NOM
MAX
UNIT
64
80
96
MHz
10
µs
2.1
5
ns
1.5
4
ns
50%
55%
45%
0.03
%/°C
0.02
%/mV
PFD section
PARAMETER
TEST CONDITIONS
fMAX
tPLZ
Maximum operating frequency
tPHZ
tPZL
PFD output disable time from high level
tPZH
tr
PFD output enable time to high level
tf
Fall time
Rise time
NOM
MAX
20
40
17
40
3.7
10
3.5
10
1.7
5
1.3
5
50
PFD output disable time from low level
PFD output enable time to low level
MIN
See Figure 6 and Figure 7
7, and Table 5
CL = 15 pF,
pF
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See Figure 6
• DALLAS, TEXAS 75265
UNIT
MHz
ns
ns
ns
13
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
90%
90%
10%
VCO OUT
10%
tr
tf
Figure 5. VCO Output Voltage Waveform (Each VCO)
VDD
VDD
50%
FIN-A
GND
GND
VDD
VDD
50%
FIN-B
GND
GND
VDD
VDD
50%
PFD INHIBIT
50%
GND
GND
VDD
PFD OUT
GND
90%
50%
10%
tPHZ
tPZH
90%
50%
10%
50%
tPZL
tr
tf
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VDD
GND
tPLZ
Figure 6. PFD Output Voltage Waveform
14
50%
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
Test Point
S1
RL
DUT
CL
S2
Figure 7. PFD Output Test Conditions
Table 5. PFD Output Test Conditions
PARAMETER
RL
CL
tPZH
tPHZ
tr
tPZL
tPLZ
1 kΩ
S1
S2
OPEN
CLOSE
CLOSE
OPEN
15 pF
tf
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15
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
TYPICAL CHARACTERISTICS
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
120
120
VDD = 3.3 V
RBIAS = 2.2 kΩ
– 20°C
f osc – Oscillation Frequency – MHz
f osc – Oscillation Frequency – MHz
VDD = 3.3 V
RBIAS = 1.8 kΩ
25°C
100
80
75°C
60
40
20
– 20°C
100
25°C
80
75°C
60
40
20
0
0
0.0
0.6
1.2
1.8
2.4
3.0
0.0
3.6
0.6
1.8
2.4
3.0
3.6
VCOIN – VCO Control Voltage – V
VCOIN – VCO Control Voltage – V
Figure 8
Figure 9
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
120
120
VDD = 3.3 V
RBIAS = 2.7 kΩ
VDD = 3.3 V
RBIAS = 3.0 kΩ
f osc – Oscillation Frequency – MHz
f osc – Oscillation Frequency – MHz
1.2
100
80
60
75°C
25°C
40
20
100
80
75°C
60
25°C
40
– 20°C
20
– 20°C
0
0
0.0
0.6
1.2
1.8
2.4
3.0
3.6
0.0
VCOIN – VCO Control Voltage – V
1.2
1.8
Figure 11
POST OFFICE BOX 655303
2.4
3.0
VCOIN – VCO Control Voltage – V
Figure 10
16
0.6
• DALLAS, TEXAS 75265
3.6
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
TYPICAL CHARACTERISTICS
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
160
VDD = 5 V
RBIAS = 2.2 kΩ
140
VDD = 5 V
RBIAS = 2.4 kΩ
25°C
– 20°C
f osc – Oscillation Frequency – MHz
f osc – Oscillation Frequency – MHz
160
120
100
75°C
80
60
40
140
– 20°C
120
100
75°C
80
60
40
20
20
0
0
0.0
1
2
3
4
1
0.0
5
VCOIN – VCO Control Voltage – V
2
3
4
5
VCOIN – VCO Control Voltage – V
Figure 12
Figure 13
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
OSCILLATION FREQUENCY
vs
CONTROL VOLTAGE
160
160
25°C
VDD = 5 V
RBIAS = 2.7 kΩ
140
f osc – Oscillation Frequency – MHz
f osc – Oscillation Frequency – MHz
25°C
– 20°C
120
100
75°C
80
60
40
VDD = 5 V
RBIAS = 3.0 kΩ
140
120
100
80
75°C
60
40
– 20°C
20
20
25°C
0
0
0.0
1
2
3
4
5
0.0
1
2
3
4
5
VCOIN – VCO Control Voltage – V
VCOIN – VCO Control Voltage – V
Figure 14
Figure 15
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17
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
TYPICAL CHARACTERISTICS
LOCK FREQUENCY RANGE
vs
BIAS RESISTANCE
LOCK FREQUENCY RANGE
vs
BIAS RESISTANCE
110
VDD = 3.15 V – 3.45 V
TA = –20°C to 75°C
60
f LOCK – Lock Frequency Range – MHz
f LOCK – Lock Frequency Range – MHz
65
55
50
45
40
35
30
1.8 k
2.2 k
2.4 k
2.7 k
3k
90
80
70
60
50
40
30
2.2 k
2.4 k
2.6 k
Figure 16
Figure 17
POST OFFICE BOX 655303
2.8 k
RBIAS – BIAS Resistance – Ω
RBIAS – BIAS Resistance – Ω
18
VDD = 4.75 V – 5.25 V
TA = –20°C to 75°C
100
• DALLAS, TEXAS 75265
3k
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
gain of VCO and PFD
Figure 18 is a block diagram of the PLL. The
divider N value depends on the input frequency
and the desired VCO output frequency according
to the system application requirements. The Kp
and KV values are obtained from the operating
characteristics of the device as shown in
Figure 18. Kp is defined from the phase detector
VOL and VOH specifications and the equation
shown in Figure 18(b). KV is defined from
Figures 8, 9, 10, and 11 as shown in Figure 18(c).
The parameters for the block diagram with the
units are as follows:
Divider
(KN = 1/N)
PFD
(Kp)
f REF
VCO
(KV)
TLC2933
LPF
(Kf)
VOH
(a)
– 2π – π
0
π
KV : VCO gain (rad/s/V)
Kp : PFD gain (V/rad)
Kf : LPF gain (V/V)
KN : countdown divider gain (1/N)
2π
fMAX
VOH
VOL
fMIN
Range of
Comparison
external counter
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
VIN MIN
Kp =
VOH – VOL
4π
(b)
KV =
VIN MAX
2π(fMAX – fMIN)
VIN MAX – VIN MIN
(c)
Figure 18. Example of a PLL Block Diagram
RBIAS
The external bias resistor sets the VCO center frequency with 1/2 VDD applied to the VCO IN terminal. For the
most accurate results, a metal-film resistor is the better choice, but a carbon-composition resistor can also be
used with excellent results. A 0.22 µF capacitor should be connected from the BIAS terminal to ground as close
to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 17 is as follows:
DwH ] 0.8
Where
ǒ Ǔ ǒ Ǔ ǒ RǓ
Kp
K
V
K ( )
f
(1)
Kf (∞) = the filter transfer function value at ω = ∞
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
References that include detailed design information about LPFs should be consulted for additional information.
Lag-lead filters or active filters are often used. Examples of LPFs are shown in Figure 19. When the active filter
of Figure 19(c) is used, the reference should be applied to FIN-B because of the amplifier inversion. Also, in
practical filter implementations, C2 is used as additional filtering at the VCO input. The value of C2 should be
equal to or less than one tenth the value of C1.
C2
R1
VI
R1
VI
VO
T1 = C1R1
T2 = C1R2
C1
T1 = C1R1
VO
R2
C1
R2
C2
C1
–
VI
R1
(a) LAG FILTER
A
VO
T1 = C1R1
T2 = C1R2
(b) LAG-LEAD FILTER
(c) ACTIVE FILTER
Figure 19. LPF Examples for PLL
passive filter
The transfer function for the low-pass filter shown in Figure 17(b) is;
V
V
O
IN
+ 1 )1s) s(T1 T2
) T2)
Where
T1
+ R1
C1 and T2
(2)
+ R2
C1
Using this filter makes the closed-loop PLL system a type 1 second-order system. The response curves of this
system to a unit step are shown in Figure 20.
active filter
When using the active filter shown in Figure 19(c), the phase detector inputs must be reversed, since the filter
adds an additional inversion. Therefore, the input reference frequency should be applied to the FIN-B terminal
and the output of the VCO divider should be applied to the input reference terminal, FIN-A.
The transfer function for the active filter shown in Figure 19(c) is:
F(s)
+ 1 )s s
R2
C1
R1 C1
(3)
Using this filter makes the closed-loop PLL system a type 2 second-order system. The response curves of this
system to a unit step are shown in Figure 21.
20
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
Using the lag-lead filter in Figure 19(b) and divider N value, the transfer function for phase and frequency are
shown in equations 4 and 5. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity,
while the feedback for frequency is 1/N.
ȱȧ
ȧȧ
Ȳ
Hence, the transfer function of Figure 19(a) for phase is
F2(s) +
F1(s) N
Kp
K
) T2)
(T1
V
ȱȧ
ȧȧ
Ȳ
s2
ƪ
1
)s 1) N
Kp
ƫ
) s T2
K
T2
Kp K
V
V
)
N (T1)T2)
(T1)T2)
and the transfer function for frequency is
F
OUT(s)
F
REF(s)
Kp K
V
+ (T1
) T2)
Ǹ
s2
ƪ
)s
1
1
)N
)s
Kp K
ȳȧ
ȧȧ
ȴ
)
ƫ
T2
T2
V
(T1 T2)
)N
Kp K
)
ȳȧ
ȧȧ
ȴ
(4)
(5)
V
(T1 T2)
The standard 2-pole denominator is D = s2 + 2 ζ ωn s + ωn2 and comparing the coefficients of the denominator
of equation (4) and (5) with the standard 2-pole denominator gives the following results.
wn +
Kp
N
K
(T1
(6)
)
V
T2)
Solving for T1 + T2
T1
) T2 + KNp
ǒ
K
V
wn2
Ǔ
and by using this value for T1 + T2 in equation (6) the damping factor is
z + w2n
T2
) Kp N K
(7)
V
solving for T2
T2
+ 2wz – Kp N K
(8)
V
then by substituting for T2 in equation (6)
K
Kp
2 z
V
N
– w
T1
2
K
n
N wn
p KV
+
)
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• DALLAS, TEXAS 75265
21
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
ƪ
ƫ
APPLICATION INFORMATION
From the circuit constants and the initial design parameters then
R2
R1
+
ȱȧ
Ȳ
+
z
N
wn * Kp K
2
Kp
wn
2 z
N
*
)
w
K
n
p K
N
Kv
2
V
1
C1
(10)
ȳȧ
ȴ
1
C1
V
(11)
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size.
22
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TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
1.9
1.8
z = 0.1
1.7
z = 0.2
1.6
z = 0.3
1.5
z = 0.4
1.4
z = 0.6
z = 0.5
1.3
z = 0.7
Normalized Gain Response
1.2
z = 0.8
1.1
1
0.9
z = 1.0
0.8
z = 1.5
0.7
0.6
z = 2.0
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
ωnts = 4.5
6
7
8
9
10
11
12
13
ωnt
Figure 20. Type 1 Second-Order Step Response
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23
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
1.9
ζ = 0.1
1.8
1.7
ζ = 0.2
1.6
ζ = 0.3
1.5
ζ = 0.4
ζ = 0.5
1.4
ζ = 0.6
1.3
ζ = 0.7
Normalized Gain Response
1.2
1.1
1
0.9
ζ = 0.8
0.8
ζ = 1.0
0.7
ζ = 2.0
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
ωnt
Figure 21. Type 2 Second-Order Step Response
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10
11
12
13
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
APPLICATION INFORMATION
PCB layout considerations
The TLC2943 contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2943 user:
D
D
D
D
D
D
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
VCO VDD to GND and LOGIC VDD to GND should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
The evaluation and operation schematic for the TLC2943 is shown in Figure 22.
AVDD
VDD
1
2
PLL1
LOGIC VDD (digital)
VCO
38
VCO VDD
R1†
37
TEST
BIAS
0.22 µF
REF IN
DGND
3
VCO OUT
4
FIN – A
5
FIN – B
6
PFD OUT
VCOIN
VCO GND
R3
36
35
C2
R2
C1
VCOINHIBIT 34
AGND
7
Divide
By
N
Phase
Comparator
LOGIC GND (Digital)
PFD INHIBIT 33
GND
31
DGND
S1
PLL2
S2
DGND
R5
R6
DVDD
† RBIAS resistor
Figure 22. Evaluation and Operation Schematic
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
SLAS249 – NOVEMBER 1999
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°– 8°
1,03
0,63
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
A MAX
3,30
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
2,70
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 / C 10/95
NOTES: A.
B.
C.
D.
26
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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