Contents
Features ..............................................................1
Applications .........................................................1
Selection Guide ...................................................2
Block Diagram .....................................................3
Pin Assignment....................................................4
Pin Description ....................................................4
Absolute Maximum Ratings .................................4
Electrical Characteristics......................................5
Measuremnet Circuits..........................................7
Description...........................................................12
Operation Timing Charts......................................16
Battery Protection IC Connection Example ..........18
Precautions..........................................................19
Dimensions..........................................................20
Markings..............................................................20
Taping ................................................................21
Characteristcs (typical characteristics).................23
21 August,1997
BATTERY PROTECTION IC (FOR A 3-SERIAL-CELL PACK)
S-8233B SERIES
The 8233B is a series of lithium-ion rechargeable battery protection ICs
incorporating high-accuracy (±25 mV) voltage detection circuits and
delay circuits. It is suitable for a 3-serial-cell lithium-ion battery pack.
Features
(1)
Internal high-accuracy voltage detection circuit
Over charge detection voltage
3.80 ± 0.025 V to 4.40 ± 0.025 V
Over charge release voltage
5 mV - step
3.45 ± 0.100 V to 4.40 ± 0.100 V
5 mV - step
(The over charge release voltage can be selected within the range where a difference from over
charge detection voltage is 0 to 0.35 V with 50 mV - step)
Over discharge detection voltage
2.00 ± 0.08 V to 2.80± 0.08 V
Over discharge release voltage
50 mV - step
2.00 ± 0.10 V to4.00± 0.10 V
50.mV - step
(The over discharge release voltage can be selected within the range where a difference from
over discharge detection voltage is 0 to 1.2V with 50 mV - step)
0.15 V ±10% to 0.50 V ±10%
Over current detection voltage 1
50 mV - step
(2)
High input-voltage device (absolute maximum rating: 26 V)
(3)
Wide operating voltage range:
(4)
The delay time for every detection can be set via an external capacitor.
(5)
Three over current detection levels (protection for short-circuiting)
(6)
Internal charge/discharge prohibition circuit via the control terminal
(7)
The function for charging batteries from 0 V is available.
(8)
Low current consumption
(9)
Operation
Power-down
2 V to 24 V
50µA max. (+25°C)
0.1µA max. (+25°C)
16-pin TSSOP package
Applications
Lithium-ion rechargeable battery packs
Seiko Instruments Inc.
1
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Selection Guide
Table1
Model/Item
Over charge
Over charge Over discharge Over discharge
detection
release
detection
voltage
voltage
voltage
S-8233BAFT 4.225±0.025V
*1
2.30±0.08V
S-8233BBFT 4.325±0.025V
4.10±0.10V
2.30±0.08V
Over current
0V battery
Conditioning
detection
charging
function
voltage1
function
2.70±0.10V
0.20V±10%
Unavailable
Available
normal
2.70±0.10V
0.20V±10%
Unavailable
Unavailable
reverse
release voltage
CTL logic
*1) Without over charge detection / release hysteresis.
*2) The input voltage of CTL for normal condition is changed by the CTL logic. (Please refer description).
Change in the detection voltage is available in products other than the above listed ones. Contact the
SII Semiconductor Products Sales Department.
2
Seiko Instruments Inc.
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Block Diagram
VCC
Reference
voltage 1
Over current
2,3 delay circuit
Over current
detection
circuit
VMP
Over current 1
delay circuit
COVT
Over discharge
delay circuit
CDT
+
−
CD1
+
−
VC1
Battery 1
Over charge
Battery 1
Over discharge
Battery 1
Over charge
Control
+
−
CD2
Logic
Battery 2
Over charge
Over charge
delay circuit
+
CCT
−
Battery 2
Over discharge
Reference
voltage 2
VC2
DOP
Battery 2
Over charge
+
−
CD3
Battery 3
Over charge
COP
+
−
Battery 3
Over discharge
Reference
voltage 3
VSS
Battery 3
Over charge
Floating
detection circuit
CTL
Figure 1
The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time
cannot be changed via an external capacitor.
Seiko Instruments Inc.
3
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
Pin Assignment
21 August,1997
Pin Description
Table 2
Top View
No.
Name
Description
1
DOP
Connects FET gate for discharge control (CMOS output)
3
COP
Connects FET gate for charge control (Nch open-drain output)
4
VMP
Detects voltage between VCC to VMP(Over current detection pin)
DOP
1
16
VCC
NC
2
15
NC
COP
3
14
CD1
VMP
4
13
VC1
6
CDT
Connects capacitor for over discharge detection delay circuit
7
CCT
Connects capacitor for over charge detection delay circuit
8
VSS
Negative power input, and connects negative voltage for battery 3
COVT
5
12
CD2
CDT
6
11
VC2
CCT
7
10
CD3
VSS
8
9
CTL
5
COVT Connects capacitor for over current detection1delay circuit
9
CTL
Charge/discharge control signal input
10
CD3
Battery 3 conditioning signal output
11
VC2
Connects battery 2 negative voltage and battery 3 positive voltage
12
CD2
Battery 2 conditioning signal output
13
VC1
Connects battery 1 negative voltage and battery 2 positive voltage
14
CD1
Battery 1 conditioning signal output
16
VCC
Positive power input and connects battery 1 positive voltage
2,15
NC
T S S O P -16
Figure 2
Non connect
Absolute Maximum Ratings
Table 3
4
Item
Sym.
Input voltage between VCC and VSS
VDS
Input terminal voltage
VIN
VMP Input terminal voltage
Ta = 25°C
Applied Pins
Rating
Unit
VSS-0.3 to VSS+26
V
VC1,VC2,CTL,CCT,CDT,COVT
VSS-0.3 to VCC+0.3
V
VVMP
VMP
VSS-0.3 to VSS+26
V
CD1 output terminal voltage
VCD1
CD1
VC1-0.3 to VCC+0.3
V
CD2 output terminal voltage
VCD2
CD2
VC2-0.3 to VCC+0.3
V
CD3 output terminal voltage
VCD3
CD3
VSS-0.3 to VCC+0.3
V
DOP output terminal voltage
VDOP
DOP
VSS-0.3 to VCC+0.3
V
COP output terminal voltage
VCOP
COP
VSS-0.3 toVVMP+0.3
V
Power dissipation
PD
TSSOP-16PKG
300
mW
Operating temperature range
Topr
-20 to +70
°C
Storage temperature range
Tstg
-40 to +125
°C
Seiko Instruments Inc.
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Electrical Characteristics
Table 4
Item
Detection voltage
Over charge detection
voltage1
Over charge release
voltage1
Over discharge detection
voltage1
Over discharge release
voltage1
Over charge detection
voltage 2
Over charge release
voltage 2
Over discharge detection
voltage 2
Over discharge release
voltage 2
Over charge detection
voltage 3
Over charge release
voltage 3
Over discharge detection
voltage 3
Over discharge release
voltage 3
Over current detection
voltage1
Over current detection
voltage 2
Over current detection
voltage 3
Voltage temperature
factor 1
Voltage temperature
factor 2
Delay time
Over charge detection
delay time1
Over charge detection
delay time 2
Over charge detection
delay time 3
Over discharge detection
delay time1
Over discharge detection
delay time 2
Over discharge detection
delay time 3
Over current detection
delay time1
Over current detection
delay time 2
Over current detection
delay time 3
Operating voltage
Operating voltage
between VCC and VSS
Symbol
condition Test
circuit
Notice
Ta = 25°C
Min.
Typ.
Max.
Unit
VCU1
1
1
3.80 to 4.40 Adjustment VCU1-0.025
VCU1
VCU1+0.025
V
VCD1
1
1
3.45 to 4.40 Adjustment
VCD1-0.10
VCD1
VCD1+0.10
V
VDD1
1
1
2.00 to 2.80 Adjustment
VDD1-0.08
VDD1
VDD1+0.08
V
VDU1
1
1
2.00 to 4.00 Adjustment
VDU1-0.10
VDU1
VDU1+0.10
V
VCU 2
2
1
3.80 to 4.40 Adjustment VCU2-0.025
VCU2
VCU2+0.025
V
VCD 2
2
1
3.45 to 4.40 Adjustment
VCD2-0.10
VCD2
VCD2+0.10
V
VDD 2
2
1
2.00 to 2.80 Adjustment
VDD2-0.08
VDD2
VDD2+0.08
V
VDU 2
2
1
2.00 to 4.00 Adjustment
VDU2-0.10
VDU2
VDU2+0.10
V
VCU 3
3
1
3.80 to 4.40 Adjustment VCU3-0.025
VCU3
VCU3+0.025
V
VCD 3
3
1
3.45 to 4.40 Adjustment
VCD3-0.10
VCD3
VCD3+0.10
V
VDD 3
3
1
2.00 to 2.80 Adjustment
VDD3-0.08
VDD3
VDD3+0.08
V
VDU 3
3
1
2.00 to 4.00 Adjustment
VDU3-0.10
VDU3
VDU3+0.10
V
VIOV1
4
2
VIOV1×0.9
VIOV1
VIOV1×1.1
V
VIOV2
4
2
(*4)0.15 to 0.50V
Adjustment
VCC Reference
0.54
0.6
0.66
V
VIOV3
4
2
VSS Reference
1.0
2.0
3.0
V
TCOE1
(*1)Ta=-20 to 70°C
-1.0
0
1.0
mV/°C
TCOE2
(*2)Ta=-20 to 70°C
-0.5
0
0.5
mV/°C
tCU1
9
6
CCCT=0.47µF
0.5
1.0
1.5
S
tCU2
10
6
CCCT=0.47µF
0.5
1.0
1.5
S
tCU3
11
6
CCCT=0.47µF
0.5
1.0
1.5
S
tDD1
9
6
CCDT=0.1µF
20
40
60
mS
tDD2
10
6
CCDT=0.1µF
20
40
60
mS
tDD3
11
6
CCDT=0.1µF
20
40
60
mS
tIOV1
12
7
CCOVT=0.1µF
10
20
30
mS
tIOV2
12
7
2
4
8
mS
tIOV3
12
7
FET gate capacitor
=2000pF
100
300
550
µS
(*3)
2.0
-
24
V
VDSOP
Seiko Instruments Inc.
5
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
Current consumption
Current consumption
IOPE
5
3
V1=V2=V3=3.5V
(during normal operation)
Current consumption for
ICELL1
5
3
V1=V2=V3=3.5V
cell 1
Current consumption for
ICELL2
5
3
V1=V2=V3=3.5V
cell 2
Current consumption for
ICELL3
5
3
V1=V2=V3=3.5V
cell 3
Current consumption at
IPDN
5
3
V1=V2=V3=1.5V
power down
Internal resistance for 0V battery charging function available type.
Resistance between
Rvcm
6
3
V1=V2=V3=3.5V
VCC and VMP
Resistance between
Rvsm
6
3
V1=V2=V3=3.5V
VSS and VMP
Internal resistance for 0V battery charging function unavailable type.
Resistance between
Rvcm
6
3
V1=V2=V3=3.5V
VCC and VMP
Resistance between
Rvsm
6
3
V1=V2=V3=3.5V
VSS and VMP
Input voltage
CTL”H”Input voltage
VCTL(H)
CTL”L”Input voltage
VCTL(L)
Output voltage
D O P”H”voltage
VDO(H)
7
4
Iout=10uA
D O P”L”voltage
VDO(L)
7
4
Iout=10uA
C O P”L”voltage
VCO(L)
8
5
Iout=10uA
C O P OFF LEAK current
ICOL
14
9
V1=V2=V3=4.5V
CD1”H”voltage
VCD1(H)
13
8
Iout=0.1uA
CD1”L”voltage
VCD1(L)
13
8
Iout=10uA
CD 2”H”voltage
VCD2(H)
13
8
Iout=0.1uA
CD 2”L”voltage
VCD2(L)
13
8
Iout=10uA
CD 3”H”voltage
VCD3(H)
13
8
Iout=0.1uA
CD 3”L”voltage
VCD3(L)
13
8
Iout=10uA
0V battery charging function (*5)
0V charging start voltage V0CHAR
15
10
(*1)
21 August,1997
-
20
50
µA
-300
0
300
nA
-300
0
300
nA
-300
0
300
nA
-
-
0.1
µA
0.20
0.50
0.80
MΩ
0.20
0.50
0.80
MΩ
0.40
0.90
1.40
MΩ
0.40
0.90
1.40
MΩ
VCC×0.8
-
-
VCC×0.2
V
V
VCC-0.5
VCC-0.5
VCC-0.5
VCC-0.5
-
-
VSS+0.1
VSS+0.1
100
VC1+0.1
VC2+0.1
VSS+0.1
V
V
V
nA
V
V
V
V
V
V
-
-
1.4
V
Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage,
over discharge detection voltage, and over discharge release voltage.
(*2)
Voltage temperature factor 2 indicates over current detection voltage.
(*3)
The DOP and COP logic must be established for the operating voltage.
(*4)
If over current detection voltage 1 is 0.50 V, both over current detection voltages 1 and 2 are 0.54 to
0.55 V, but VIOV2 > VIOV1.
(*5)
6
This spec applies for only 0V battery charging function available type.
Seiko Instruments Inc.
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Measurement Circuits
Attention!) At the Measurement circuit from 1 to 15.
If the device’s CTL logic is “normal” then set the CTL voltage at VSS (V4=0V).
If the device’s CTL logic is “reverse” then set the CTL voltage at VCC (V4=V1+V2+V3).
(1) Measurement 1 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V1 from 3.5 V gradually. The V1 voltage
when COP = 'H' is over charge detection voltage 1 (VCU1). Decrease V1 gradually. The V1 voltage
when COP = 'L' is over charge release voltage 1 (VCD1). Further decrease V1. The V1 voltage when
DOP = 'H' is over discharge voltage 1 (VDD1). Increase V1 gradually. The V1 voltage when DOP = 'L'
is over discharge release voltage 1 (VDU1).
(2) Measurement 2 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V2 from 3.5 V gradually. The V2 voltage
when COP = 'H' is over charge detection voltage 2 (VCU2). Decrease V2 gradually. The V2 voltage
when COP = 'L' is over charge release voltage 2 (VCD2). Further decrease V2. The V2 voltage when
DOP = 'H' is over discharge voltage 2 (VDD2). Increase V2 gradually. The V2 voltage when DOP = 'L'
is over discharge release voltage 2 (VDU2).
(3) Measurement 3 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V3 from 3.5 V gradually. The V3 voltage
when COP = 'H' is over charge detection voltage 3 (VCU3). Decrease V3 gradually. The V3 voltage
when COP = 'L' is over charge release voltage 3 (VCD3). Further decrease V3. The V3 voltage when
DOP = 'H' is over discharge voltage 3 (VDD3). Increase V3 gradually. The V3 voltage when DOP = 'L'
is over discharge release voltage 3 (VDU3).
Note: The voltage change rate is 150 V/sec or less under measuring conditions 1 to 3.
(4) Measurement 4 Measurement circuit 2
Set V1, V2, V3 to 3.5 V and V5 to 0 V under normal condition. Increase V5 from 0 V gradually. The V5
voltage when DOP = 'H' and COP = 'H, is over current detection voltage 1 (VIOV1).
Set V1, V2, and V3 to 3.5 V and V5 to 0 V under normal condition. Fix the COVT terminal at VSS,
increase V5 from 0 V gradually. The V5 voltage when DOP = 'H" and COP = 'H' is over current
detection voltage 2 (VI0V2).
Set V1, V2, and V3 to 3.5 V and V5 to 0 V under normal condition. Fix the COVT terminal at VSS,
increase V5 gradually from 0 V at 400 µs to 2 ms. The V5 voltage when DOP = 'H" and COP = 'H' is
over current detection voltage 3 (VI0V3).
(5) Measurement 5 Measurement circuit 3
Set S1 to ON, V1, V2, and V3 to 3.5 V, and V5 to 0 V under normal condition and measure current
consumption. I1 is the normal condition current consumption (IOPE), I2, the cell 2 current consumption
(ICELL2), and I3, the cell 3 current consumption (ICELL3).
Set S1 to ON, V1, V2, and V3 to 1.5 V, and V5 to 4.5 V under over discharge condition. Current
consumption I1 is power-down current consumption (IPDN).
Seiko Instruments Inc.
7
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
(6) Measurement 6 Measurement circuit 3
Set S1 to ON, V1, V2, and V3 to 3.5 V, and V5 to 10.5 V under normal condition. V5/I5 is the internal
resistance between VCC and VMP (Rvcm).
Set S1 to ON, V1, V2, and V3 to 1.5 V, and V5 to 4.1 V under over discharge condition. (4.5-V5)/I5 is the
internal resistance between VSS and VMP (Rvsm).
(7) Measurement 7 Measurement circuit 4
Set S1 to ON, S2 to OFF, V1, V2, and V3 to 3.5 V, and V5 to 0 V under normal condition. Increase V6
from 0 V gradually. The V6 voltage when I6 = 10 µA is DOP'L' voltage (VD0 (L)).
Set S1 to OFF, S2 to ON, V1, V2, V3 to 3.5 V, and V5 to VIOV2+0.1 V under over current condition.
Increase V7 from 0 V gradually. The V7 voltage when I7 = 10 µA is the DOP'H' voltage (VDO (H)).
(8) Measurement 8 Measurement circuit 5
Set V1, V2, V3 to 3.5 V and V5 to 0 V under normal condition. Increase V6 from 0 V gradually. The V6
voltage when I1 = 10 µA is the COP'L' voltage (VC0 (L)).
(9) Measurement 9 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V1 from 3.5 V to 4.5 V immediately (within 10
µs). The time after V1 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 1 (tCU1).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V1 from 3.5 V to 1.9 V immediately (within 10
µs). The time after V1 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 1
(tDD1).
(10) Measurement 10 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V2 from 3.5 V to 4.5 V immediately (within 10
µs). The time after V2 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 2
(tCU2).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V2 from 3.5 V to 1.9 V immediately (within 10
µs). The time after V2 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 2
(tDD2).
(11) Measurement 11 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V3 from 3.5 V to 4.5 V immediately (within 10
µs). The time after V3 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 3
(tCU3).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V3 from 3.5 V to 1.9 V immediately (within 10
µs). The time after V3 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 3
(tDD3).
(12) Measurement 12 Measurement circuit 7
Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V5 from 0 V to 0.55 V
immediately (within 10 µs). The time after V5 becomes 0.55 V until DOP goes 'H' is the over current
detection delay time 1 (tI0V1).
Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V5 from 0 V to 0.75 V
immediately (within 10 µs). The time after V4 becomes 0.75 V until DOP goes 'H' is the over current
detection delay time 2 (tIOV2)
Set S1 to ON to inhibit over discharge detection. Set V1, V2, V3 to 4.0 V and increase V5 from 0 V to
8
Seiko Instruments Inc.
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
6.0 V immediately (within 1 µs) and decrease V1, V2, and V3 to 2.0 V at a time. The time after V5
becomes 6.0 V until DOP goes 'H' is the over current detection delay time 3 (tIOV3).
(13) Measurement 13 Measurement circuit 8
Set S4 to ON, S1, S2, S3, S5, and S6 to OFF, V1, V2, V3 to 3.5 V and V6, V7, and V8 to 0 V under
normal condition. Increase V5 from 0 V gradually. The V5 voltage when I5 = 10 µA is the CD1'L'
voltage (CD1(L))
Set S5 to ON, S1, S2, S3, S4, and S6 to OFF, V1, V2, and V3 to 3.5 V and V5, V7, and V8 to 0 V under
normal condition. Increase V6 from 0 V gradually. The V6 voltage when I6 = 10 µA is the CD2'L'
voltage (VCD2(L)).
Set S6 to ON, S1, S2, S3, S4, and S5 to OFF, V1, V2, and V3 to 3.5 V and V5, V6, and V8 to 0 V under
normal condition. Increase V7 from 0 V gradually. The V7 voltage when I7 = 10 µA is the CD3'L'
voltage (VCD3(L)).
Set S1 to ON, S2, S3, S4, S5, and S6 to OFF, V1 to 4.5 V, V2 and V3 to 3.5 V and V5, V6, and V7 to 0
V under over charge condition. Increase V8 from 0 V gradually. The V8 voltage when I8 = 0.1 µA is the
CD1'H' voltage (VCD1(H)).
Set S2 to ON, S1, S3, S4, S5, and S6 to OFF, V2 to 4.5 V, V1 and V3 to 3.5 V and V5, V6, and V7 to 0
V under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 µA is the
CD2'H' voltage (VCD2(H)).
Set S3 to ON, S1, S2, S4, S5, and S6 to OFF, V3 to 4.5 V, V1 and V2 to 3.5 V and V5, V6, and V7 to 0
V under over charge condition. Increase V8 from 0 V gradually. The V8 voltage when I8 = 0.1 µA is the
CD3'H' voltage (VCD3(H)).
(14) Measurement 14 Measurement circuit 9
Set V1, V2, and V3 to 4.5 V under over charge condition. The current I1 flowing to COP terminal is
COP OFF LEAK current (ICOL).
(15) Measurement 15 Measurement circuit 10
Set V1, V2, and V3 to 0 V, and V5 to 2 V, and decrease V5 gradually. The V5 voltage when COP = 'H'
(VSS + 0.3 V or higher) is the 0V charge start voltage (V0CHAR).
(16) Measurement 16 Measurement circuit 1 ( Measurement will be changed by the CTL logic! )
If the CTL logic is “normal”
Set V1, V2, and V3 to 3.5 V, and V4 to 0 V, and increase V4 gradually. The V4 voltage when COP = 'H'
(VSS + 0.3 V or higher) and DOP = 'H' (VSS + 0.3 V or higher) is the CTL’H’ input voltage {VCTL(H)}.
After that decrease V4 gradually. The V4 voltage when COP = ‘L' (VCC - 0.3 V or lower) and DOP = 'L'
(VCC - 0.3 V or lower) is the CTL’L’ input voltage {VCTL(L)}.
If the CTL logic is “reverse”
Set V1, V2, and V3 to 3.5 V, and V4 to10.5 V, and decrease V4 gradually. The V4 voltage when COP =
'H' (VSS + 0.3 V or higher) and DOP = 'H' (VSS + 0.3 V or higher) is the CTL’L’ input voltage {VCTL(L)}.
After that increase V4 gradually. The V4 voltage when COP = ‘L' (VCC - 0.3 V or lower) and DOP = 'L'
(VCC - 0.3 V or lower) is the CTL’H’ input voltage {VCTL(H)}.
Seiko Instruments Inc.
9
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Notice : If the CTL logic is “normal” (S-8233BA) then CTL=VSS (V4=0V).
If the CTL logic is “reverse” (S-8233BB) then CTL=VCC (V4=V1+V2+V3).
V5
1MΩ
DOP
V1
1MΩ
COP
VCC
VMP
CD1
CTL
DOP
V4
CD1
CTL
V2
CCT
CD2
CDT
VC2
V4
VC1
CCT
CD2
V3
VMP
V1
VC1
V2
COP
VCC
CDT
VC2
V3
CD3
CD3
COVT
COVT
VSS
VSS
Measurement circuit 1
Measurement circuit 2
I5
V6
S1
S1
V5
DOP
I1
I6
V7
S2
COP
VCC
VMP
CD1
CTL
V1
V4
I2
DOP
V1
VC1
V2
V5
I7
VCC
COP
VMP
CD1
CTL
V4
CCT
CD2
VC1
I3
CDT
VC2
V2
CCT
CD2
V3
CDT
VC2
CD3
COVT
V3
VSS
CD3
COVT
VSS
Measurement circuit 3
Measurement circuit 4
V6
I6
1MΩ
V5
DOP
DOP
VCC
V1
CD1
COP
VMP
CTL
V1
V4
COP
VCC
VMP
CD1
CTL
V4
VC1
VC1
V2
CCT
V2
CCT
CD2
CD2
C1 = 0.47µF
C2 = 0.1µF
VC2
VC2
CDT
V3
V3
CDT
COVT
VSS
VSS
Measurement circuit 6
Measurement circuit 5
Seiko Instruments Inc.
C2
CD3
CD3
COVT
10
C3 = 0.1µF
C1
C3
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
V5
1MΩ
DOP
1MΩ
COP
VCC
V1
VMP
CD1
CTL
V1
V4
S4
VC1
CD2
C1 = 0.47µF
S5
S1
C2 = 0.1µF
VC2
V3
I5
V5
V2
C1
CDT
C3 = 0.1µF
C2
I6
V6
S3
COVT
I7
V7
C3
VSS
I1
DOP
CD1
CTL
V4
V1
CCT
VC2
CDT
COVT
VSS
1MΩ
COP
VCC
VMP
CD1
CTL
V4
VC1
CCT
V2
CD2
CDT
CCT
CD2
CDT
VC2
V3
CD3
CD2
DOP
VC1
V3
V4
VC1
COP
VMP
VC2
CTL
V5
V1
V2
VMP
Measurement circuit 8
Measurement circuit 7
VCC
COP
CD3
V3
S6
CD3
DOP
CD1
S2
CCT
V2
VCC
I8 V8
S1
CD3
COVT
COVT
VSS
VSS
Measurement circuit 10
Measurement circuit 9
Seiko Instruments Inc.
11
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Description
Normal condition
This IC monitors the voltages of the three serially-connected batteries and the discharge current to
control charging and discharging. If the voltages of all the three batteries are in the range from the over
discharge detection voltage (VDD) to the over charge detection voltage (VCU), and the current flowing
through the batteries becomes equal or lower than a specified value (the VMP terminal voltage is equal
or lower than over current detection voltage 1), the charging and discharging FETs turn on. In this
condition, charging and discharging can be carried out freely. This condition is called the normal
condition. In this condition, the VMP and VCC terminals are shorted by the Rvcm resistor.
Over current condition
This IC is provided with the three over current detection levels (VIOV1,VIOV2 and VIOV3) and the three
over current detection delay time (TIOV1,TIOV2 and TIOV3) corresponding to each over current
detection level.
If the discharging current becomes equal to or higher than a specified value (the VMP terminal voltage
is equal to or higher than the over current detection voltage) during discharging under normal condition
and it continues for the over current detection delay time (TIOV) or longer, the discharging FET turns off
to stop discharging. This condition is called an over current condition. The VMP and VCC terminals are
shorted by the Rvcm resistor at this time. The charging FET turns off.
When the discharging FET is off and a load is connected, the VMP terminal voltage equals the VSS
potential.
The over current condition returns to the normal condition when the load is released and the impedance
between the EB- and EB+ terminals (see Figure 7 for a connection example) is 100MΩ or higher.
When the load is released, the VMP terminal, which and the VCC terminal are shorted with the Rvcm
resistor, goes back to the VCC potential. The IC detects that the VMP terminal potential returns to over
current detection voltage 1 (VIOV1) or lower (or the over current detection voltage 2 (VIOV2) or lower if
the COVT terminal is fixed at the 'L' level and over current detection 1 is inhibited) and returns to the
normal condition.
Over charge condition
If one of the battery voltages becomes higher than the over charge detection voltage (VCU) during
charging under normal condition and it continues for the over charge detection delay time (TCU) or
longer, the charging FET turns off to stop charging. This condition is called the over charge condition.
The 'H' level signal is output to the conditioning terminal corresponding to the battery which exceeds the
over charge detection voltage until the battery becomes equal to lower than the over charge release
voltage (VCD). The battery can be discharged by connecting an Nch FET externally. The discharging
current can be limited by inserting R11, R12 and R13 resistors (see Figure 7 for a connection example).
The VMP and VCC terminals are shorted by the Rvcm resistor under the over charge condition.
The over charge condition is released in two cases:
1) The battery voltage which exceeded the over charge detection voltage (VCU) falls below the over
charge release voltage (VCD), the charging FET turns on and the normal condition returns.
2) If the battery voltage which exceeded the over charge detection voltage (VCU) is equal or higher
than the over charge release voltage (VCD), but the charger is removed, a load is placed, and
discharging starts, the charging FET turns on and the normal condition returns.
The release mechanism is as follows: the discharge current flows through an internal parasitic
diode of the charging FET immediately after a load is installed and discharging starts, and the VMP
terminal voltage decreases by about 0.6 V from the VCC terminal voltage momentarily. The IC
detects this voltage (over current detection voltage 1 or higher), releases the over charge condition
and returns to the normal condition.
12
Seiko Instruments Inc.
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Over discharge condition
If any one of the battery voltages falls below the over discharge detection voltage (VDD) during
discharging under normal condition and it continues for the over discharge detection delay time (TDD)
or longer, the discharging FET turns off and discharging stops. This condition is called the over
discharge condition. When the discharging FET turns off, the VMP terminal voltage becomes equal to
the VSS voltage and the IC's current consumption falls below the power-down current consumption
(IPDN). This condition is called the power-down condition. The VMP and VSS terminals are shorted by
the Rvsm resistor under the over discharge and power-down conditions.
The power-down condition is canceled when the charger is connected and the voltage between VMP
and VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes
equal to or higher than the over discharge release voltage (VDU) in this condition, the over discharge
condition changes to the normal condition.
Delay circuits
The over charge detection delay time (TCU1 to TCU3), over discharge detection delay time (TDD1 to
TDD3), and over current detection delay time 1 (TI0V1) are changed with external capacitors (C4 to
C6).
The delay times are calculated by the following equations:
Min Typ. Max.
TCU[S] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF]
TDD[S] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF]
TIOV1[S]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF]
Note: The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time
cannot be changed via an external capacitor.
CTL terminal
[If the CTL logic is “normal”]<S-8233BA>
If the CTL terminal is floated under normal condition, it is pulled up to the VCC potential in the IC, and
both the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the Rvcm resistor.
When the CTL terminal becomes equal to VSS potential, charging and discharging are enabled and go
back to their appropriate conditions for the battery voltages.
[If the CTL logic is “reverse”]<S-8233BB>
When the CTL terminal becomes equal to VSS potential, both the charging and discharging FETs turn
off to inhibit charging and discharging. If the CTL terminal is floated under normal condition, charging
and discharging are enabled and go back to their appropriate conditions for the battery voltages.
Seiko Instruments Inc.
13
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Table.5 Output voltage & current consumption by CTL terminal voltage.
Statements
CTL terminal voltage
CTL logic “normal”
COP
Normal &Over voltage state
High & Floated
High
S-8233BA
Power down mode(Without charger)
Low
High
Low
Floated
Comply with
High
Low
Unknown
High
High
High
battery voltage
DOP
High
Comply with
battery voltage
Current consumption
CTL logic “reverse”
COP
S-8233BB
Typ.20µA
Typ.20µA
Typ. 1nA
Typ. 1nA
Unknown
Comply with
High
Low
High
Unknown
High
High
High
High
Typ.20µA
Typ. 1nA
Typ. 1nA
Unknown
battery voltage
DOP
Comply with
battery voltage
Current consumption
Typ.20µA
0V battery charging function
This function is used to recharge the three serially-connected batteries after they self-discharge to 0V.
When the 0V charging start voltage (V0CHAR) or higher is applied to between VMP and VSS by
connecting the charger, the charging FET gate is fixed to VSS potential.
When the voltage between the gate sources of the charging FET becomes equal to or higher than the
turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the
discharging FET turns off and the charging current flows through the internal parasitic diode in the
discharging FET. If all the battery voltages become equal to or higher than the over discharge release
voltage (VDU), the normal condition returns.
Notes: In the products without 0V battery charging function, the resistance between VCC and VMP and
between VSS and VMP are lower than the products with 0V battery charging function. It causes to
that over charge detection voltage increases by the drop voltage of R5 (see Figure 7 for a
connection example) with sink current at VMP.
The COP output is undefined below 2.0V on VCC-VSS voltage in the products without 0V battery
charging function.
Voltage temperature factor
Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage, over
discharge detection voltage, and over discharge release voltage.
Voltage temperature factor 2 indicates over current detection voltage.
The Voltage temperature factors 1 and 2 are expressed by the oblique line parts in Figure 3.
14
Seiko Instruments Inc.
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Ex. Voltage temperature factor of over charge detection voltage
VCU
[V]
+0.1mV/°C
VCU25 is the over charge detection
voltage at 25°C
VCU25
-0.1mV/°C
-20
25
70
Ta[°C]
Figure 3
Seiko Instruments Inc.
15
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Operation Timing Charts
1.
Over charge detection
V2 battery
V1 battery
V3 battery
Vcu
Vcd
Battery
voltage
Vdu
Vdd
Vcc
DOP
terminal
Vss
COP
terminal
Hi-z
Hi-z
Hi-z
Hi-z
Vss
Vcha
Vcc
VMP
terminal
Vss
Charger
connected
Load
connected
Mode
Note:
Delay
Delay
Normal mode, Over charge mode, Over discharge mode, Over current mode
The charger is assumed to charge with a constant current. Vcha indicates the open voltage of the charger.
Figure 4
16
Delay
Delay
Seiko Instruments Inc.
Delay
& Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
2. Over discharge detection
V1 battery
V2 battery
V3 battery
Vcu
Vcd
Battery
voltage
Vdu
Vdd
Vcc
DOP
terminal
Vss
COP
terminal
Hi-z
Vss
Vcha
VMP
Vcc
terminal
Vss
Charger
connected
Load
connected
Delay
Mode
Delay
Delay
Delay
Delay
Note: Normal mode, Over charge mode, Over discharge mode, Over current mode
The charger is assumed to charge with a constant current. Vcha indicates the open voltage of the charger.
Figure 5
3. Over current detection
V1, V2, and V3 batteries
Battery
voltage
Vcu
Vcd
Vdu
Vdd
Vcc
DOP
terminal
Vss
COP
terminal
Hi-z
Hi-z
Hi-z
Hi-z
Vss
Vcc
VMP
Viov1
terminal
Viov2
Viov3
Charger
connected
Load
connected
Delay T IOV1
Mode
Delay
Delay T IOV2
Note: Normal mode, Over charge mode,
Over discharge mode, Over current mode
T IOV3
CTL terminal
VSS VCC
Inhibit charging and
discharging
CTL terminal
VCC VSS
Figure 6
If the CTL logic is “reverse” ,it will be exchanged VCC for VSS.
Seiko Instruments Inc.
17
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Battery Protection IC Connection Example
EB+
FET-A
FET1
Battery 1
R11
C1
R6
FET-B
DOP
VCC
R5
1MΩ
10KΩ
COP
VMP
Nch open
drain
CTL
R7
CD1
1KΩ
R1
VC1
Battery 2
CD2
C2
C4
S-8233B series
VC2
C5
FET3
Battery 3
Over discharge delay
time setting
FET-C
CDT
R2
R13
Over charge delay
time setting
CCT
FET2
R12
C3
CTL logic is “normal” (S-8233BA)
VSS(GND): Normal operation
Floating or VCC: Inhibit charging
and discharging.
CTL logic is “reverse” (S-8233BB)
Floating or VCC: Normal operation
VSS(GND): Inhibit charging and
discharging.
CD3
COVT
VSS
High: Inhibit over
discharge detection.
Over current delay
time setting
C6
R3
EB -
Figure 7
[Description of Figure 7]
R11, R12, and R13 are used to adjust the battery conditioning current. The conditioning current during
over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To disable the
conditioning function, open CD1, CD2, and CD3.
The over charge detection delay time (tCU1 to tCU3), over discharge detection delay time (tDD1 to
tDD3), and over current detection delay time (tI0V1) are changed with external capacitors (C4 to C6).
See the electrical characteristics.
R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a 100kΩ to 1
MΩ resistor.
R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ resistor.
If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters the
over current mode. C6 must be connected to prevent it.
If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of
battery voltage when the over current occurs. In this case, a charger must be connected to return to
the normal condition. To prevent this, connect an at least 0.01µF capacitor to C5.
If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and VSS,
the delay time increases and an error occurs. The leak current must be 100 nA or less.
Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 µA or less.
If over discharge is inhibited by using this FET, the current consumption does not fall below 0.1 µA even
when the battery voltage drops and the IC enters the over discharge detection mode.
R1, R2, and R3 must be 1kΩ or less.
R7 is the protection of the CTL when the CTL terminal voltage higher than VCC voltage. Connect a
300 Ω to 5 k Ω resister. If the CTL terminal voltage never greater than the VCC voltage (ex. R7
connect to VSS), without R7 resistance is allowed .
Notes:
If any electrostatic discharge of 2000 V or higher is not applied to the S-8233B series with a human
body model, R1, R2, R3, C1, C2, and C3 are unnecessary.
The above connection diagram and constants do not guarantee proper operations. Evaluate your
actual application and set constants properly.
18
Seiko Instruments Inc.
21 August,1997
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
Precautions
If a charger is connected in the over discharge condition and one of the battery voltages becomes
equal to or higher than the over charge release voltage (VCU) before the battery voltage which is
below the over discharge detection voltage (VDD) becomes equal to or higher than the over
discharge release voltage (VDU), the over discharge and over charge conditions are entered and
the charging and discharging FETs turn off. Both charging and discharging are disabled. If the
battery voltage which was higher than the over charge detection voltage (VCU) falls to the over
charge release voltage (VCD) due to internal discharging, the charging FET turns on.
If the charger is detached in the over charge and over discharge condition, the over charge
condition is released, but the over discharge condition remains. If the charger is connected again,
the battery condition is monitored after that. The charging FET turns off after the over charge
detection delay time, the over charge and over discharge conditions are entered.
If any one of the battery voltages is equal to or lower than the over discharge release voltage (VDU)
when they are connected for the first time, the normal condition may not be entered. If the VMP
terminal voltage is made equal to or higher than the VCC voltage (if a charger is connected), the
normal condition is entered.
If the CTL terminal floats in power-down mode, it is not pulled up in the IC, charging may not be
inhibited. However, the over discharge condition becomes effective. At that time, current
consumption would be increase because CTL terminal is affected by noise. If the charger is
connected, the CTL terminal is pulled up, and charging and discharging are inhibited immediately.
Seiko Instruments Inc.
19
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Dimensions
5.0
16
0.5
9
4.4
6.4±0.2
0.15±0.05
8
1
1.10
0.65
0.07
0.10
φ0.13 M
0.2±0.1
(Unit : mm )
Figure 8
Markings
16
9
(1) : U fix
(2) : Assembly year (last digit of the year)
(3) : Assembly month (1 to 9, X, Y, Z)
(4) to (10) : Product name
(7)
1
(1)
(2)
(3)
(4)
(5)
(6)
(8)
(9)
(10)
8
Figure 9
20
Seiko Instruments Inc.
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Taping
1. Tape specifications
7.5±0.1
0.3±0.05
2.0±0.1
φ1.5
+0.1
-0
1.75±0.1
After molding
B
8.0±0.1
4.0±0.1
16.0±0.3
5.1 +0.4
A
-0.2
A
φ1.6±0.1
B
(0° ~ 5°)
+0.4
6.5 -0.2
4.2±0.2
Section B-B
0.3±0.1
(0° ~ 5°)
( Unit : mm )
(0° ~ 40°)
Feed direction
Section A-A
Figure 9
Seiko Instruments Inc.
21
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
2. Reel specifications
One reel holds 2000 ICs.
External reel diameter
Part
A
(Unit: mm)
Enlarged part A
Figure 11
22
Seiko Instruments Inc.
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Characteristics (typical characteristics)
Detection voltage temperature characteristics
Over charge detection voltage vs. temperature
VCU=4.25[V]
4.35
Over charge release voltage vs. temperature
VCD=4.10[V]
4.20
VCU[V]
VCD [V]
4.25
4.10
4.15
-40
-20
0
20
40
Ta [°C]
60
80
100
Over discharge detection voltage vs. temperature
VDD=2.35[V]
2.45
4.00
-40
VDU [V]
2.35
2.85
-20
0
20
40
Ta [°C]
60
80
100
Over current 1 detection voltage vs. temperature
2.75
-40
VIOV1=0.3[V]
VIOV1 [V]
VIOV2 [V]
0.30
0.60
0
20
40
Ta [°C]
60
80
60
80
100
-20
0
20
40
Ta [°C]
60
80
100
VIOV2=0.6[V]
0.65
-20
20
40
Ta [°C]
Over current 2 detection voltage vs. temperature
0.35
0.25
-40
0
Over discharge release voltage vs. temperature
VDU=2.85[V]
2.95
VDD[V]
2.25
-40
-20
100
0.55
-40
Seiko Instruments Inc.
-20
0
20
40
Ta [°C]
60
80
100
23
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
2. Current consumption temperature characteristics
Current consumption vs. temperature in normal mode
Current consumption vs. temperature in
power-down mode
VCC=4.5[V]
VCC=10.5[V]
1.0
50
IOPE [uA]
IPDN [nA]
0.5
25
0
-40
-20
0
20
40
Ta [°C]
60
80
100
0.0
-40
-20
0
20
40
Ta [°C]
60
80
100
3. Delay time temperature characteristics
Over charge detection time vs. temperature
C=0.47[uF]
VCC=11.5[V]
1.5
Over discharge detection time vs. temperature
C=0.1[uF]
VCC=8.5[V]
60
TCU [S]
TDD [mS]
1.0
40
0.5
-40
-20
0
20
40
Ta [°C]
60
80
100
Over current 1 detection time vs. temperature
C=0.1[uF]
VCC=10.5[V]
30
TIOV1 [mS]
24
-20
0
20
40
Ta [°C]
60
80
100
Over current 2 detection time vs. temperature
VCC=10.5[V]
8
TIOV2 [mS]
20
10
-40
20
-40
5
-20
0
20
40
Ta [°C]
60
80
100
2
-40
Seiko Instruments Inc.
-20
0
20
40
Ta [°C]
60
80
100
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
21 August,1997
Over current 3 (load short) detection time vs.
temperature
VCC=6.0[V]
0.40
TIOV3 [mS]
0.25
0.10
-40
-20
0
20
40
Ta [°C]
60
80
100
4. Delay time vs. power supply voltage
Over current 3 (load short) detection time vs. power
supply voltage
Ta=25[°C]
1.0
TIOV3 [mS]
0.5
0.0
3
6
9
VCC [V]
12
15
Seiko Instruments Inc.
25
Battery Protection IC(for a 3-serial-cell pack)
S-8233B Series
* Please design all applications of the S-8233 Series with safety in mind.
26
Seiko Instruments Inc.
21 August,1997