SIPEX SP6137

®
SP6137
Wide Input, 900KHz Synchronous PWM Controller
FEATURES
■
■
■
■
■
■
■
■
■
■
■
VCC 1
2.5V to 20V Step Down Achieved Using Dual Input
Small 10-Pin MSOP Package
2A to 15A Ouput Capability
Highly Integrated Design, Minimal Components
UVLO Detects Both VCC and VIN
Short Circuit Protection with Auto-Restart
On-Board 1.5Ω sink (2Ω source) NFET Drivers
Programmable Soft Start
Fast Transient Response
High Efficiency: Greater than 94% Possible
A Synchronous Start-Up into a Pre-Charged Output
10 BST
GL 2
SP6137
8 SWN
GND 3
VFB 4
9 GH
10 Pin MSOP
7 SS
6 UVIN
COMP 5
Now Available in Lead Free Packaging
APPLICATIONS
■ 12V DPA
■ Communications Systems
■ Graphics Cards
DESCRIPTION
The SP6137 is a synchronous step-down switching regulator controller optimized for high efficiency. The part is
designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower VCC
voltage minimizes power dissipation in the part. The SP6137 is designed to drive a pair of external NFETs using a fixed
900kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown and output
short circuit protection. The SP6137 is available in the cost and space saving 10-pin MSOP.
TYPICAL APPLICATION CIRCUIT
VIN
2.5V -20V
C1
22µF
16V
8 7 6 5
C2
22µF
16V
VCC = 5V @ 30mA
FDS6676S
14.5A, 6mΩ
QT
4
RLF
3.0,5%
GND
C1, C2
Ceramic
1210
X5R
1 2 3
CBST
1µF
U1
DBST
MBR0530
1
R3
221k, 1%
CVCC
10µF
6.3V
GND 3
2
3
4
0.8V
5
UVIN
R4
100k, 1%
CVCC
Ceramic
8050
X5R
GL
BST 10
SP6137
R5
Bead
SWN 8
VFB
SS 7
COMP
UVIN 6
CZ2
RZ2
L1 SC5018-2R7M
2.7µH @ 12A
DCR=4.30mΩ
GH 9
GND
8 7 6 5
QB
4
SS
CSS
47nF
RZ3
4.64k, 1%
C3
47µF
6.3V
C4
47µF
6.3V
1 2 3
CZ3
220pF
VOUT≤VIN
1.8V @ 10A
R1
68.1k, 1%
FDS6676S
14.5A, 6.0mΩ
GND2
820pF 40.2k, 1%
CP1
CF1
100pF
Date: 7/28/04
VCC
C3, C4
Ceramic
1210
X5R
56pF
SP6137 Wide Input, 900KHz Synchronous PWM Controll
1
R2
21.5k, 1%
© Copyright 2004 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
Peak Output Current < 10us
GH,GL ............................................................................................. 2A
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
Storage Temperature .................................................. -65°C to 150°C
Power Dissipation .......................................................................... 1W
Lead Temperature (Soldering, 10 sec) ...................................... 300°C
ESD Rating .......................................................................... 2kV HBM
Thermal Resistance ............................................................. 41.9°C/W
VCC .................................................................................................. 7V
BST ............................................................................................... 27V
BST-SWN ......................................................................... -0.3V to 7V
SWN ................................................................................... -1V to 20V
GH ......................................................................... -0.3V to BST+0.3V
GH-SWN ......................................................................................... 7V
All other pins .......................................................... -0.3V to VCC+0.3V
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = 0V, UVIN = 3.0V, CVCC =
10µF, CCOMP = 0.1µF, CGH = CGL = 3.3nF, CSS = 50nF, Typical measured at VCC=5V. The ♦ denotes the specifications
which apply over the full operating temperature range, unless otherwise specified.
PARAMETER
MIN
TYP
MAX
UNITS
♦
CONDITIONS
QUIESCENT CURRENT
VCC Supply Current
1.5
BST Supply Current
0.2
0.4
mA
mA
♦
VFB =0.9V (No switching)
V
♦
V
♦
VFB =0.9V (No switching)
PROTECTION: UVLO
VCC UVLO Start Threshold
4.00
4.25
4.5
VCC UVLO Stop Threshold
3.80
4.05
4.4
VCC UVLO Hysteresis
200
mV
UVIN Start Threshold
2.3
2.5
2.65
V
♦
UVIN Stop Threshold
2.0
2.2
2.35
V
♦
UVIN Hysteresis
300
mV
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference
0.792
0.800
0.808
V
Error Amplifier Reference
Over Line and Temperature
0.788
0.800
0.812
V
2X Gain Config., Measure COMP/2
♦
Error Amplifier Transconductance
6
ms
Error Amplifier Gain
60
dB
No Load
COMP Sink Current
150
µA
VFB = 0.9V, COMP = 0.9V
COMP Source Current
150
µA
VFB Input Bias Current
50
Internal Pole
4
COMP Clamp
2.5
V
COMP Clamp Temp. Coefficient
-2
mV/°C
200
nA
VFB = 0.7V, COMP = 2.2V
♦
VFB = 0.8V
MHz
VFB=0.7V, TA = 25°C
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude
0.92
RAMP Offset
1.1
RAMP Offset Temp. Coefficient
-2
GH Minimum Pulse Width
90
Maximum Controllable Duty Ratio
92
Maximum Duty Ratio
100
Internal Oscillator Frequency
810
Date: 7/28/04
1.28
1.1
V
♦
V
TA = 25°C, RAMP COMP
until GH starts switching
mV/°C
180
97
ns
♦
%
♦
%
900
990
kHz
Maximum Duty Ratio Measured just
before pulse skipping begins
Valid for 20 Cycles
♦
SP6137 Wide Input, 900KHz Synchronous PWM Controll
2
© Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS: Continued
Unless otherwise specified: 0°C < TAMB < 70°C, 4.5V < VCC < 5.5V, BST=VCC,SWN = GND = 0V, UVIN = 3.0V, CVCC = 10µF,
CCOMP = 0.1µF, CGH = CGL = 3.3nF, CSS = 50nF, Typical measured at VCC=5V. The ♦ denotes the specifications which
apply over the full operating temperature range, unless otherwise specified.
PARAMETER
MIN
TYP
MAX
UNITS
♦
CONDITIONS
mA
♦
Fault Present, SS = 0.2V
V
♦
Measured VREF (0.8V) - VFB
TIMERS: SOFTSTART
SS Charge Current:
SS Discharge Current:
10
µA
1
PROTECTION: SHORT CIRCUIT & THERMAL
Short Circuit Threshold Voltage
0.2
0.25
0.3
Hiccup Timeout
100
ms
Number of Allowable Clock Cycles
at 100% Duty Cycle
20
Cycles
VFB = 0.7V
VFB = 0V
Minimum GL Pulse After 20 Cycles
0.5
Cycles
VFB = 0.7V
Thermal Shutdown Temperature
145
°C
Thermal Recovery Temperature
135
°C
Thermal Hysteresis
10
°C
OUTPUT: NFET GATE DRIVERS
GH & GL Rise Times
35
50
ns
♦
Measured 10% to 90%
GH & GL Fall Times
30
40
ns
♦
Measured 90% to 10%
GL to GH Non Overlap Time
45
70
ns
♦
GH & GL Measured at 2.0V
SWN to GL Non Overlap Time
20
30
ns
♦
Measured SWN = 100mV to GL = 2.0V
GH & GL Pull Down Resistance
50
KΩ
PIN DESCRIPTION
PIN #
1
2
3
4
5
6
7
8
9
10
Date: 7/28/04
PIN NAME DESCRIPTION
VCC
Bias Supply Input. Connect to external 5V supply. Used to power internal circuits and
low side gate driver.
GL
High current driver output for the low side NFET switch. It is always low if GH is high or
during a fault. Resistor pull down ensure low state at low voltage.
GND
Ground Pin. The control circuitry of the IC and lower power driver are referenced to this
pin. Return separately from other ground traces to the (-) terminal of COUT.
VFB
Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the Error
Amplifier and serves as the output voltage feedback point for the Buck Converter. The
output voltage is sensed and can be adjusted through an external resistor divider.
Whenever VFB drops 0.25V below the positive reference, a short circuit fault is detected
and the IC enters hiccup mode.
COMP
Output of the Error Amplifier. It is internally connected to the non-inverting input of the
PWM comparator. An optimal filter combination is chosen and connected to this pin and
either ground or VFB to stabilize the voltage mode loop.
UVIN
UVLO input for VIN voltage. Connect a resistor divider between VIN and UVIN to set
minimum operating voltage.
SS
Soft Start. Connect an external capacitor between SS and GND to set the soft start rate
based on the 10µA source current. The SS pin is held low via a 1mA (min) current during
all fault conditions.
SWN
Lower supply rail for the GH high-side gate driver. Connect this pin to the switching node
at the junction between the two external power MOSFET transistors.
GH
High current driver output for the high side NFET switch. It is always low if GL is high or
during a fault. Resistor pull down ensure low state at low voltage.
BST
High side driver supply pin. Connect BST to the external boost diode and capacitor as
shown in the Typical Application Circuit on page 1. High side driver is connected between
BST pin and SWN pin.
SP6137 Wide Input, 900KHz Synchronous PWM Controll
3
© Copyright 2004 Sipex Corporation
FUNCTIONAL DIAGRAM
5 COMP
VCC
100% Protection Logic
CLR
COUNT 20
CLOCK
PULSES
PWM LOOP
VFBINT
10 BST
RESET
DOMINANT
Gm ERROR AMPLIFIER
VPOS
VFB
FAULT
CLK
Gm
FAULT
R
VCC
VCC
Q
FAULT
9 GH
SYNCHRONOUS
DRIVER
QPWM
S
8 SWN
2 GL
10 µA
SS 7
SOFTSTART INPUT
600 kHZ
POS REF
RAMP = 1.1V
CLK
CLOCK PULSE GENERATOR
FAULT
0.4 V
GL HOLD OFF
SS
REFERENCE
CORE
VCC 1
0.8V
1.7 V
1.7 V
REF OK
3 GND
ASYNC. STARTUP
COMPARATOR
THERMAL AND SHORT CIRCUIT PROTECTION
THERMAL
SHUTDOWN
145°C ON
135°C OFF
PWRFLT
MFLT
UVLO COMPARATORS
0.25V
SHORT CIRCUIT
DETECTION
VPOS
REF OK
VFBINT
Q
PWRFLT
4.25 V ON
4.05 V OFF
UVIN
R
SET
DOMINANT
VCC UVLO
REF OK
6
2.50 V ON
2.20 V OFF
FAULT
SET
DOMINANT
S
R
CLK
100ms Delay
COUNTER
Q
VIN UVLO
Logic
Delay
CLR
S
POWER OK ONCE LOGIC
MFLT
REF OK
THEORY OF OPERATION
General Overview
The SP6137 is a fixed frequency, voltage mode,
synchronous PWM controller optimized for high
efficiency. The part has been designed to be
especially attractive for split plane applications
utilizing 5V to power the controller and 2.5V to
20V for step down conversion.
The SP6137 contains two unique control features that are very powerful in distributed applications. First, asynchronous driver control is
enabled during start up to prohibit the low side
NFET from pulling down the output until the
high side NFET has attempted to turn on. Second, a 100% duty cycle timeout ensures that the
low side NFET is periodically enhanced during
extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the BST
capacitor during very large duty ratios.
The heart of the SP6137 is a wide bandwidth
transconductance amplifier designed to accommodate Type II and Type III compensation
schemes. A precision 0.8V reference present on
the positive terminal of the error amplifier permits the programming of the output voltage
down to 0.8V via the VFB pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp and PWM
control logic are governed by the internal oscillator that accurately sets the PWM frequency to
900kHz.
Date: 7/28/04
The SP6137 also contains a number of valuable
protection features. A programmable input (VIN)
UVLO allows a user to set the exact value at
which the conversion voltage is at a safe point to
begin down conversion, and an internal VCC
UVLO ensures that the controller itself has
enough voltage to properly operate. Other pro-
SP6137 Wide Input, 900KHz Synchronous PWM Controll
4
© Copyright 2004 Sipex Corporation
THEORY OF OPERATION: Continued
Hiccup
tection features include thermal shutdown and
short-circuit detection. In the event that either a
thermal, short-circuit, or UVLO fault is detected, the SP6137 is forced into an idle state
where the output drivers are held off for a finite
period before a re-start is attempted.
Upon the detection of a power, thermal, or shortcircuit fault, the SP6137 is forced into an idle
state for 100mS (typical). The SS and COMP
pins are immediately pulled low, and the gate
drivers are held off for the duration of the
timeout period. Power and thermal faults have
to be removed before a restart may be attempted,
whereas, a short-circuit fault is internally cleared
shortly after the fault latch is set. Therefore, a
restart attempt is guaranteed every 100mS (typical) as long as the short-circuit condition persists.
Under Voltage Lock Out (UVLO)
The SP6137 contains two separate UVLO comparators to monitor the bias (VCC) and conversion (VIN) voltages independently. The VCC
UVLO threshold is internally set to 4.25V,
whereas the VIN UVLO threshold is programmable through the UVIN pin. When the UVIN
pin is greater than 2.5V, the SP6137 is permitted
to start up pending the removal of all other
faults. Both the VCC and VIN UVLO comparators have been designed with hysteresis to prevent noise from resetting a fault.
Thermal and Short-Circuit
Protection
Because the SP6137 is designed to drive large
NFETs running at high current, there is a chance
that either the controller or power converter will
become too hot. Therefore, an internal thermal
shutdown (145°C) has been included to prevent
the IC from malfunctioning at extreme temperatures.
Soft Start
“Soft Start” is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source current. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor.
A short-circuit detection comparator has also
been included in the SP6137 to protect against
the accidental short or sever build up of current
at the output of the power converter. This comparator constantly monitors the positive and
negative terminals of the error amplifier, and if
the VFB pin ever falls more than 250mV (typical) below the positive reference, a short-circuit
fault is set. Because the SS pin overrides the
internal 0.8V reference during soft start, the
SP6137 is capable of detecting short-circuit
faults throughout the duration of soft start as
well as in regular operation.
IVIN = COUT * DVOUT / DTSoft-start
The SP6137 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10uA pull up current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
Error Amplifier and Voltage Loop
As stated before, the heart of the SP6137 voltage
error loop is a high performance, wide bandwidth transconductance amplifier. Because of
the amplifier’s current limited (+/-150µA)
transconductance, there are many ways to compensate the voltage loop or to control the COMP
pin externally. If a simple, single pole, single
IVIN = COUT * DVOUT *10µA / (CSS * 0.8V)
Date: 7/28/04
SP6137 Wide Input, 900KHz Synchronous PWM Controll
5
© Copyright 2004 Sipex Corporation
THEORY OF OPERATION: Continued
zero response is required, then compensation
can be a simple as an RC to ground. If a more
complex compensation is required, then the
amplifier has enough bandwidth (45° at 4 MHz)
and enough gain (60dB) to run Type III compensation schemes with adequate gain and phase
margins at cross over frequencies greater than
50kHz.
GATE DRIVER TEST CONDITIONS
90%
GH(GL)
2V
FALL TIME
10%
90%
RISE TIME
2V
GL(GH)
10%
NON-OVERLAP
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensure proper 0% to 100% duty cycle capability.
The voltage loop also includes two other very
important features. One is an asynchronous start
up mode. Basically, the GL driver can not turn
on unless the GH driver has attempted to turn on
or the SS pin has exceeded 1.7V. This feature
prevents the controller from “dragging down”
the output voltage during startup or in fault
modes. The second feature is a 100% duty cycle
timeout that ensures synchronized refreshing of
the BST capacitor at very high duty ratios. In the
event that the GH driver is on for 20 continuous
clock cycles, a reset is given to the PWM flip
flop half way through the 21st cycle. This forces
GL to rise for the remainder of the cycle, in turn
refreshing the BST capacitor.
V(BST)
GH
Voltage
V(SWN)
V(VCC)
GL
Voltage
0V
V(VIN)
SWN
Voltage
-0V
-V(Diode) V
V(VIN)+V(VCC)
BST
Voltage
V(VCC)
TIME
Gate Drivers
The SP6137 contains a pair of powerful 2Ω
SOURCE and 1.5Ω SINK drivers. These state
of the art drivers are designed to drive external
NFETs capable of handling up to 30A. Rise,
fall, and non-overlap times have all been minized
to achieve maximum efficiency. All drive pins
GH, GL & SWN are monitored continuously to
ensure that only one external NFET is ever on at
any given time.
Date: 7/28/04
SP6137 Wide Input, 900KHz Synchronous PWM Controll
6
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION
Inductor Selection
I PEAK = I OUT (max) +
There are many factors to consider in selecting
the inductor including cost, efficiency, size and
EMI. In a typical SP6137 circuit, the inductor is
chosen primarily for value, saturation current
and DC resistance. Increasing the inductor value
will decrease output voltage ripple, but degrade
transient response. Low inductor values provide
the smallest size, but cause large ripple currents,
poor efficiency and more output capacitance to
smooth out the larger ripple current. The inductor must also be able to handle the peak current
at the switching frequency without saturating,
and the copper resistance in the winding should
be kept as low as possible to minimize resistive
power loss. A good compromise between size,
loss and cost is to set the inductor ripple current
to be within 20% to 40% of the maximum output
current.
and provide low core loss at the high switching
frequency. Low cost powdered iron cores have
a gradual saturation characteristic but can introduce considerable ac core loss, especially when
the inductor value is relatively low and the
ripple current is high. Ferrite materials, on the
other hand, are more expensive and have an
abrupt saturation characteristic with the inductance dropping sharply when the peak design
current is exceeded. Nevertheless, they are preferred at high switching frequencies because
they present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials are better
choice for all but the most cost sensitive applications.
The switching frequency and the inductor operating point determine the inductor value as follows:
L=
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To minimize copper losses, the winding resistance needs
to be minimized, but this usually comes at the
expense of a larger inductor. Core losses have a
more significant contribution at low output current where the copper losses are at a minimum,
and can typically be neglected at higher output
currents where the copper losses dominate. Core
loss information is usually available from the
magnetic vendor.
VOUT (V IN (max) − VOUT )
VIN (max) FS Kr I OUT ( max)
where:
Fs = switching frequency
Kr = ratio of the ac inductor ripple current to the
maximum output current
The peak to peak inductor ripple current is:
I PP =
The copper loss in the inductor can be calculated
using the following equation:
VOUT (VIN (max) − VOUT )
PL( Cu) = I L2 ( RMS ) RWINDING
VI N (max) FS L
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
IL(RMS) = IOUT(max) 1 + 1
3
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency requirements. The core must be large enough not to
saturate at the peak inductor current
Date: 7/28/04
I PP
2
SP6137 Wide Input, 900KHz Synchronous PWM Controll
7
(
IPP
IOUT(max)
)
2
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION: Continued
Output Capacitor Selection
FS = Switching Frequency
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resistive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the additional current demanded by the load until the
SP6137CU adjusts the inductor current to the
new value.
D = Duty Cycle
COUT = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source current of the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN. Most of
this current is supplied by the input bypass
capacitors. The RMS value of input capacitor
current is determined at the maximum output
current and under the assumption that the peak
Therefore the capacitance must be large enough
so that the output voltage is help up while the
inductor current ramps up or down to the value
corresponding to the new load current. Additionally, the ESR in the output capacitor causes
a step in the output voltage equal to the current.
Because of the fast transient response and inherent 100% and 0% duty cycle capability provided
by the SP6137CU when exposed to output load
transient, the output capacitor is typically chosen for ESR, not for capacitance value.
to peak inductor ripple current is low, it is given
by:
ICIN(rms) = IOUT(max) √D(1 - D)
The worse case occurs when the duty cycle D is
50% and gives an RMS current value equal to
IOUT/2.
Select input capacitors with adequate ripple
current rating to ensure reliable operation.
The output capacitor’s ESR, combined with the
inductor ripple current, is typically the main
contributor to output voltage ripple. The maximum allowable ESR required to maintain a
specified output voltage ripple can be calculated
by:
The power dissipated in the input capacitor is:
2
PCIN = ICIN
( rms ) R ESR ( CIN )
RESR ≤ ∆VOUT
IPK-PK
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency. The input voltage ripple
primarily depends on the input capacitor ESR
and capacitance. Ignoring the inductor ripple
current, the input voltage ripple can be determined by:
where:
∆VOUT = Peak to Peak Output Voltage Ripple
IPK-PK = Peak to Peak Inductor Ripple Current
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
(
∆VOUT = IPP (1 – D)
COUTFS
Date: 7/28/04
where:
)
∆ VIN = I out (max) RE SR (CIN ) +
I OUT ( MAX )VOUT (VI N − VOUT )
FS C INV IN
2
2
+ (IPPRESR)2
SP6137 Wide Input, 900KHz Synchronous PWM Controll
8
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION: Continued
The capacitor type suitable for the output capacitors can also be used for the input capacitors.
The total power losses of the top MOSFET are the
sum of switching and conduction losses. For synchronous buck converters of efficiency over 90%,
allow no more than 4% power losses for high or
low side MOSFETs. For input voltages of 3.3V
and 5V, conduction losses often dominate switching losses. Therefore, lowering the RDS(ON) of the
MOSFETs always improves efficiency even
though it gives rise to higher switching losses due
to increased Crss.
However, exercise extra caution when tantalum
capacitors are considered. Tantalum capacitors are
known for catastrophic failure when exposed to
surge current, and input capacitors are prone to
such surge current when power supplies are connected “live” to low impedance power sources.
MOSFET Selection
The losses associated with MOSFETs can be
divided into conduction and switching losses.
Conduction losses are related to the on resistance
of MOSFETs, and increase with the load current.
Switching losses occur on each on/off transition
when the MOSFETs experience both high current
and voltage. Since the bottom MOSFET switches
current from/to a paralleled diode (either its own
body diode or a Schottky diode), the voltage across
the MOSFET is no more than 1V during switching
transition. As a result, its switching losses are
negligible. The switching losses are difficult to
quantify due to all the variables affecting turn on/
off time. However, the following equation provides an approximation on the switching losses
associated with the top MOSFET driven by SP6137.
Top and bottom MOSFETs experience unequal
conduction losses if their on time is unequal. For
applications running at large or small duty cycle, it
makes sense to use different top and bottom
MOSFETs. Alternatively, parallel multiple
MOSFETs to conduct large duty factor.
RDS(ON) varies greatly with the gate driver voltage.
The MOSFET vendors often specify RDS(ON) on
multiple gate to source voltages (VGS), as well as
provide typical curve of RDS(ON) versus VGS. For
5V input, use the RDS(ON) specified at 4.5V VGS. At
the time of this publication, vendors, such as
Fairchild, Siliconix and International Rectifier,
have started to specify RDS(ON) at VGS less than 3V.
This has provided necessary data for designs in
which these MOSFETs are driven with 3.3V and
made it possible to use SP6137 in 3.3V only
applications.
PSH (max) = 12C rssV IN (max) I OUT (max) FS
where
Crss = reverse transfer capacitance of the top
MOSFET
Thermal calculation must be conducted to ensure
the MOSFET can handle the maximum load current. The junction temperature of the MOSFET,
determined as follows, must stay below the maximum rating.
Switching losses need to be taken into account for
high switching frequency, since they are directly
proportional to switching frequency. The conduction losses associated with top and bottom
MOSFETs are determined by:
TJ ( max) = T A (max) +
2
PCH (max) = RDS (ON ) I OUT (max) D
PMOSFET (max)
Rθ JA
where
2
PCL(max) = R DS (ON ) I OUT (max) (1 − D)
TA(max) = maximum ambient temperature
PMOSFET(max) = maximum power dissipation of the MOSFET
RΘJA = junction to ambient thermal resistance.
where
PCH(max) = conduction losses of the high side
MOSFET
PCL(max) = conduction losses of the low side
MOSFET
RΘJA of the device depends greatly on the board
layout, as well as device package. Significant
RDS(ON) = drain to source on resistance.
Date: 7/28/04
SP6137 Wide Input, 900KHz Synchronous PWM Controll
9
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION: Continued
diode is equal to input voltage, and the diode
must be able to handle the peak current equal to
the maximum load current.
thermal improvement can be achieved in the maximum power dissipation through the proper design
of copper mounting pads on the circuit board. For
example, in a SO-8 package, placing two 0.04
square inches copper pad directly under the package, without occupying additional board space,
can increase the maximum power from approximately 1 to 1.2W. For DPAK package, enlarging
the tap mounting pad to 1 square inches reduces the
RΘJA from 96°C/W to 40°C/W.
The power dissipation of the Schottky diode is
determined by
PDIODE = 2VFIOUTTNOLFS
where
Schottky Diode Selection
TNOL = non-overlap time between GH and GL.
When paralleled with the bottom MOSFET, an
optional Schottky diode can improve efficiency
and reduce noises. Without this Schottky diode,
the body diode of the bottom MOSFET conducts the current during the non-overlap time
when both MOSFETs are turned off. Unfortunately, the body diode has high forward voltage
and reverse recovery problem. The reverse recovery of the body diode causes additional
switching noises when the diode turns off. The
Schottky diode alleviates these noises and additionally improves efficiency thanks to its low
forward voltage. The reverse voltage across the
VF = forward voltage of the Schottky diode.
Loop Compensation Design
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to crossover at the selected frequency FCO, the gain of
the error amplifier has to compensate for the
attenuation caused by the rest of the loop at this
frequency.
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
VREF
(Volts)
+
_
PWM Stage
GPWM Gain
Block
VIN
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
VRAMP_PP
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
Output Stage
GOUT (s) Gain
Block
[S^2LCOUT+S(RESR+RDC) COUT+1]
VOUT
(Volts)
Notes: RESR = Output Capacitor Equivalent Series Resistance.
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
GFBK Gain Block
R2
VFBK
(Volts)
(R1 + R2)
or
VREF
VOUT
SP6134 Voltage Mode Control Loop with Loop Dynamic
Date: 7/28/04
SP6137 Wide Input, 900KHz Synchronous PWM Controll
10
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION: Continued
The goal of loop compensation is to manipulate
loop frequency response such that its gain crosses
When the output capacitors are of a Ceramic
Type, the SP6137CU Evaluation Board requires
a Type III compensation circuit to give a phase
boost of 180° in order to counteract the effects of
an under damped resonance of the output filter
at the double pole frequency.
over 0db at a slope of -20db/dec. The first step
of compensation design is to pick the loop
crossover frequency. High crossover frequency
is desirable for fast transient response, but often
jeopardizes the system stability. Crossover frequency should be higher than the ESR zero but
less than 1/5 of the switching frequency. The
ESR zero is contributed by the ESR associated
with the output capacitors and can be determined by:
Gain
(dB)
Error Amplify Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
1
ƒZ(ESR) =
20 Log (RZ2/R1)
1/6.28 (RZ3) (CZ3)
1/6.28 (RZ2) (CP1)
The next step is to calculated the complex conjugate poles contributed by the LC output filter,
1/6.28 (R1) (CZ2)
1/6.28(R22) (CZ2)
1/6.28 (R1) (CZ3)
2π COUT RESR
Frequency
(Hz)
Bode Plot of Type III Error Amplify Compensation.
1
ƒP(LC) =
2π
L COUT
INDUCTORS - SURFACE MOUNT
Inductor Specification
Inductance
(uH)
Manufacturer/Part No.
Series R
mΩ
ISAT
(a)
Size
LxW(mm)
Ht.(mm)
Inductor Type
Manufaturer
Website
2.7
2.7
3.3
Easy Magnet SC5018-2R7M
TDK RLF 12560T-2R7N110
Coilcraft DO5010P-332HC
4.30
4.50
8.60
12.0
12.2
17.0
12.6x12.6
12.5x12.8
14.7x15.2
4.5
6.0
8.0
Shielded Ferrite Core
Shielded Ferrite Core
Unshielded Ferrite Core
inter-technical.com
tdk.com
coilcraft.com
1.2
1.2
1.5
1.9
Easy Magnet SC5018-1R2M
Inter-Technical SC4015-1R2M
Coilcraft DO5010P-152HC
TDK RLF 12560T-1R9N120
1.96
4.37
4.00
3.60
20.0
17.0
25.0
13.2
12.6x12.6
10.0x10.0
14.7x15.2
12.5x12.8
4.5
3.8
8.0
6.0
Shielded Ferrite Core
Shielded Ferrite Core
Unshielded Ferrite Core
Shielded Ferrite Core
inter-technical.com
inter-technical.com
coilcraft.com
tdk.com
CAPACITORS -SURFACE MOUNT
Capacitance
(uF)
Manufacturer/Part No.
ESR
Ω (max)
Ripple Current
(A)@45°C
Size
LxW(mm) Ht.(mm)
Voltage
(V)
Capacitor
Type
Manufaturer
Website
22
TDK C3225X5R1C226M
0.002
4.00
3.2x2.5
2.0
16.0
X5R Ceramic
tdk.com
47
TDK C3225X5ROJ476M
0.002
4.00
3.2x2.5
2.5
6.3
X5R Ceramic
tdk.com
MOSFET - Surface Mount
MOSFET
Manufacturer/Part No.
RDS (on)
Ω (max)
ID Current
(A)
Qg
nC(Typ)
Qg
nC(Max)
Voltage
(V)
Foot Print
Manufaturer
Website
fairchildsemi.com
N-Channel
Fairchild Semi FDS6676S
0.006
14.50
43
60.0
30.0
SO-8
N-Channel
Fairchild Semi FD7088N3
0.005
21.10
37
48.0
30.0
SO-8
fairchildsemi.com
30.0
SO-8
vishay.com
N-Channel
Vishay Si4336DY
0.004
25.0
32
50.0
Note: Components highlighted in Bold are those used on the SP6134 Evaluation Board.
Table 1. Input and Output Stage Components Selection Charts.
Date: 7/28/04
SP6137 Wide Input, 900KHz Synchronous PWM Controll
11
© Copyright 2004 Sipex Corporation
PACKAGE: 10 PIN MSOP
(ALL DIMENSIONS IN MILLIMETERS)
D
e1
Ø1
E/2
R1
R
E1
E
Gauge Plane
L2
Ø1
Seating Plane
Ø
L
L1
1
2
e
Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)
Dimensions in (mm)
10-PIN MSOP
JEDEC MO-187
(BA) Variation
MIN NOM MAX
A
-
-
1.1
A1
0
-
0.15
A2
0.75
b
0.17
-
0.27
c
0.08
-
0.23
D
0.85
0.95
(b)
WITH PLATING
3.00 BSC
E
4.90 BSC
E1
3.00 BSC
e
0.50 BSC
e1
c
2.00 BSC
L
0.4
0.60
0.80
L1
-
0.95
-
L2
-
0.25
-
N
-
10
-
R
0.07
-
-
R1
0.07
-
Ø
0º
Ø1
0º
BASE METAL
D
A2
-
A
8º
-
b
15º
A1
1
Date: 7/28/04
SP6137 Wide Input, 900KHz Synchronous PWM Controll
12
© Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Part Number
Temperature
Topmark
Package
SP6137EU........................-40°C to +85°C...................SP6137CU ........................... 10 Pin MSOP
SP6137EU/TR..................-40°C to +85°C...................SP6137CU ........................... 10 Pin MSOP
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6137EU/TR = standard; SP6137EU-L/TR = lead free
/TR = Tape and Reel
Pack quantity is 2500 for MSOP.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 7/28/04
SP6137 Wide Input, 900KHz Synchronous PWM Controll
13
© Copyright 2004 Sipex Corporation