SIPEX SP7652ER-L/TR

®
SP7652
Preliminary
Wide Input Voltage Range 6A, 600kHz, Buck Regulator
SP7652
FEATURES
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DFN PACKAGE
7mm x 4mm
2.5V to 28V Step Down Achieved Using Dual Input
Output Voltage down to 0.8V
6A Output Capability (Up to 8A with Air Flow)
Built in Low RDSON Power FETs (15 mΩ typ)
Highly Integrated Design, Minimal Components
600 kHz Fixed Frequency Operation
UVLO Detects Both VCC and VIN
Over Temperature Protection
Short Circuit Protection with Auto-Restart
Wide BW Amp Allows Type II or III Compensation
Programmable Soft Start
Fast Transient Response
High Efficiency: Greater than 92% Possible
Asynchronous Start-Up into a Pre-Charged Output
Small 7mm x 4mm DFN Package
PGND 1
26 LX
TOP VIEW
PGND 2
Heatsink Pad 1
Connect to Lx
PGND 3
25 LX
24 LX
GND 4
23 LX
VFB 5
2 2 VCC
COMP 6
21 GND
Heatsink pad 2
Connect to GND
UVIN 7
20 GND
GND 8
19 GND
SS 9
18 BST
VIN 10
17 NC
Heatsink pad 3
Connect to VIN
VIN 11
16 LX
VIN 12
15 LX
VIN 13
14 LX
Now Available in Lead Free Packaging
DESCRIPTION
The SP7652 is a synchronous step-down switching regulator optimized for high efficiency. The part is designed to be
especially attractive for dual supply, 12V step down with 5V used to power the controller. This lower VCC voltage
minimizes power dissipation in the part. The SP7652 is designed to provide a fully integrated buck regulator solution
using a fixed 600kHz frequency, PWM voltage mode architecture. Protection features include UVLO, thermal shutdown
and output short circuit protection. The SP7652 is available in the space saving DFN package.
TYPICAL APPLICATION CIRCUIT
100pF
21.5k,1%
RSET
(note 2)
U1
1nF
12K
2
3
4
5
6
7
CF1
100pF
8
9
ENABLE
10
CSS
22nF
VIN
VOUT
3.3V
0-8A
68.1k,1%
SP7652
1
22pF
5.1K
11
12
13
PGND
LX
PGND
LX
PGND
LX
GND
LX
VFB
VCC
COMP
GND
UVIN
GND
GND
GND
SS
BST
VIN
NC
VIN
LX
VIN
LX
VIN
LX
26
25
1.5uH, Irate=8A
47uF
24
Ceramic
X5R 6.3V
23
5V VCC
22
21
20
CVCC
1uF
19
18
17
5.1
SD101AWS
16
15
14
1uF
2.5V - 20V
Notes:
C1
22uF
1. U1 Bottom-Side Layout should has
three contacts isolated from one
another VIN and SWNODE and GND
2. RSET = 54.48 / (Vout - 0.8V)
(kOhm)
GND
Date: 08/12/04
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
1
© Copyright 2004 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
GH ......................................................................... -0.3V to BST+0.3V
GH-SWN ......................................................................................... 7V
All other pins .......................................................... -0.3V to VCC+0.3V
VCC .................................................................................................. 7V
VIN ........................................................................................................................................... 30V
ILX ............................................................................................................................................ 10A
BST ............................................................................................... 35V
BST-SWN ......................................................................... -0.3V to 7V
SWN ................................................................................... -1V to 30V
Storage Temperature .................................................. -65°C to 150°C
Power Dissipation .................................................... Internally Limited
Lead Temperature (Soldering, 10 sec) ...................................... 300°C
ESD Rating .......................................................................... 2kV HBM
Thermal Resistance ϑJC .................................................................................... 5°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C<Tj<125°C, 4.5V < VCC < 5.5V, 3V<Vin<28V, BST=LX + 5V, LX =
GND = 0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
VCC Supply Current (No switching)
1.5
3
mA
VCC Supply Current (switching)
11
TBD
mA
BST Supply Current (No switching)
0.2
0.4
mA
BST Supply Current (switching)
5.0
TBD
mA
CONDITIONS
QUIESCENT CURRENT
VFB =0.9V
♦
VFB =0.9V
♦
PROTECTION: UVLO
VCC UVLO Start Threshold
4.00
4.25
4.5
V
VCC UVLO Hysteresis
100
200
300
mV
UVIN Start Threshold
2.3
2.5
2.65
V
UVIN Hysteresis
200
300
400
mV
1
µA
UVIN Input Current
♦
UVIN= 3.0V
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference
0.792
0.800
0.808
V
Error Amplifier Reference
Over Line and Temperature
0.788
0.800
0.812
V
2X Gain Config., Measure
VFB; VCC =5 V, T=25ºC
♦
Error Amplifier Transconductance
6
mA/V
Error Amplifier Gain
60
dB
No Load
COMP Sink Current
150
µA
VFB =0.9V, COMP= 0.9V
COMP Source Current
150
µA
VFB =0.7V, COMP= 2..2V
VFB Input Bias Current
50
nA
VFB = 0.8V
Internal Pole
4
MHz
COMP Clamp
2.5
V
COMP Clamp Temp. Coefficient
-2
mV/ºC
Date: 08/12/04
200
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
2
VFB =0.7V, TA=25ºC
© Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < TAMB < 85°C, -40°C<Tj<125°C, 4.5V < VCC < 5.5V, 3V<Vin<28V, BST=LX + 5V, LX =
GND = 0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.
The ♦ denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude
0.92
1.1
1.28
V
RAMP Offset
1.1
V
RAMP Offset Temp. Coefficient
-2
mV/ºC
GH Minimum Pulse Width
90
Maximum Controllable Duty Ratio
92
Maximum Duty Ratio
100
Internal Oscillator Ratio
420
180
97
600
720
ns
TA = 25ºC, RAMP COMP
until GH starts Switching
♦
%
Maximum Duty Ratio
Measured just before
pulsing begins
%
Valid for 20 cycles
kHz
♦
TIMERS: SOFTSTART
SS Charge Current:
10
SS Discharge Current:
µA
1
mA
♦
Fault Present, SS = 0.2V
V
♦
Measured VREF (0.8V) VFB
PROTECTION: Short Circuit & Thermal
Short Circuit Threshold Voltage
0.2
0.25
0.3
Hiccup Timeout
200
ms
VFB = 0.5V
Number of Allowable Clock Cycles
at 100% Duty Cycle
20
Cycles
Minimum GL Pulse After 20 Cycles
0.5
Cycles
VFB = 0.7V
Thermal Shutdown Temperature
145
ºC
VFB = 0.7V
Thermal Recovery Temperature
135
ºC
Thermal Hysteresis
10
ºC
High Side RDSON
15
mΩ
VCC = 5V ; IOUT = 6A TAMB
= 25ºC
Synchronous FET RDSON
15
mΩ
VCC = 5V ; IOUT = 6A TAMB
= 25ºC
OUTPUT: POWER STAGE
Maximum Output Current
Date: 08/12/04
6
A
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
3
© Copyright 2004 Sipex Corporation
PIN DESCRIPTION
Pin #
Pin Name
1-3
PGND
Ground connection for the synchronous rectifier
4,8,19-21
GND
Ground Pin. The control circuitry of the IC and lower power driver are
referenced to this pin. Return separately from other ground traces to the (-)
terminal of Cout.
VFB
Feedback Voltage and Short Circuit Detection pin. It is the inverting input
of the Error Amplifier and serves as the output voltage feedback point for
the Buck Converter. The output voltage is sensed and can be adjusted
through an external resistor divider. Whenever VFB drops 0.25V below the
positive reference, a short circuit fault is detected and the IC enters hiccup
mode.
6
COMP
Output of the Error Amplifier. It is internally connected to the inverting input
of the PWM comparator. An optimal filter combination is chosen and
connected to this pin and either ground or VFB to stabilize the voltage
mode loop.
7
UVIN
9
SS
Soft Start. Connect an external capacitor between SS and GND to set the
soft start rate based on the 10µA source current. The SS pin is held low
via a 1mA (min) current during all fault conditions.
10-13
VIN
Input connection to the high side N-channel MOSFET. Place a decoupling
capacitor between this pin and PGND.
14-16,23-26
LX
Connect an inductor between this pin and VOUT
22
V CC
Input for external 5V bias supply
17
NC
No Connect
5
Description
UVLO input for Vin voltage. Connect a resistor divider between VIN and
UVIN to set minimum operating voltage
THEORY OF OPERATION
General Overview
The SP7652 is a fixed frequency, voltage mode,
synchronous PWM regulator optimized for high
efficiency. The part has been designed to be
especially attractive for split plane applications
utilizing 5V to power the controller and 3V to
28V for step down conversion.
The SP7652 contains two unique control features that are very powerful in distributed applications. First, asynchronous driver control is
enabled during start up, to prohibit the low side
NFET from pulling down the output until the
high side NFET has attempted to turn on. Second, a 100% duty cycle timeout ensures that the
low side NFET is periodically enhanced during
extended periods at 100% duty cycle. This guarantees the synchronized refreshing of the BST
capacitor during very large duty ratios.
The heart of the SP7652 is a wide bandwidth
transconductance amplifier designed to accommodate Type II and Type III compensation
schemes. A precision 0.8V reference, present on
the positive terminal of the error amplifier permits the programming of the output voltage
down to 0.8V via the VFB pin. The output of the
error amplifier, COMP, which is compared to a
1.1V peak-to-peak ramp is responsible for trailing edge PWM control. This voltage ramp, and
PWM control logic are governed by the internal
oscillator that accurately sets the PWM frequency to 600kHz.
Date: 08/12/04
The SP7652 also contains a number of valuable
protection features. Programmable UVLO allows the user to set the exact VIN value at which
the conversion voltage can safely begin down
conversion, and an internal VCC UVLO ensures
that the controller itself has enough voltage to
properly operate. Other protection features in-
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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© Copyright 2004 Sipex Corporation
THEORY OF OPERATION
Thermal and Short-Circuit
Protection
clude thermal shutdown and short-circuit detection. In the event that either a thermal, shortcircuit, or UVLO fault is detected, the SP7652 is
forced into an idle state where the output drivers
are held off for a finite period before a re-start is
attempted.
Because the SP7652 is designed to drive large
output current, there is a chance that the power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
included to prevent the IC from malfunctioning
at extreme temperatures.
Soft Start
“Soft Start” is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source current. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor.
A short-circuit detection comparator has also
been included in the SP7652 to protect against
an accidental short at the output of the power
converter. This comparator constantly monitors
the positive and negative terminals of the error
amplifier, and if the VFB pin falls more than
250mV (typical) below the positive reference, a
short-circuit fault is set. Because the SS pin
overrides the internal 0.8V reference during soft
start, the SP7652 is capable of detecting shortcircuit faults throughout the duration of soft
start as well as in regular operation.
IVIN = COUT * (DVOUT / DTSOFT-START)
The SP7652 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10uA pull up current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
Handling of Faults:
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7652 is forced into
an idle state where the SS and COMP pins are
pulled low and the NFETS are held off. In the
event of UVLO fault, the SP7652 remains in this
idle state until the UVLO fault is removed.
Upon the detection of a thermal or short-circuit
fault, an internal 200ms timer is activated. In the
event of a short-circuit fault, a re-start is attempted immediately after the 200ms timeout
expires. Whereas, when a thermal fault is detected the 200ms delay continuously recycles
and a re-start cannot be attempted until the
thermal fault is removed and the timer expires.
IVIN = COUT * (DVOUT *10µA / (CSS * 0.8V)
Under Voltage Lock Out (UVLO)
The SP7652 contains two separate UVLO comparators to monitor the internal bias (VCC) and
conversion (VIN) voltages independently. The
VCC UVLO threshold is internally set to 4.25V,
whereas the VIN UVLO threshold is programmable through the UVIN pin. When the UVIN
pin is greater than 2.5V, the SP7652 is permitted
to start up pending the removal of all other
faults. Both the VCC and VIN UVLO comparators have been designed with hysteresis to prevent noise from resetting a fault.
Date: 08/12/04
Error Amplifier and Voltage Loop
Since the heart of the SP7652 voltage error loop
is a high performance, wide bandwidth
transconductance amplifier great care should be
taken to select the optimal compensation network. Because of the amplifier’s current limited (+/-150µA) transconductance, there are
many ways to compensate the voltage loop or to
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
5
© Copyright 2004 Sipex Corporation
THEORY OF OPERATION
control the COMP pin externally. If a simple,
single pole, single zero response is desired, then
compensation can be as simple as an RC to
ground. If a more complex compensation is
required, then the amplifier has enough bandwidth (45° at 4 MHz) and enough gain (60dB) to
run Type III compensation schemes with adequate gain and phase margins at cross over
frequencies greater than 50kHz.
VBST
GH
Voltage
VSWN
V(VCC)
GL
Voltage
0V
V(VIN)
The common mode output of the error amplifier
is 0.9V to 2.2V. Therefore, the PWM voltage
ramp has been set between 1.1V and 2.2V to
ensure proper 0% to 100% duty cycle capability.
The voltage loop also includes two other very
important features. One is an asynchronous start
up mode. Basically, the synchronous rectifier
can not turn on unless the high side NFET has
attempted to turn on or the SS pin has exceeded
1.7V. This feature prevents the controller from
“dragging down” the output voltage during
startup or in fault modes. The second feature is
a 100% duty cycle timeout that ensures synchronized refreshing of the BST capacitor at very
high duty ratios. In the event that the high side
NFET is on for 20 continuous clock cycles, a
reset is given to the PWM flip flop half way
through the 21st cycle. This forces GL to rise for
the cycle, in turn refreshing the BST capacitor.
SWN
Voltage
-0V
-V(Diode) V
V(VIN)+V(VCC)
BST
Voltage
V(VCC)
TIME
Setting Output Voltages
The SP7652 can be set to different output
voltages. The relationship in the following
formula is based on a voltage divider from the
output to the feedback pin VFB, which is set
to an internal reference voltage of 0.80V.
Standard 1% metal film resistors of surface
mount size 0603 are recommended.
Power MOSFETs
The SP7652 contains a pair of integrated low
resistance N MOSFETs designed to drive up to
6A of output current. Maximum output current
could be limited by thermal limitations of a
particular application. The SP7652 incorporates a built-in over-temperature protection to
prevent internal overheating.
Date: 08/12/04
Vout = 0.80V ( R1 / R2 + 1 ) => R2 = R1 / [ (
Vout / 0.80V ) – 1 ]
Where R1 = 68.1KΩ and for Vout = 0.80V
setting, simply remove R2 from the board.
Furthermore, one could select the value of R1
and R2 combination to meet the exact output
voltage setting by restricting R1 resistance
range such that 50KΩ < R1 < 100KΩ for
overall system loop stability.
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
6
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION
saturate at the peak inductor current
Inductor Selection
There are many factors to consider in selecting
the inductor including core material, inductance
vs. frequency, current handling capability, efficiency, size and EMI. In a typical SP7652 circuit, the inductor is chosen primarily by operating frequency, saturation current and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. Low inductor values provide the
smallest size, but cause large ripple currents,
poor efficiency and more output capacitance to
smooth out the larger ripple current. The inductor must be able to handle the peak current at the
switching frequency without saturating, and the
copper resistance in the winding should be kept
as low as possible to minimize resistive power
loss. A good compromise between size, loss and
cost is to set the inductor ripple current to be
within 20% to 40% of the maximum output
current.
I PEAK = I OUT (max) +
and provide low core loss at the high switching
frequency. Low cost powdered iron cores are
inappropriate for 900kHz operation. Gapped
ferrite inductors are widely available for consideration. Select devices that have operating data
shown up to 1MHz. Ferrite materials, on the
other hand, are more expensive and have an
abrupt saturation characteristic with the inductance dropping sharply when the peak design
current is exceeded. Nevertheless, they are preferred at high switching frequencies because
they present very low core loss and the design
only needs to prevent saturation. In general,
ferrite or molypermalloy materials are better
choice for all but the most cost sensitive applications.
The switching frequency and the inductor operating point determine the inductor value as follows:
L=
I PP
2
Optimizing Efficiency
The power dissipated in the inductor is equal to
the sum of the core and copper losses. To minimize copper losses, the winding resistance needs
to be minimized, but this usually comes at the
expense of a larger inductor. Core losses have a
more significant contribution at low output current where the copper losses are at a minimum,
and can typically be neglected at higher output
currents where the copper losses dominate. Core
loss information is usually available from the
magnetic vendor. Proper inductor selection can
affect the resulting power supply efficiency by
more than 15-20%!
VOUT (V IN (max) − VOUT )
VIN (max) FS Kr I OUT ( max)
where:
Fs = switching frequency
Kr = ratio of the ac inductor ripple current to the
maximum output current
The peak to peak inductor ripple current is:
The copper loss in the inductor can be calculated
using the following equation:
I PP =
VOUT (VIN (max) − VOUT )
PL( Cu) = I L2 ( RMS ) RWINDING
VI N (max) FS L
where IL(RMS) is the RMS inductor current that
can be calculated as follows:
Once the required inductor value is selected, the
proper selection of core material is based on
peak inductor current and efficiency requirements. The core must be large enough not to
Date: 08/12/04
IL(RMS) = IOUT(max) 1 + 1
3
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
7
(
IPP
IOUT(max)
)
2
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION
Output Capacitor Selection
The required ESR (Equivalent Series Resistance) and capacitance drive the selection of the
type and quantity of the output capacitors. The
ESR must be small enough that both the resistive voltage deviation due to a step change in the
load current and the output ripple voltage do not
exceed the tolerance limits expected on the
output voltage. During an output load transient,
the output capacitor must supply all the additional current demanded by the load until the
SP7652 adjusts the inductor current to the new
value.
FS = Switching Frequency
D = Duty Cycle
COUT = Output Capacitance Value
Input Capacitor Selection
The input capacitor should be selected for ripple
current rating, capacitance and voltage rating.
The input capacitor must meet the ripple current
requirement imposed by the switching current.
In continuous conduction mode, the source current of the high-side MOSFET is approximately
a square wave of duty cycle VOUT/VIN. Most of
this current is supplied by the input bypass
capacitors. The RMS value of input capacitor
current is determined at the maximum output
current and under the assumption that the peak
In order to maintain VOUT, the capacitance must
be large enough so that the output voltage is held
up while the inductor current ramps up or down
to the value corresponding to the new load
current. Additionally, the ESR in the output
capacitor causes a step in the output voltage
equal to the current. Because of the fast transient
response and inherent 100% and 0% duty cycle
capability provided by the SP7652 when exposed to output load transient, the output capacitor is typically chosen for ESR, not for
capacitance value.
to peak inductor ripple current is low, it is given
by:
ICIN(rms) = IOUT(max) √D(1 - D)
The worse case occurs when the duty cycle D is
50% and gives an RMS current value equal to
IOUT/2.
The output capacitor’s ESR, combined with the
inductor ripple current, is typically the main
contributor to output voltage ripple. The maximum allowable ESR required to maintain a
specified output voltage ripple can be calculated
by:
RESR
Select input capacitors with adequate ripple
current rating to ensure reliable operation.
The power dissipated in the input capacitor is:
2
PCIN = ICIN
( rms ) R ESR ( CIN )
≤ ∆VOUT
IPK-PK
This can become a significant part of power
losses in a converter and hurt the overall energy
transfer efficiency. The input voltage ripple
primarily depends on the input capacitor ESR
and capacitance. Ignoring the inductor ripple
current, the input voltage ripple can be determined by:
where:
∆VOUT = Peak to Peak Output Voltage Ripple
IPK-PK = Peak to Peak Inductor Ripple Current
The total output ripple is a combination of the
ESR and the output capacitance value and can
be calculated as follows:
(
∆VOUT = IPP (1 – D)
COUTFS
Date: 08/12/04
)
2
+ (IPPRESR)2
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
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© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION
∆ VIN = I out (max) RE SR (CIN ) +
High cross over frequency is desirable for fast
transient response, but often jeopardizes the
system stability. Cross over frequency should
be higher than the ESR zero but less than 1/5 of
the switching frequency. The ESR zero is contributed by the ESR associated with the output
capacitors and can be determined by:
I OUT ( MAX )VOUT (VI N − VOUT )
FS C INV IN
2
The capacitor type suitable for the output capacitors can also be used for the input capacitors.
However, exercise extra caution when tantalum
capacitors are used. Tantalum capacitors are known
for catastrophic failure when exposed to surge
current, and input capacitors are prone to such
surge current when power supplies are connected
“live” to low impedance power sources.
1
ƒZ(ESR) =
2π COUT RESR
Loop Compensation Design
The next step is to calculate the complex conjugate poles contributed by the LC output filter,
The open loop gain of the whole system can be
divided into the gain of the error amplifier,
PWM modulator, buck converter output stage,
and feedback resistor divider. In order to cross
over at the selected frequency FCO, the gain of
the error amplifier has to compensate for the
attenuation caused by the rest of the loop at this
frequency.
2π
Type III Voltage Loop
Compensation
GAMP (s) Gain Block
+
_
L COUT
When the output capacitors are of a Ceramic
Type, the SP7652 Evaluation Board requires a
Type III compensation circuit to give a phase
boost of 180° in order to counteract the effects of
an under damped resonance of the output filter
at the double pole frequency.
The goal of loop compensation is to manipulate
loop frequency response such that its gain
crossesover 0db at a slope of -20db/dec. The
first step of compensation design is to pick the
loop cross over frequency.
VREF
(Volts)
1
ƒP(LC) =
PWM Stage
GPWM Gain
Block
Output Stage
GOUT (s) Gain
Block
VIN
(SRz2Cz2+1)(SR1Cz3+1)
(SRESRCOUT+ 1)
VRAMP_PP
SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1)
[S^2LCOUT+S(RESR+RDC) COUT+1]
VOUT
(Volts)
Notes: RESR = Output Capacitor Equivalent Series Resistance.
RDC = Output Inductor DC Resistance.
VRAMP_PP = SP6132 Internal RAMP Amplitude Peak to Peak Voltage.
Condition: Cz2 >> Cp1 & R1 >> Rz3
Output Load Resistance >> RESR & RDC
Voltage Feedback
GFBK Gain Block
R2
VFBK
(Volts)
(R1 + R2)
or
VREF
VOUT
SP7652 Voltage Mode Control Loop with Loop Dynamic
Definitions:
RESR = Output Capacitor Equivalent Series Resistance
RDC = Output Inductor DC Resistance
RRAMP_PP = SP7652 internal RAMP Amplitude Peak to Peak Voltage
Conditions:
CZ 2 >> Cp1 and R1 >> RZ 3
Output Load Resistance >> RESR and RDC
Date: 08/12/04
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
9
© Copyright 2004 Sipex Corporation
APPLICATIONS INFORMATION
Gain
(dB)
Error Amplifier Gain
Bandwidth Product
Condition:
C22 >> CP1, R1 >> RZ3
1/6.28 (RZ3) (CZ3)
1/6.28 (RZ2) (CP1)
1/6.28 (R1) (CZ2)
1/6.28 (R1) (CZ3)
1/6.28(R22) (CZ2)
20 Log (RZ2/R1)
Frequency
(Hz)
Bode Plot of Type III Error Amplifier Compensation.
CP1
RZ3
CZ3
CZ2
RZ2
VOUT
R1
68.1k, 1%
5
VFB
R
SET
+
+
- 0.8V
R
SET
6
COMP
CF1
=54.48/ (VOUT -0.8) (kΩ)
Type III Error Amplifier Compensation Circuit
Date: 08/12/04
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
10
© Copyright 2004 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
SP7652 Effi. vs Iout Plots @
Vin=8V, 12V, 15V, and Vout=5.0V
96.0
SP7652 Vout vs Iout Plots @
Vin=8V, 12V, and 15V
4.96
Output Voltage (V)
94.0
Efficiency (%)
92.0
90.0
88.0
86.0
Vin=12V
Vin=8V
Vin=15V
84.0
82.0
4.955
4.95
Vin=12V
Vin=8V
Vin=15V
4.945
4.94
80.0
1
2
3
4
5
0
6
1
2
SP7652 Effi. vs Iout Plots @
Vin=5V, and Vout=3.3V
93.5
5
6
3.305
Output Voltage (V)
Efficiency (%)
4
SP7652 Vout vs Iout Plots @
Vin=5V, and Vout=3.3V
3.31
93.0
92.5
92.0
91.5
91.0
90.5
3.3
3.295
3.29
3.285
90.0
1
2
3
4
5
3.28
6
0
Load Current (A)
1
2
3
4
5
6
Load Current (A)
SP7652 Effi. vs Iout Plots @ Vin=3.3V, and Vout=0.8V
SP7652 Vout vs Iout Plots @ Vin=3.3V, and Vout=0.8V
80.0
79.0
0.794
Output Voltage (V)
78.0
Efficiency (%)
3
Load Current (A)
Load Current (A)
77.0
76.0
75.0
74.0
73.0
72.0
0.792
0.79
0.788
71.0
0.786
70.0
1
2
3
4
5
0
6
1
Date: 08/12/04
2
3
4
5
6
Load Current (A)
Load Current (A)
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
11
© Copyright 2004 Sipex Corporation
PACKAGE: 26 PIN DFN
D
(7 x 4 mm)
E
Top View
A
A3
A1
Side View
b
e
L
E2
D2
D2
D3
26 Pin DFN
SYMBOL
A
A1
A3
b
D
D2
D3
e
E
E2
L
Bottom View
DIMENSIONS in
(mm)
MIN NOM MAX
0.800 0.850 0.900
0.000
- 0.050
0.178 0.203 0.228
0.17
0.22
0.27
6.95
7.05
7.00
2.05
2.10
1.78 1.83
1.88
2.00
0.45
0.50
0.55
3.95
4.00
4.05
2.730 2.780 2.830
0.350 0.400 0.450
26 Pin DFN
Date: 08/12/04
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
12
© Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Part Number
Temperature
Package
SP7652ER/TR ......................................... -40°C to +85°C ................................. 26 Pin 7 X 4 DFN
SP7652ER-L/TR ..................................... -40°C to +85°C ............. (Lead Free) 26 Pin 7 X 4 DFN
/TR = Tape and Reel
Pack quantity is 3000 DFN.
Corporation
ANALOG EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Date: 08/12/04
SP7652 Wide Input Voltage Range 6A, 600kHz, Buck Regulator
13
© Copyright 2004 Sipex Corporation