CXD1257AR CCD Camera Timing Generator Description The CXD1257AR generates the timing pulses required by the CCD image sensors as well as signal processing circuits. 64 pin LQFP (Plastic) Features • NTSC and PAL compatible • Electronic shutter function • H-driver • Compatible with digital and analog camera systems • Standby function Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD Vss – 0.5 to +7.0 V • Input voltage VI Vss – 0.5 to VDD + 0.5 V • Output voltage VO Vss – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Applications CCD cameras Structure Silicon gate CMOS IC Recommended Operating Conditions • Supply voltage VDD 5.0 ± 0.25 Applicable CCD Image Sensors ICX026CKA, ICX027CKA ICX054AK, ICX055AK ICX056AK • Operating temperature Topr Block Diagram VSS –20 to +75 V °C VDD 8 21 28 40 15 16 17 18 19 20 24 25 56 62 60 SYNC GEN 59 HD INITIALIZE 57 63 MODE SET VD INITIALIZE 1/2 64 1 2 41 11 12 AA AA AA AA AA AA AA AAAA ADR . COUNT ADR . COUNT ADR . COUNT H – ROM V – ROM ROG – ROM LATCH LATCH GATE GATE LATCH 13 14 23 36 GATE CONTROLLER 61 HTSG 42 43 44 45 46 22 4 HIGH-SPEED PULSE GENERATION CIRCUIT DRIVER DECODER 5 MICROCOMPUTER 6 GATE COUNTER SHUT ROM DECODER 7 9 37 38 39 26 27 3 10 47 48 49 50 51 52 53 54 29 30 31 32 33 34 35 58 55 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E91817B4X-PK CXD1257AR Pin Description Pin No. Symbol I/O 1 OSCO O Inverter output for oscillation. 2 OSCI I Inverter input for oscillation. 3 EF I Not used. (With pull-up resistor) 4 ED0 I Shutter speed setting. Strobe input for serial mode. (With pull-up resister) 5 ED1 I Shutter speed setting. Clock input for serial mode. (With pull-up resister) 6 ED2 I Shutter speed setting. Data input for serial mode. (With pull-up resister) 7 SMD1 I Shutter mode setting. (With pull-up resister) 8 Vss 9 SMD2 I Shutter mode setting. (With pull-up resister) 10 XVCT O Not used. (Open) 11 D1 I Fix at Low in normal operation. (With pull-down resister) 12 D2 I Fix at Low in normal operation. (With pull-down resister) 13 D3 I Fix at Low in normal operation. (With pull-down resister) 14 D4 I Low: NTSC, High: PAL. (With pull-down resister) 15 A5 O Not used. (Open) 16 A4 O Not used. (Open) 17 A3 O Not used. (Open) 18 A0 O Not used. (Open) 19 A1 O Not used. (Open) 20 A2 O Not used. (Open) 21 Vss — GND 22 RG O Reset gate pulse output. 23 NC — 24 VDD — Power supply. 25 VDD — Power supply for H1 and H2. 26 H1 O Clock output for CCD horizontal register drive. 27 H2 O Clock output for CCD horizontal register drive. 28 Vss — GND for H1 and H2. 29 XSUB O CCD discharge pulse output. 30 XV2 O Clock output for CCD vertical register drive. 31 XV1 O Clock output for CCD vertical register drive. 32 XSG1 O CCD sensor charge readout pulse output. 33 XV3 O Clock output for CCD vertical register drive. 34 XSG2 O CCD sensor charge readout pulse output. 35 XV4 O Clock output for CCD vertical register drive. — Description GND –2– CXD1257AR Pin No. Symbol 36 TEST2 I Test input. Set at Low in normal operation. 37 MCK O NTSC: 1820fH/3, PAL: 1816fH/3. Output. 38 XSHP O Precharge level sample-and-hold pulse. 39 XSHD O Data sample-and-hold pulse. 40 Vss — GND 41 XSP1 O Color separation sample-and-hold pulse. 42 XSP2 O Color separation sample-and-hold pulse. 43 XSH1 O Switching sample-and-hold pulse. 44 XSH2 O Switching sample-and-hold pulse. 45 XDL1 O Delay line clock output. 46 XDL2 O Delay line clock output. 47 BFG O Pulse output for chroma modulator in encoder. 48 CLP1 O Clamp pulse output. 49 CLP2 I/O Clamp pulse output. When GM is set at High, standby mode switching input. 50 CLP3 I/O Clamp pulse output. When GM is set at High, standby mode switching input. 51 CLP4 O Clamp pulse output. 52 PBLK O Blanking cleaning pulse output. 53 ID O Line identification output. 54 WEN O Write enable output for low-speed shutter operation. 55 GM I Low: Analog signal processing, High: Digital signal processing. (With pull-down resister) 56 VDD — Power supply. 57 CL O NTSC: 910fH, PAL: 908fH. Clock output. 58 PS I Switching for electronic shutter speed input method. (With pull-up resister) Low: Serial input, High: Parallel input. 59 HD I Horizontal synchronizing signal input. 60 VD I Vertical synchronizing signal input. (During Low, 9H for NTSC and 7.5H for PAL) 61 HTSG I Control input for XSG1 and XSG2. (With pull-up resistor) Low: XSG1, XSG2 halted, High: XSG1, XSG2 generated. 62 TEST I Test input. Set at Low in normal operation. (With pull-down resister) 63 XCK O NTSC: 1820fH, PAL: 1816fH. Clock output. 64 CK I NTSC: 1820fH, PAL: 1816fH. Clock input. I/O Description –3– CXD1257AR Electrical Characteristics DC Characteristics Item Supply voltage (VDD = 5V ± 0.25V, Topr = –20 to +75°C) Symbol Conditions VDD VIH1 Input voltage 1 (Input pins other than those below) VIL1 Min. Typ. Max. Unit 4.75 5.0 5.25 V 0.3VDD Input voltage 2 (Pins 59 and 60) VIH2 Output voltage 1 (Output pins other than those below) VOH1 IOH = –2mA VOL1 IOL = 4mA Output voltage 2 (Pins 22, 37, 38, 39, 57, and 63) VOH2 IOH = –4mA VOL2 IOL = 8mA Output voltage 3 (Pins 26 and 27) VOH3 IOH = –8mA VOL3 IOL = 8mA Output voltage 4 (Pin 1) VOH4 IOH = –1mA VOL4 IOL = 1mA Feedback resister RFB VIN = Vss or VDD 500k Pull-up resister RPU VIL = 0V Pull-down resister RPD VIH = VDD VIL2 0.8 VDD – 0.5 Min. VDD – 0.5 VDD – 0.5 V V 0.4 VDD/2 V V VDD/2 V 2M 5M Ω 40k 100k 250k Ω 40k 100k 250k Ω Max. Unit Input pin capacitance CIN 9 pF Output pin capacitance COUT 11 pF I/O pin capacitance CI/O 11 pF –4– V V 0.4 Typ. V V 0.4 (VDD = VI = 0V, fM = 1MHz) Symbol V V 2.2 I/O Pin Capacitances Item V 0.7VDD CXD1257AR Description of Operation 1. Mode Control Symbol Pin No. L H GM 55 Analog signal processing Digital signal processing PS 58 Serial shutter speed setting Parallel shutter speed setting EF 3 HTSG 61 D1 11 Fix at Low in normal operation D2 12 Fix at Low in normal operation D3 13 Fix at Low in normal operation D4 14 Fix at High in normal operation XSG1, 2 OFF XSG1, 2 ON NTSC PAL –5– CXD1257AR 2. Changes in I/O Signals in Each Mode Symbol Pin No. Analog color Digital color 1 Digital color 2 GM 55 L H H D2 12 L L L TEST2 36 L L H XSP1 41 Color separation sample-and-hold pulse output Halted at High Color separation sample-and-hold pulse output XSP2 42 Color separation sample-and-hold pulse output Halted at High Color separation sample-and-hold pulse output XSH1 43 Switching sampleand-hold pulse output Halted at Low Switching sampleand-hold pulse output XSH2 44 Switching sampleand-hold pulse output Halted at Low Switching sampleand-hold pulse output XDL1 45 Delay line clock Halted at High Halted at High XDL2 46 Delay line clock Halted at Low Halted at Low BFG 47 Burst flag gate pulse output Burst flag gate pulse output (normally not used) Burst flag gate pulse output (normally not used) Standby control input Low: Standby High: Normal operation Standby control∗ Low: All circuits halted for standby mode High: Only CL output for standby mode Standby control input Low: Standby High: Normal operation Standby control∗ Low: All circuits halted for standby mode High: Only CL output for standby mode Line identification output Line identification output CLP2 49 Clamp pulse output CLP3 50 Clamp pulse output ID 53 Line identification output ∗ When CLP2 = High, normal operation occurs regardless of whether CLP3 is high or low. (Mode combinations other than those shown above cannot be used.) Note) In the standby mode described above, XCK, XSG1, XSG2, XV1, XV2, XV3, XV4, XSUB, H1, H2, RG, XSHD, XSHP, XSP1, XSP2, XSH1, XSH2, XDL1, and XDL2 pins are halted at Low. MCK, CLP1, CLP4, PBLK, ID, XVCT, WEN, BFG, A0, A1, A2, A3, A4, and A5 pins are halted at the state just before standby. –6– CXD1257AR 3. Electronic Shutter The operation of the electronic shutter is controlled by the output of XSUB pulse during particular intervals. <Shutter Modes> SMD1 SMD2 L L L H H L H H Flickerless: Eliminates fluorescent frequency-induced flicker. High-speed shutter: Shutter speed faster than 1/60 (NTSC), 1/50 (PAL) Low-speed shutter: Shutter speed slower than 1/60 (NTSC), 1/50 (PAL) No shutter operation. <Shutter Mode and Speed Setting Method> PS = High: Parallel input; set by ED0 to ED2, SMD1, and SMD2. PS = Low: Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin. 3-1. Parallel input (PS = H) Shutter Speed Compatibility Chart Mode OFF Flickerless High-speed shutter Low-speed shutter NTSC/PAL SMD1 SMD2 ED0 ED1 ED2 X H H X X X Shutter off NTSC L L X X X 1/100 (s) PAL L L X X X 1/120 (s) NTSC L H H H H 1/60 (s) PAL L H H H H 1/50 (s) X L H L H H 1/125 (s) X L H H L H 1/250 (s) X L H L L H 1/500 (s) X L H H H L 1/1000 (s) X L H L H L 1/2000 (s) X L H H L L 1/4000 (s) X L H L L L 1/10000 (s) X H L H H H 2FLD X H L L H H 4FLD X H L H L H 6FLD X H L L L H 8FLD X H L H H L 10FLD X H L L H L 12FLD X H L H L L 14FLD X H L L L L 16FLD –7– Shutter speed CXD1257AR 3-2. serial input (PS = L) For serial input (PS = L), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2 (Pin 9) pins as SMD1 and SMD2 (shutter mode control). In this case, control by SMD1 and SMD2 pins is invalid. ED1 (CLK) ED2 (DATA) D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) ED2 data is latched to the register at the rise of ED1, and transferred to the within during the Low period of ED0. –8– CXD1257AR AC Characteristics ED2 ts2 th2 tW1 tW1 ED1 ts1 ts0 ED0 tw0 Symbol tS2 th2 tS1 tW0 tS0 tW1 Min. Max. ED2 set-up time, activated by the rising edge of ED1 20ns — ED2 hold time, activated by the rising edge of ED1 20ns — ED1 rising set-up time, activated by the rising edge of ED0 20ns — ED0 pulse width 20ns 50µs ED0 rising set-up time, activated by the rising edge of ED1 20ns — ED1 pulse width (serial input) 20ns — 3-4. Low-speed shutter timing chart (ED2 : ED1 : ED0 = H : H : H) O E O E O E O E O E O E O E VD XSG1, 2 WEN (ED2 : ED1 : ED0 = H : H : L) XSG1, 2 WEN –9– CXD1257AR 3-5. Shutter speed calculation formula High-speed shutter • NTSC T = [26210 – (1FF16 – L16)] × 63.56 + 32.37µs • PAL T = [31210 – (1FF16 – L16)] × 64 + 32.14µs (L16 = Load value) NTSC Load value Shutter speed PAL Calculated value Load value Shutter speed Calculated value 0FA16 1/10000 1/10424 0C816 1/10000 1/10401 0FC16 1/4000 1/4483 0CA16 1/4000 1/4461 10016 1/2000 1/2095 0CE16 1/2000 1/2083 10816 1/1000 1/1014 0D616 1/1000 1/1008 11816 1/500 1/499 0E616 1/500 1/496 13716 1/250 1/252 10516 1/250 1/250 17616 1/125 1/125 14316 1/125 1/125 19616 1/100 1/100 14916 1/120 1/120 Low-speed shutter Shutter speed calculation formula N = 2 × (1FF16 – L16) FLD However, "1FF" cannot be used as the load value. Load value Shutter speed (FLD) 1FE16 2 1FD16 4 : : : : 10116 508 10016 510 – 10 – – 11 – BFG CLP4 CLP3 CLP2 CLP1 PBLK CCD XV4 XV3 XV2 XV1 ID XSG2 XSG1 HD BLK/VD FLD Timing Chart (1) NTSC vertical direction 491 492 2 4 6 1 3 5 7 491 490 492 2 4 6 8 1 3 5 7 CXD1257AR – 12 – BFG CLP4 CLP3 CLP2 CLP1 PBLK CCD XV4 XV3 XV2 XV1 ID XSG2 XSG1 HD BLK/VD FLD 581 582 Timing Chart (2) PAL vertical direction 2 4 6 8 1 3 5 7 9 582 2 4 6 8 10 1 3 5 7 9 CXD1257AR – 13 – 2 8 18 18 21 24 Black painted portions of H1 clock indicate the optical black. BFG ID PBLK CLP4 CLP3 CLP2 CLP1 XSUB XV4 XV3 XV2 XV1 XDL2 XDL1 XSH2 XSH1 XSP2 XSP1 XSHD XSHP RG H1 MCK CL BLK/HD Timing Chart (3) NTSC horizontal direction 27 29 33 39 45 45 50 51 56 57 67 75 89 94 64 94 94 BLK HD 63 102 (63) CXD1257AR – 14 – 2 8 18 23 Black painted portions of H1 clock indicate the optical black. BFG ID PBLK CLP4 CLP3 CLP2 CLP1 XSUB XV4 XV3 XV2 XV1 XDL2 XDL1 XSH2 XSH1 XSP2 XSP1 XSHD XSHP RG H1 MCK CL BLK/HD Timing Chart (4) PAL horizontal direction 24 26 32 34 38 44 55 50 61 56 68 69 72 80 94 103 103 103 BLK HD 62 112 (64) CXD1257AR EVEN FIELD ODD – 15 – XSG2 XSG1 XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 HD H1 Timing Chart of Readout (NTSC/PAL) 1 2 3 4 289 290 [285] [286] 10 3 24 14 24 19 1clock:104.76ns (NTSC) 105.73ns (PAL) Unit: Number of clocks (Common to NTSC and PAL) Numerals in brackets are for PAL. CXD1257AR – 16 – XSH2 XSH1 XDL2 XDL1 XSP2 XSP1 XSHD XSHP RG H2 H1 CL MCK XCK HD 1 2 3 93 Resetting phase Timing Specifications of Resetting Phase and H1/2 Start — High-speed Waveform (NTSC) 112 H1/2 start CXD1257AR – 17 – XSH2 XSH1 XDL2 XDL1 XSP2 XSP1 XSHD XSHP RG H2 H1 CL MCK XCK HD 1 2 3 100 Resetting phase Timing Specifications of Resetting Phase and H1/2 Start — High-speed Waveform (PAL) AA AA AA AA AA 118 H1/2 start CXD1257AR CXD1257AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 ± 0.08 + 0.08 0.18 – 0.03 16 + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 18 –