SONY CXD2508AR

CXD2508AQ/AR
CD Digital Signal Processor
For the availability of this product, please contact the sales office.
Description
The CXD2508AQ/AR is a digital signal processor
for CD players and is equipped with built-in digital
filters, no-sound data detection circuit, and 1-bit
DAC.
Features
DSP block
• Digital PLL
• EFM frame sync protection
• SEC strategy-based error correction
• Subcode demodulation, CRC checking
• Digital spindle servo
• Servo auto sequencer
• Asymmetry compensation circuit
• Digital audio interface output
• 16K RAM
• Double-speed playback capability
• New microcomputer interface circuit
Digital filter, DAC block
• Double-speed playback capability
• Digital de-emphasis
• Digital attenuation
• No-sound data detection circuit
• 4 Fs oversampling filter
• Secondary ∆∑ noise shaper
• PWM-system pulse conversion output
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AR
80 pin LQFP (Plastic)
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
–0.3 to 7.0
V
• Supply voltage VDD
• Input voltage
VI
–0.3 to 7.0
V
• Input voltage
VIN Vss–0.3V (min.) VDD+0.3 (max.) V
• Output voltage VO
–0.3 to 7.0
V
• Storage temperature
Tstg
–40 to 125
°C
• Supply voltage variation
VSS–AVSS –0.3V (min.) +0.3V (max.)
VDD–AVDD –0.3V (min.) +0.3V (max.)
Recommended Operating Conditions
• Supply voltage VDD Note) 4.5 to 5.5V
(double-speed playback)
3.5 to 5.5V
(normal-speed playback)
3.4 to 5.5V
(low power consumption
or special playback mode)
• Operating temperature
Topr
–20 (min.) 75 (max.)
°C
Note) VDD (min.) is varied by the playback speed and built-in
VCO in the CXD2508AQ/AR. 4.5V is the value using the
VCO which generates the slower frequency in doublespeed playback. The table below shows the VDD (min.)
for each condition.
VDD (min.) [V]
Playback
speed
VCO
VCO
DAC block
high-speed normal-speed
×2
3.40
4.50
3.40
×1
3.40
3.50
3.40
× 1∗
3.40
3.40
3.40
∗ When the internal operation of the LSI is set to doublespeed mode and the crystal oscillation frequency is
halved, normal-speed playback results.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94602A54-ST
CXD2508AQ/AR
WDCK
LRCK
LRCKI
PCMD
PCMDI
BCK
BCKI
GTOP
XUGF
XPCK
GFS
RFCK
Vss
C2PO
XROF
MNT3
MNT1
MNT0
FSTT
C4M
DOUT
EMPH
EMPHI
WFCK
Pin Configuration
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
ZEROL
65
40
ASYE
ZEROR
66
39
ASYO
DTS1
67
38
ASYI
68
37
BIAS
VDD
NLPWM
69
36
RF
LPWM
70
35
AVDD1
AVDD2
71
34
CLTV
AVDD3
72
33
AVss1
XTAI
73
CXD2508AQ
32
VDD
PCO
XTAO
74
31
AVss3
75
30
FILI
XTSL
XLON
PCMD
LRCKI
MON
SPOC
PCMDI
FOK
SPOB
Vss
BCK
C2PO
BCKI
CLOK
XROF
SPOA
XLAT
GTOP
DATA
MNT3
CLKO
XRST
XUGF
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
XLTO
8
DATO
7
XPCK
6
CNIN
5
GFS
4
SEIN
3
RFCK
2
Vss
1
MNT1
MDP
SENS
80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
EMPHI
61
40
LRCK
WFCK
62
39
WDCK
ZEROL
63
38
ASYE
ZEROR
64
37
ASYO
DTS1
65
36
ASYI
VDD
66
35
BIAS
NLPWM
67
34
RF
LPWM
68
33
AVdd1
AVDD2
69
32
CLTV
AVDD3
70
XTAI
71
XTAO
31
AVss1
30
Vdd
72
29
PCO
AVss3
73
28
FILI
AVss2
74
27
FILO
NRPWM
75
26
TEST
RPWM
76
25
LOCK
DTS2
77
24
MDS
DTS3
78
23
MDP
SCOR
79
22
MON
SBSO
80
21
FOK
SENS
XRST
DATA
XLAT
CLOK
XLON
MUTE
XTSL
SQCK
–2–
SPOC
9 10 11 12 13 14 15 16 17 18 19 20
SPOB
8
SPOA
7
CLKO
6
XLTO
5
DATO
4
CNIN
3
SEIN
2
Vss
1
SQSO
CXD2508AR
EXCK
DTS3
MNT0
MDS
25
MUTE
26
FSTT
79
SQCK
LOCK
DTS2
C4M
27
DOUT
78
SQSO
TEST
RPWM
EMPH
FILO
EXCK
29
28
SBSO
76
77
SCOR
AVss2
NRPWM
CXD2508AQ/AR
ZEROL
ZEROR
73 74
66
65
XTAI
XTAO
Block Diagram
69 NLPWM
EMPHI 63
LRCKI 43
70 LPWM
Digital Filter
+
1bit DAC
PCMDI 45
BCKI 47
78 RPWM
77 NRPWM
MUTE 6
BCK 46
PCMD 44
LRCK 42
61 DOUT
WDCK 41
digital
OUT
D/A
Interface
C2PO 54
55 XROF
27 LOCK
RFCK 52
digital
CLV
26 MDS
25 MDP
24 MON
MNT0 58
error
corrector
MNT1 57
16K RAM
MNT3 56
WFCK 64
CPU
interface
EMPH 62
SQCK
4
SQSO
3
EXCK
2
SBSO
1
SCOR
22 XLON
19 SPOA to C
SUB code
Processor
EFM
demodulator
GFS 51
5
11 CLOK
10 XLAT
XUGF 49
GTOP 48
9
DATA
7
SENS
17 CLKO
clock
generator
16 XLTO
31 34
23
13
14
FOK
SEIN
CNIN
PCO
FILI
FILO
50 29 30
CLTV
15 DATO
XPCK
BIAS
RF
38 39 40 37
ASYE
36
ASYI
60
ASYO
59
C4M
asymmetry
corrector
FSTT
XTSL 18
Servo auto
sequencer
digital
PLL
Note) The pin numbers are for QFP. Refer to the Pin Description for those of LQFP.
–3–
CXD2508AQ/AR
Pin Description
Pin No.
Symbol
Description
I/O
R
Q
79
1
SCOR
O
Outputs a high signal when either subcode sync S0 or S1 is detected.
80
2
SBSO
O
Sub P to W serial output.
1
3
EXCK
I
SBSO readout clock input.
2
4
SQSO
O
Sub Q 80-bit serial output.
3
5
SQCK
I
SQSO readout clock input.
4
6
MUTE
I
High: mute; low: release
5
7
SENS
O
SENS output to CPU.
6
8
XRST
I
System reset. Reset when low.
7
9
DATA
I
Serial data input from CPU.
8
10
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
9
11
CLOK
I
Serial data transfer clock input from CPU.
10
12
VSS
11
13
SEIN
I
Sense input from SSP.
12
14
CNIN
I
Track jump count signal input.
13
15
DATO
O
Serial data output to SSP.
14
16
XLTO
O
Serial data latch output to SSP. Latched at the falling edge.
15
17
CLKO
O
Serial data transfer clock output to SSP.
16
18
SPOA
I
Microcomputer extended interface (input A).
17
19
SPOB
I
Microcomputer extended interface (input B).
18
20
SPOC
I
Microcomputer extended interface (input C).
19
21
XTSL
I
Crystal selection input. Low for 16.9344MHz; high for 33.8688MHz
20
22
XLON
O
Microcomputer extended interface (output).
21
23
FOK
I
Focus OK input. Used for SENS output and the servo auto sequencer.
22
24
MON
O
Spindle motor on/off control output.
23
25
MDP
O
Spindle motor servo control.
24
26
MDS
O
Spindle motor servo control.
25
27
LOCK
O
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
26
28
TEST
I
TEST pin. Normally GND.
27
29
FILO
O
Master PLL (slave = digital PLL) filter output.
28
30
FILI
I
Master PLL filter input.
29
31
PCO
O
Master PLL charge pump output.
30
32
VDD
Digital power supply for DSP.
31
33
AVSS1
Analog GND for DSP.
32
34
CLTV
GND.
I
Master PLL VCO control voltage input.
–4–
CXD2508AQ/AR
Pin No.
Symbol
Description
I/O
R
Q
33
35
AVDD1
34
36
RF
I
EFM signal input.
35
37
BIAS
I
Constant current input of asymmetry compensation circuit.
36
38
ASYI
I
Comparator voltage input of asymmetry compensation circuit.
37
39
ASYO
O
EFM full-swing output (low = Vss, high = VDD).
38
40
ASYE
I
Low: asymmetry compensation off; high: asymmetry compensation on.
39
41
WDCK
O
D/A interface for 48-bit slot. Word clock (2Fs).
40
42
LRCK
O
D/A interface for 48-bit slot. LR clock (Fs).
41
43
LRCKI
I
LR clock input for DAC. (48-bit slot)
42
44
PCMD
O
D/A interface. Serial data (two's complement, MSB first).
43
45
PCMDI
I
Audio data input for DAC. (48-bit slot)
44
46
BCK
O
D/A interface. Bit clock.
45
47
BCKI
I
Bit clock input for DAC. (48-bit slot)
46
48
GTOP
O
GTOP output.
47
49
XUGF
O
XUGF output.
48
50
XPCK
O
XPLCK output.
49
51
GFS
O
GFS output.
50
52
RFCK
O
RFCK output.
51
53
VSS
52
54
C2PO
O
C2PO output.
53
55
XROF
O
XRAOF output.
54
56
MNT3
O
MNT3 output.
55
57
MNT1
O
MNT1 output.
56
58
MNT0
O
MNT0 output.
57
59
FSTT
O
2/3 frequency-divider output for Pins 73 and 74.
58
60
C4M
O
4.2336MHz output.
59
61
DOUT
O
Digital Out output.
60
62
EMPH
O
Outputs high signal when the playback disc has emphasis, low signal when no
emphasis.
61
63
EMPHI
I
DAC de-emphasis on/off. High: on; low: off.
62
64
WFCK
O
WFCK (write frame clock) output.
63
65
ZEROL
O
No-sound data detection output; high when no sound data is detected.
(Left channel)
64
66
ZEROR
O
No-sound data detection output; high when no sound data is detected.
(Right channel)
65
67
DTS1
I
Test pin 1 for DAC; normally low.
66
68
VDD
Analog power supply for DSP.
GND.
Digital power supply for DAC.
–5–
CXD2508AQ/AR
Pin No.
Symbol
I/O
69
NLPWM
O
Left channel PWM output. (Reverse phase)
68
70
LPWM
O
Left channel PWM output. (Forward phase)
69
71
AVDD2
Power supply for PWM driver.
70
72
AVDD3
Power supply for crystal.
71
73
XTAI
I
33.8688MHz crystal oscillation circuit input.
72
74
XTAO
O
33.8688MHz crystal oscillation circuit output.
73
75
AVSS3
GND for crystal.
74
76
AVSS2
GND for PWM driver.
75
77
NRPWM
O
Right channel PWM output. (Reverse phase)
76
78
RPWM
O
Right channel PWM output. (Forward phase)
77
79
DTS2
I
DAC test pin 2; normally low.
78
80
DTS3
I
DAC test pin 3; normally low.
R
Q
67
Description
Note)
• PCMD is an MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the negative pulse for the frame sync derived from the EFM signal. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the
EFM signal transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µ.
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
–6–
CXD2508AQ/AR
Electrical Characteristics
DC Characteristics
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) NOTE)
Output voltage (4) Output voltage (3) Output voltage (2) Output voltage (1) Input voltage (3) Input voltage (2) Input voltage (1)
Item
High level input voltage
Conditions
VIL (1)
High level input voltage
VIH (2)
Typ.
Max.
0.7VDD
VIH (1)
Low level input voltage
Min.
Unit
V
0.3VDD
0.8VDD
V
0.2VDD
V
VSS
VDD
V
VDD–0.8
VDD
V
0
0.4
V
VDD–0.8
VDD
V
Low level input voltage
VIL (2)
Input voltage
VIN (3)
Analog input
High level output
voltage
VOH (1)
IOH = –4mA
Low level output
voltage
VOL (1)
IOL = 4mA
High level output
voltage
VOH (2)
IOH = –2mA
Low level output
voltage
VOL (2)
IOL = 4mA
High level output
voltage
VOH (3)
IOH = –0.28mA
Low level output
voltage
VOL (3)
IOL = 0.36mA
0
0.4
V
High level output
voltage
VOH (4)
IOH = –10mA
VDD–0.4
VDD
V
Low level output
voltage
VOL (4)
0
0.4
V
VDD–0.5
VDD
V
0
∗1
V
Schmitt input
IOL = 10mA
Applicable
pins
0.4
V
∗2
∗3
∗4
∗5
∗6
∗7
Input leak current
ILI
VI = 0 to 5.25V
±5
µA
∗1, ∗2, ∗3
Tri-state pin output leak
current
ILO
VO = 0 to 5.25V
±5
µA
∗8
Applicable pins
∗1 XTSL, DATA, XLAT, PCMDI, EMPHI, DTS1, DTS2, DTS3, SPOA, SPOB, SPOC
∗2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, ASYE, LRCKI, BCKI
∗3 CLTV, FILI, RF, BIAS, ASYI
∗4 MDP, PCO
∗5 ASYO, DOUT, FSTT, C4M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO,
SENS, MDS, LRCK, WFCK, PCMD, BCK, GTOP, XUGF, XPCK, GFS, RFCK, XROF, MNT0, MNT1,
MNT3, ZEROL, ZEROR
∗6 FILO
∗7 LPWM, NLPWM, RPWM, NRPWM
∗8 SENS, MDS, MDP
Note) "AVDD" refers to AVDD1, AVDD2, and AVDD3. In addition, "AVss" refers to AVss1, AVss2, and AVss3.
–7–
CXD2508AQ/AR
AC Characteristics
1) XTAI pin
(1) When using self-oscillation (Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Symbol
Oscillation frequency
Min.
fMAX
Typ.
Max.
Unit
34
MHz
15
(2) When inputting pulses to XTAI
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Symbol
Min.
Typ.
Max.
Unit
High level
pulse width
tWHX
13
500
ns
Low level
pulse width
tWLX
13
500
ns
Pulse cycle
tCK
26
1,000
ns
Input high level
VIHX
VDD – 1.0
Input low level
VILX
0.8
V
Rise time,
fall time
tR, tF
10
ns
V
tCX
tWLX
tWHX
VIHX
VIHX × 0.9
VDD/2
XTAI
VIHX × 0.1
VILX
tr
tr
(3) When inputting sine waves to XTAI via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Input amplitude
Symbol
Min.
V1
2.0
Typ.
Max.
Unit
VDD + 0.3 Vp-p
–8–
CXD2508AQ/AR
2) CLOK, DATA, XLAT, CNIN, SQCK EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Clock frequency
fCK
Clock pulse width
Latch pulse width
tWCK
tSU
tH
tD
tWL
EXCK SQCK frequency
fT
Setup time
Hold time
Delay time
Min.
Typ.
Max.
Unit
0.65
MHz
750
ns
300
ns
300
ns
300
ns
750
ns
0.65∗
MHz
750∗
EXCK SQCK pulse width fWT
ns
1/fCX
tWCK
tWCK
CLK
DATA
XLT
tSU
tH
tD
tWL
EXCK
CNIN
SQCK
tWT
tWT
1/fr
SUBQ
SQCK
tSU
tH
∗ In pseudo double-speed playback mode, when SL0 = SL1 = 1, the maximum operating frequency for SQCK
is 300kHz and the minimum pulse width is 1.5µs.
3) BCKI, LRCKI, and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol Conditions
BCK pulse width
tW
tSU
tH
tSU
DATAL, R setup time
DATAL, R hold time
LRCK setup time
Min.
Typ.
Max.
Unit
94
118
141
nsec
18
nsec
18
nsec
18
nsec
tW(BCKI) tW(BCKI)
BCKI
VDD/2
VDD/2
tH
tSU
(PCMDI) (PCMDI)
PCMDI
tsu
(LRCKI)
LRCKI
–9–
CXD2508AQ/AR
1-bit DAC Block Analog Characteristics
Item
Symbol
Total harmonic
distortion
THD
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)
1kHz,
0dB data
Typ.
Min.
Playback mode
Conditions
Max.
Normal speed
0.015
Pseudo double-speed playback
0.025
1kHz,
Normal speed
87
0dB data
83
(using filter A) Pseudo double-speed playback
For both items, Fs=44.1kHz
The circuits for measuring the total harmonic distortion and S/N ratio are shown below.
S/N ratio
4.7k
4.7k
RPWM
SHIBASOKU (AM51A)
2700p
820p
470p
22µ
470p
820p
NRPWM
4.7k
100
Audio
Analyzer
4.7k
560p
11k
330k
4.7k
4.7k
Analog LPF Circuit
768Fs/384Fs (Normal speed/Pseudo double-speed playback)
SHIBASOKU (AM51A)
RPWM
EFM
Signal
Generater
NRPWM
RF
CXD2508AQ/AR
NLPWM
Analog
Circuit
Rch
A
Lch
B
LPWM
Block Diagram for Measuring Analog Characteristics
– 10 –
%
dB
S/N
11k
Unit
Audio
Analyzer
CXD2508AQ/AR
Description of Functions
1. CPU Interface and Instructions
• CPU interface
This interface uses DATA, CLOK, and XLAT to set the modes. The interface timing chart is shown below.
750ns or more
CLOK
DATA
D1
D2
Data
D3
D0
D1
D2
D3
750ns or more
Address
XLAT
Registers 4 to E
Valid
300ns max
• Information on each address and the data is provided in Table 1-1.
• The internal registers are initialized by a reset when XRST = 0; the initialization data is shown in Table 1-2.
Note) When XLAT is low, EXCK and SQCK must be set high.
– 11 –
Servo coefficient setting
CLV CTRL
CLV mode
TEST mode
C
D
E
F
0
1
1
1
1
1
1
1
1
0
1
Audio CTRL
A
1
0
1
Function specification
9
Serial bus CTRL
0
1
MODE specification
8
B
1
0
Auto sequence (N)
track jump count setting
7
1
1
0
0
KICK (D)
Brake (B)
Blind (A, E), Overflow (C)
6
5
1
0
4
Auto sequence
D2
– 12 –
1
1
0
0
1
1
0
0
1
1
0
0
D1
Address
D3
Command
Register
name
Command Table
1
0
1
0
1
0
1
0
1
0
1
0
D0
AS2
D2
AS1
D1
AS0
D0
4096
Mute
SL 0 CPUSR
0
0
ATT
DOUT DOUT WSEL
MUTE ON/OFF
DSPB
0
0
ON/OFF
8192
CM3
CM0
—
—
—
D3
—
—
—
—
—
—
0
—
2048
Table 1-1
CM1
Don't Use
CM2
Gain Gain Gain Gain
MDP1 MDP0 MDS1 MDS0
CLVS
DCLV
TP
Gain
PWMmod TB
SL 1
0
0
CDROM
32768 16384
11.6ms 5.8ms 2.9ms 1.45ms
0.36ms 0.18ms 0.09ms 0.05ms
0.18ms 0.09ms 0.05ms 0.02ms
AS3
D3
Data 1
—
—
—
—
—
—
0
—
1024
—
—
—
D2
—
—
—
—
—
DADS
0
—
512
—
—
—
D1
Data 2
—
—
—
—
—
—
VCO
SEL
FSTT
SEL
256
—
—
—
D0
AD6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
64
—
—
128
—
—
—
—
—
D2
D3
—
—
—
—
—
AD5
—
—
32
—
—
—
D1
Data 3
—
—
—
—
—
AD4
—
—
16
—
—
—
D0
—
—
—
—
—
AD3
—
—
8
—
—
—
D3
—
—
—
—
—
AD2
—
—
4
—
—
—
D2
—
—
—
—
—
AD1
—
—
2
—
—
—
D1
Data 4
—
—
—
—
—
AD0
—
—
1
—
—
—
D0
CXD2508AQ/AR
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
Auto sequence (N)
track jump count setting
MODE specification
Function specification
Audio CTRL
Serial bus CTRL
Servo coefficient setting
CLV CTRL
CLV mode
TEST mode
7
8
9
A
B
C
D
E
F
1
1
1
0
0
D2
D3
– 13 –
1
1
0
0
1
1
0
0
1
1
0
0
D1
Address
KICK (D)
Brake (B)
Blind (A, E), Overflow (C)
Auto sequence
Command
6
5
4
Register
name
Reset Initialization
1
0
1
0
1
0
1
0
1
0
1
0
D0
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
1
1
1
0
1
0
1
0
0
D1
Don't Use
0
0
1
0
0
0
0
0
1
1
0
D2
Data 1
Table 1-2
0
0
0
0
1
0
0
0
1
1
0
D0
—
—
—
—
—
—
0
—
0
—
—
—
D3
—
—
—
—
—
—
0
—
0
—
—
—
D2
—
—
—
—
—
0
0
—
0
—
—
—
D1
Data 2
—
—
—
—
—
—
0
0
1
—
—
—
D0
0
—
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
D2
D3
—
—
—
—
—
1
—
—
0
—
—
—
D1
Data 3
—
—
—
—
—
1
—
—
0
—
—
—
D0
—
—
—
—
—
1
—
—
0
—
—
—
D3
—
—
—
—
—
1
—
—
0
—
—
—
D2
—
—
—
—
—
1
—
—
0
—
—
—
D1
Data 4
—
—
—
—
—
1
—
—
0
—
—
—
D0
CXD2508AQ/AR
CXD2508AQ/AR
1-1. The meaning of the data for each address is explained below.
$4X commands
Command
AS3
AS2
AS1
AS0
CANCEL
0
0
0
0
FOCUS-ON
0
1
1
1
1 TRACK JUMP
1
0
0
RXF
10 TRACK JUMP
1
0
1
RXF
2N TRACK JUMP
1
1
0
RXF
N TRACK MOVE
1
1
1
RXF
RXF = 0
RXF = 0
FORWARD
REVERSE
• When the FOCUS-ON command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the TRACK JUMP/MOVE commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is
interrupted.
$5X commands
Auto sequence timer setting
Setting timers: A, E, C, B
Command
D3
D2
D1
D0
Blind (A, E), Over flow (C)
0.18ms
0.09ms
0.05ms
0.02ms
Brake (B)
0.36ms
0.18ms
0.09ms
0.05ms
Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)
A = E = C = 0.11ms
B = 0.23ms
$6X commands
Auto sequence timer setting
Setting timer: D
Command
KICK (D)
D3
D2
D1
D0
11.6ms
5.8ms
2.9ms
1.45ms
Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)
D = 10.15ms
$7X commands
Auto sequence TRACK JUMP/MOVE count setting (N)
Command
Data 1
Data 2
Data 3
Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Auto sequence track jump 15 14 13 12 11 10
2
2
2
2
2
2
number setting
29
28
27
26
25
24
23
22
21
20
This command is used to set N when a 2N TRACK JUMP and an N TRACK MOVE are executed for auto
sequence.
• The maximum track count is 65,535, but note that with 2N track jumps the maximum track jump count is
determined by the mechanical limitations of the optical system.
• The number of track jump is counted according to the signals input from CNIN pin.
– 14 –
CXD2508AQ/AR
$8X commands
Data 1
Command
MODE
specification
Data 2
D3
D2
D1
D0
D3
D2
D1
D0
CDROM
DOUT
MUTE
DOUT
ON-OFF
WSEL
0
0
0
VCO
SEL
Command bit
C2PO timing
CDROM = 1
1-3
CDROM mode; average value interpolation and
pre-value hold are not performed.
CDROM = 0
1-3
Audio mode; average value interpolation and pre-value
hold are performed.
Processing
Command bit
Processing
DOUT MUTE = 1
Digital Out output is muted. (DA output is not muted.)
DOUT MUTE = 0
When no other mute conditions are set, Digital Out output is not muted.
Command bit
Processing
DOUT ON-OFF = 1 Digital Out is output from the DOUT pin.
DOUT ON-OFF = 0 Digital Out is not output from the DOUT pin.
Command bit
Sync protection window width
Application
WSEL = 1
±26 channel clock∗
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
∗ In normal-speed playback, channel clock = 4.3218MHz.
Command bit
Processing
Application
VCOSEL = 1
VCO for double-speed
playback is selected.
Double-speed playback or low voltage
operation is possible.
VCOSEL = 0
VCO for normal-speed
playback is selected.
The selection is made for the normal
speed playback.
$9X commands
Command
Function
specifications
Data 1
Data 2
D3
D2
D1
D0
D3
D2
D1
D0
0
DSPB
ON-OFF
0
0
0
0
0
FSTT
SEL
Command bit
Processing
DSPB = 0
Normal-speed playback
DSPB = 1
Double-speed playback
Command bit
FSTTSEL = 0
The clock with two-thirds frequency of crystal is output to FSTT pin.
FSTTSEL = 1
The clock with the sixth frequency of crystal is output to FSTT pin.
– 15 –
CXD2508AQ/AR
$AX commands
Command
Audio CTRL
Data 1
Data 2
D3
D2
D1
D0
D3
D2
D1
D0
0
0
Mute
ATT
—
—
DADS
—
Command bit
Command bit
Meaning
Meaning
Mute = 0
Mute off.
ATT = 0
Attenuation off.
Mute = 1
Mute on. 0 data is output
from DSP.
ATT = 1
–12dB
Command bit
Processing
DADS = 0
Normal-speed playback for DAC block
DADS = 1
Double-speed playback for DAC block
In the case of using the crystal of 768Fs (Fs = 44.1kHz)
Digital Attenuation
The audio output level from DAC can be attenuated by setting AD6 to AC0 of register A. (with a built-in primary
noise shaper)
Command
Audio CTRL
Data 3
Data 4
D2
D1
D0
D3
D2
D1
D0
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Command bit
AD6 to AD0
Audio output
7F (H)
0dB
7E (H)
to
01 (H)
–0.13dB
to
–42.144dB
00 (H)
–∞
The attenuation data consists of seven bits (AD6 to AC0), and 127 settings are possible.
Audio output from 01 (H) to 7E (H) is determined according to the following formula:
Audio output = 20 log (
attenuation data
128
) dB
Ex.) When the attenuation data is 7A (H)
Audio output=20 log (
122
) dB = –0.417dB
128
Soft Mute
With soft mute function, when the attenuation data goes from 7F (H) (0dB) to 00 (H) (–∞) or vice versa, muting is
turned on/off with a muting time of 1024/Fs [s] = 23.2 [ms] (Fs = 44.1kHz).
– 16 –
CXD2508AQ/AR
Attenuation Operation
Assume attenuation data X1, X2, and X3, where X1 > X3 > X2, and audio output Y1, Y2, and Y3, where Y1 >
Y3 > Y2. First, assume X1 is transferred and then X2 is transferred. If X2 is transferred before Y1 is reached
(state "A" in the diagram), then the value continues approaching Y2. Next, if X3 is transferred before Y2 is
reached (either state "B" or "C" in the diagram), the value begins approaching Y3 from the current value at that
point.
0dB
7F (H)
A
Y1
B
Y3
C
Y2
–∞
00(H)
23.2 [ms]
$BX commands
Command
Serial bus CTRL
D3
D2
D1
D0
SL1
SL0
CPUSR
0
This command switches the method of interfacing with the CPU. With the CDL500 series, the number of signal
lines between the CPU and the DSP can be reduced in comparison with the CDL40 series. Also, the error rate
can be measured with the CPU.
Command bits
Processing
SL1
SL0
0
0
Same interface mode as the CDL40 series.
0
1
SBSO is output from SQSO pin. In other words, subcodes P to W are
read out from SQSO. Input the readout clock to SQCK.
1
0
SENS is output from SQSO pin.
1
1
Each output signal is output from SQSO pin.
Input the readout clock to SQCK.
(See the Timing Chart 1-2.)
Command bits
Processing
CPUSR = 1
XLON pin is high.
CPUSR = 0
XLON pin is low.
– 17 –
CXD2508AQ/AR
$CX commands
Command
D3
D2
D1
D0
Servo coefficient setting
Gain
MDP1
Gain
MDP0
Gain
MDS1
Gain
MDS0
Gain
CLVS
CLV CTRL ($DX)
• CLVS mode gain setting: GCLVS
Gain
MDS1
Gain
MDS0
Gain
CLVS
GCLVS
0
0
0
–12dB
0
0
1
–6dB
0
1
0
–6dB
0
1
1
0dB
1
0
0
0dB
1
0
1
+6dB
• CLVP mode gain setting: GMDP, GMDS
Gain
MDP1
Gain
MDP0
GMDP
Gain
MDS1
Gain
MDS0
GMDS
0
0
–6dB
0
0
–6dB
0
1
0dB
0
1
0dB
1
0
+6dB
1
0
+6dB
– 18 –
CXD2508AQ/AR
$DX commands
Command
D3
D2
D1
D0
CLV CTRL
DCLV
PWM MD
TB
TP
CLVS
Gain
See the $CX command.
Explanation (See the Timing Chart 1-3.)
Command bit
DCLV PWM MD = 1
CLV PWM mode specified. Both MDS and MDP are used.
DCLV PWM MD = 0
CLV PWM mode specified. Ternary MDP values are output.
Explanation
Command bit
TB = 0
Bottom hold in CLVS mode at cycle of RFCK/32
TB = 1
Bottom hold in CLVS mode at cycle of RFCK/16
TP = 0
Peak hold in CLVS mode at cycle of RFCK/4
TP = 1
Peak hold in CLVS mode at cycle of RFCK/2
$EX commands
Command
CLV mode
D3
D2
D1
D0
CM3
CM2
CM1
CM10
CM3
CM2
CM1
CM0
Mode
Explanation
0
0
0
0
STOP
See the Timing Chart 1-4.
1
0
0
0
KICK
See the Timing Chart 1-5.
1
0
1
0
BRAKE
See the Timing Chart 1-6.
1
1
1
0
CLVS
1
1
1
1
CLVP
0
1
1
0
CLVA
STOP
KICK
BRAKE
CLVS
CLVP
CLVA
: Spindle motor stop mode
: Spindle motor forward rotation mode
: Spindle motor reverse rotation mode
: Rough servo mode. When RF-PLL circuit lock is disengaged, this mode is used to pull the disc
rotations within the RF-PLL capture range.
: PLL servo mode.
: Automatic CLVS/CLVP switching mode. This mode is normally used during playback.
– 19 –
– 20 –
C2P0
CDROM = 1
C2P0
CDROM = 0
WDCK
LRCK
Timing Chart 1-1
C2 Pointer for lower 8bits
Rch C2 Pointer
C2 Pointer for upper 8bits
Rch 16bit C1 Pointer
C2 Pointer for lower 8bits
Lch C2 Pointer
C2 Pointer for upper 8bits
Rch 16bit C2 Pointer
If C2 Pointer = 1,
data is NG
CXD2508AQ/AR
SQSO
SQCK
XLAT
Timing Chart 1-2
SPOA
– 21 –
0
1
1
No Error
Single error correction
Irretrievable error
0
1
1
1
1
0
0
C2F1 C2F2
0
C1 correction status
0
C1F1 C1F2
XRAOF
C1F1 C1F2 C2F1
Irretrievable error
Single error correction
No Error
C2 correction status
FOK LOCK RFCK
750ns or more
(1500ns or more in low power consumption mode)
SPOB SPOC XTSL WFCK SCOR GFS GTOP EMPH
Internal signal latch
Set SQCK and EXCK high during this interval.
$BC latch
C2F2
CXD2508AQ/AR
CXD2508AQ/AR
Timing Chart 1-3
DCLV PWM MD = 0
Z
MDS
n • 236 (ns) n = 0 to 31
Acceleration
MDP
Z
132kHz
7.6µs
Deceleration
DCLV PWM MD = 0
MDS
Acceleration
Deceleration
MDP
n • 236 (ns) n = 0 to 31
7.6µs
Timing Chart 1-4
DCLV PWM MD = 0
STOP
MDS
Z
MDP
Z
MON
L
DCLV PWM MD = 1
STOP
MDS
MDP
L
MON
L
– 22 –
CXD2508AQ/AR
Timing Chart 1-5
DCLV PWM MD = 0
KICK
Z
MDS
H
MDP
Z
7.6µs
H
MON
DCLV PWM MD = 1
KICK
MDS
MDP
H
H
L
MON
H
– 23 –
CXD2508AQ/AR
Timing Chart 1-6
DCLV PWM MD = 0
BRAKE
Z
MDS
H
MDP
Z
H
MON
DCLV PWM MD = 1
MDS
MDP
MON
H
– 24 –
CXD2508AQ/AR
1-2. Description of SENS Output
The following signals are output from SENS, depending on the microcomputer serial register value (latching
not required).
Microcomputer serial register SENS
value (latching not required) output
Meaning
$0X, 1X, 2X, 3X
SEIN
$4X
XBUSY Low while the auto sequencer is in operation, high when operation terminates.
$5X
FOK
Outputs the signal input to the FOK pin. Normally, FOK (from RF) is
input. High for "focus OK".
$6X
SEIN
SEIN, a signal input to this IC from the SSP, is output.
$AX
GFS
High when the played back frame sync is obtained with the correct
timing.
$EX
OV64
Low when the EFM signal, after passing through the sync detection filter,
is lengthened by 64 channel clock pulses or more.
$7X, 8X, 9X, BX, CX,
DX, FX
"L"
SENS pin is fixed low.
SEIN, a signal input to the this IC from the SSP, is output.
Note that the SENS output can be read from SQSO pin when SL1 = 1 and SL0 = 0. (See the $BX commands.)
2. Subcode Interface
This section explains the subcode interface.
There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from
SBSO by inputting EXCK to the CXD2508AQ/AR.
Sub Q can be read out after the CRC check of the 80 bits data in the subcode frame. This accomplished, after
checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data from SQSO pin.
2-1. P to W Subcode Read
Data can be read out by inputting EXCK immediately after WFCK falls. (See Fig. 2-1.)
Also, SBSO can be read out from SQSO pin when SL1 = 0 and SL0 = 1. (See the $BX commands.)
2-2. 80-bit Sub Q Read
Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are
loaded into the parallel/serial register.
When SQSO goes high 400µs or more later (monostable multivibrator time constant) after the subcode is
read out, the CPU determines that new data (which passed the CRC check) has been loaded.
• In the CXD2508AQ/AR, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte.
As a result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be read.
In the CXD2508AQ/AR, the SQCK input is detected, and when it is low the retriggerable monostable
multivibrator is reset.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration of
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the S/P register is not loaded into the P/S register.
• While the monostable multivibrator is being reset, data can not be loaded in the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant,
the register will not be rewritten by CRCOK and others.
• Fig. 2-3 shows Timing Chart.
• Although a clock is input from SQCK pin to actually perform these operations, the high and low intervals for
this clock should be between 750ns and 120µs.
– 25 –
CXD2508AQ/AR
Timing Chart 2-1
Interrel
PLL clock
4.3218 ±∆MHz
WFCK
SCOR
EXCK
400ns max
S0 • S1
SBSO
Q
R
WFCK
SCOR
EXCK
SBSO
S0•S1 Q R S T U V W S0•S1
Same
P1
Q R S T U V W P1
Same
Subcode P.Q.R.S.T.U.V.W Read Timing
– 26 –
P2
P3
SUBQ
SI
LD
H G F E D C B A
A B C D E F G H
SIN
Order
Inversion
– 27 –
CRCC
SUBQ
8
LD
(ASEC)
8
(AMIN)
80bit S/P Register
8
80bit S/P Register
Mono/Multi
LD
(AFRAM)
LD
SHIFT
8
8
8
8
LD
Mix
CRCF
8
SHIFT
SQSO
8
ADDRS CTRL
LD
Block Diagram 2-2
SQCK
SO
CXD2508AQ/AR
LD
LD
– 28 –
SQSO
SQCK
CRCF
Mono/multi (Interral)
SQCK
SQSO
SCOR
WFCK
Timing Chart 2-3
CRCF1
1
2
Order
Inversion
ADR1
3
2
1
94
ADR2
ADR3
270 to 400µs for SQCK = High
CTL0
Determined by mode
93
92
91
Registere load forbidder
80 Clock
750ns to 120µs
300ns max
ADR0
3
95
L
CTL1
96
CTL2
97
CTL3
CRCF2
98
CXD2508AQ/AR
CXD2508AQ/AR
3. Description of Other Functions
3-1. Channel Clock Regeneration by Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is demodulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result,
T, that is channel clock, is required.
In an actual player, the fluctuation in the spindle rotation alters the width of the EFM signal pulses, making a
PLL necessary for regenerating channel clock.
The block diagram of this PLL is shown in Fig. 3-1.
The CXD2508AQ/AR has a built-in two-stage PLL as shown in the diagram.
• The first-stage PLL generates a high-frequency clock needed by the second-stage digital PLL.
• The second-stage PLL is a digital PLL that regenerates the actual channel clock, and has a ±250kHz (normal
state) or more capture range.
Block Diagram 3-1
OSC
X'tal
I/M
Phase
comparator
PCO
I/N
FILI
FILO
CLTV
VCO
VDD
Digital PLL
RFPLL
– 29 –
CXD2508AQ/AR
3-2. Frame Sync Protection
• In a CD player operating at normal speed, a frame sync is recorded approximately every 136µs (7.35kHz).
This signal is used as a reference to know which data is the data within a frame. Conversely, if the frame
sync can not be recognized, the data is processed as error data because it can not be recognized what the
data is. As a result, recognizing the frame sync properly is extremely important for improving playability.
• In the CXD2508AQ/AR, window protection and forward protection/backward protection have been adopted
for frame sync protection. The adoption of these functions achieves very powerful frame sync protection.
There are two window widths: one for cases where a rotational disturbance affects the player and the other
for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is
fixed to 13, and the backward protection counter is fixed to 3. In other words, when the frame sync is being
played back normally and then can not be detected due to scratches, a maximum of 13 frames are inserted.
If frame sync can not be detected for 13 frames or more, the window is released and the frame sync is
resynchronized.
In addition, immediately after the window is released and resynchronization is executed, if a proper frame
sync can not be detected within 3 frames, the window is released immediately.
3-3. Error Correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code
is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.
• The CXD2508AQ/AR SEC strategy provides excellent playability through powerful frame sync protection and
C1 and C2 error corrections.
• The correction status can be monitored outside the LSI.
See Table 3-1.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held for that
data, or an average value interpolation was made.
MNT3
MNT1
MNT0
Description
0
0
0
No C1 errors
0
0
1
One C1 errors corrected
0
1
1
C1 correction impossible
1
0
0
No C2 errors
1
0
1
One C2 errors corrected
1
1
1
C2 correction impossible
Table 3-1.
– 30 –
CXD2508AQ/AR
Timing Chart 3-2
Normal-speed PB
400 to 500ns
RFCK
t = Dependent on error
condition
MNT3
C1 correction
C2 correction
MNT1
MNT0
Strobe
Strobe
C4M
MNTO, 1, 3
Valid
Valid
Invalid
3-4. DA Interface
• The CXD2508AQ/AR DA interface is as described below.
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is
high, the data is for the left channel.
– 31 –
RO
1
2
3
– 32 –
PCMD
WDCK
BCK
(4.23M)
LRCK
(88.2k)
RO
1
2
4
5
Lch MSB (15)
Lch MSB (15)
48bit slot Double-Speed Playback
PCMD
WDCK
BCK
(2.12M)
LRCK
(44.1k)
48bit slot Normal-Speed Playback
Timing Chart 3-3
6
7
8
9
L14
10
L13
11
L12
12
LO
24
L11
L9
Rch MSB
L10
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2508AQ/AR
CXD2508AQ/AR
3-5. Digital Out
There are three Digital Out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for
home use, and the type 2 form 2 format for the manufacture of software.
The CXD2508AQ/AR supports type 2 form 1.
Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3)
of channel status.
Digital Out C bit
0
2
3
From sub Q
0
ID0
16
1
0
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ID1 COPY Emph
0
0
0
32
48
0
176
bit0 to 3 – Sub Q control bits that matched twice with CRCOK
Table 3-2.
3-6. Servo Auto Sequencer
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1 track jump, 2N track jumps, and N track move are executed
automatically.
SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when
XBUSY = low), so that commands from the CPU are not transferred to the SSP, but they can be sent to the
CXD2508AQ/AR.
Connect the CPU, RF and SSP as shown in Fig. 3-4.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point. This is designed to prevent the transfer of erroneous data to the SSP when XBUSY
changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is
low).
– 33 –
CXD2508AQ/AR
(a) Auto Focus ($47)
Focus search up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-5. The auto focus starts with
focus search up, and the pickup should be lowered beforehand (focus search down). In addition, blind E of
register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling edge
of FZC after FZC has been continuously high for a longer time than E.
Connection diagram for using auto sequencer (example)
RF
FOK
FOK
DATA
CXD2508A
SSP
CLOK
Micro-computer
XLAT
C. out
CNIN
SENS
SEIN
DATA
DATO
CLK
CLKO
XLT
XLTO
SENS
Fig. 3-4.
Auto focus
Focus search up
FOK = H
NO
YES
(Checks whether FZC is continuously high or
not for the period of time E set in register 5)
FZC = H
NO
YES
FZC = L
NO
YES
Focus servo ON
END
Fig. 3-5-(a). Auto Focus Flow Chart
– 34 –
CXD2508AQ/AR
$47latch
XLT
FOK
SEIN (FZC)
BUSY
Command
for SSP
Blind E
$08
$03
Fig. 3-5-(b). Auto Focus Timing Chart
(b) Track Jump
1, 10, and 2N-track jumps are performed respectively. Always use this when focus, tracking, and the sled
servo are on. Note that tracking gain up and braking on ($17) should be sent beforehand because they are
not performed.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, an FWD (REV) 1-track jump is performed in accordance
with Fig. 3-6. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, an FWD (REV) 10-track jump is performed in
accordance with Fig. 3-7. The principal difference between the 10-track jump and the 1-track jump is whether
to kick the sled or not. In addition, after kicking the actuator, 5 tracks have been counted through CNIN, and
the brake is applied to the actuator. Then, the actuator speed is found to have slowed up enough
(determined by the CNIN cycle becoming longer than the overflow C set in register 5), and the tracking and
sled servos are turned on.
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, an FWD (REV) 2N-track jump is performed in
accordance with Fig. 3-8. The track jump count "N" is set in register 7. Although N can be set to 216 tracks,
note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set in register 6.
• N-track move
When $4E ($4F for REV) is received from the CPU, an FWD (REV) N-track move is performed in accordance
with Fig. 3-9. N can be set to a maximum of 216 tracks. CNIN is used for counting the number of jumps. This
N-track move uses a method in which only the sled is moved, and is suited for moves over thousands of
tracks.
– 35 –
CXD2508AQ/AR
Track
(REV kick for REV jump)
Track kick
sled servo
WAIT
(Blind A)
CNIN =
NO
YES
(FWD kick for REV jump)
Track REV
kick
WAIT
(Brake B)
Track sled
servo ON
END
Fig. 3-6-(a). 1-Track Jump Flow Chart
$48 (REV = $49) latch
XLT
CNIN
BUSY
Command
for SSP
Brake B
Blind A
$28 ($2C)
$2C ($28)
Fig. 3-6-(b). 1-Track Jump Timing Chart
– 36 –
$25
CXD2508AQ/AR
10 Track
Track, sled
FWD kick
WAIT
(Blind A)
(Counts CNIN × 5)
CNIN=5 ?
NO
YES
Track, REV
kick
C = Overflow ?
NO
(Checks whether the CNIN
cycle is longer than overflow C)
YES
Track sled
servo ON
END
Fig. 3-7-(a). 10-Track Jump Flow Chart
$4A (REV = $4B) latch
XLT
CNIN
BUSY
Blind A
Command
for SSP
CNIN 5count
Overflow C
$2E ($2B)
$2A ($2F)
Fig. 3-7-(b). 10-Track Jump Timing Chart
– 37 –
$25
CXD2508AQ/AR
2N Track
Track, sled
FWD kick
WAIT
(Blind A)
CNIN = N
NO
YES
Track REV
kick
C = Overflow
NO
YES
Track servo
ON
WAIT
(Kick D)
Sled servo
ON
END
Fig. 3-8-(a). 2N-Track Jump Flow Chart
$4C (REV = $4D) latch
XLT
CNIN
BUSY
Blind A
Command
for SSP
$2A ($2F)
CNIN
N count
Overflow
$2E ($2B)
$26 ($27)
Fig. 3-8-(b). 2N-Track Jump Timing Chart
– 38 –
Kick D
$25
CXD2508AQ/AR
N Track move
Track servo OFF
Sled FWD kick
WAIT
(Blind A)
CNIN = N
NO
YES
Track, sled
servo ON
END
Fig. 3-9-(a). N-Track Move Flow Chart
$4E (REV = $4F) latch
XLT
CNIN
BUSY
Blind A
Command
for SSP
CNIN N count
$25
$22 ($23)
Fig. 3-9-(b). N-Track Move Timing Chart
– 39 –
CXD2508AQ/AR
3-7. Digital CLV
Fig. 3-10 shows the Block Diagram. Digital CLV makes PWM output in CLVS and CLVP with the MDS error
and MDP error signal sampling frequency increased to 130kHz during normal-speed operation.
In addition, the digital spindle servo can set the gain.
Digital CLV
Gain
CLVS U/D
MDS Error
MDP Error
0, –6dB
Measure
Measure
CLVS P/S
Over Sampling
Filter-1
2/1 MUX
GS (Gain)
GP (Gain)
1/2
Mux
Over Sampling
Filter-2
CLV P
CLV S
CLV-P/S
Noise Shape
KICK, BRAKE STOP
Modulation
Mode Select
DCLVMD
Fig. 3-10. Block Diagram
– 40 –
MDP
MDS
CXD2508AQ/AR
3-8. Asymmetry Compensation
Fig. 3-11 shows the Block Diagram and Circuit Example.
ASYE
ASYO
R1
RF
R1
R2
R1
ASYI
R1
BIAS
R2
2
=
R1
5
Fig. 3-11. Example of Asymmetry Compensation Application Circuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 41 –
CXD2508AQ/AR
3-9. Setting Method of the CXD2508AQ/AR Playback Speed
(a) Signal processing block (DSP block)
The playback mode shown below can be selected by the combination of crystal, XTSL pin and doublespeed command (DSPB) in the CXD2508AQ/AR.
Playback mode at DSP block
Mode
Crystal
XTSL
DSPB
Speed at DSP block
1
768Fs
1
0
×1
2
768Fs
1
1
×2
3
384Fs
0
0
×1
4
5∗1
384Fs
0
1
×2
384Fs
1
1
×1
Fs = 44.1kHz
∗1 Low power consumption mode. The processing speed is halved in the LSI so that the power consumption
can be decreased.
(b) DAC block
The operating speed at DAC block is determined by the crystal and the double-speed command DADS in
DAC block in spite of the operating conditions of DSP block mentioned above. Then, the playback mode for
DAC block and DSP block can be determined independently. (For example, normal-speed playback for DSP
block; low power consumption playback for DAC block.) The DAC block supports the normal speed and
double speed.
∗ DADS is controlled by sending the command to DSP block.
Playback mode at DAC block
Mode
Crystal
DADS
Speed at DAC block
1
768Fs
0
×1
2
3∗2
768Fs
1
×2
384Fs
1
×1
∗2 Low power consumption mode. The processing speed is halved in the LSI so that the power consumption
can be decreased.
– 42 –
CXD2508AQ/AR
4. 1-bit DAC Block
4-1. PWM Output Pattern
In the CXD2508AQ/AR, PWM outputs from the DAC include forward phase PWM (RPWM, LPWM) and
inverted PWM (NRPWM, NLPWM). By determining the difference between these PWM outputs in the
subsequent analog LPF, the noise and others can be canceled in the digital block. In addition, this method also
yields improvements in the analog characteristics.
The PWM output waveforms differ for each of the CXD2508AQ/AR three playback modes (normal, doublespeed, and pseudo double-speed). (In the following explanation, Fs = 44.1kHz.)
During normal speed playback (DSPB = 0, crystal = 768Fs), eleven values (integers from –5 to 5) are taken
within the 32Fs cycle. The minimum pulse width is –5, and the maximum pulse width is +5. The minimum
variation width of change for PWM is the 384 Fs cycle. (See Fig. 4-3.)
LPWM
(RPWM)
Noise shaper
output value
5
4
3 • • •
• • • –3 –4 –5
–5 –4 –3 • • •
• • • 3
4
5
NLPWM
(NRPWM)
33.8688 [MHZ]
(768Fs)
1.4112 [MHZ] (32Fs)
Fig. 4-1.
In double-speed playback (DSPB = 1, crystal = 768Fs), five values (–4, –2, 0, 2, 4) are taken within the 64Fs
cycle. (See Fig. 4-4.)
4
2
0
33.8688 [MHz]
(768Fs)
–2 –4
LPWM
(PRWM)
–4 –2
0
2
4
2.8224 [MHz] (64Fs)
Fig. 4-2.
In pseudo double-speed playback (DSPB = 1, crystal = 384Fs), five values (–4, –2, 0, 2, 4) are taken within the
32Fs cycle. (See Fig. 4-5.)
4
2
0
–2
16.9344 [MHz]
(384Fs)
–4
LPWM
(RPWM)
–4
–2
0
2
4
1.4112 [MHz] (32Fs)
Fig. 4-3.
4-2. Input Timing for DAC Block
Fig. 4-4 shows the input timing for DAC section.
In the CXD2508AQ/AR, there is no internal transfer of sound data from the CD signal processing block to DAC
block. Therefore, data can be transferred to DAC block through an audio DSP and others.
When data is input to DAC block without passing through an audio DSP or similar device, data should be
connected externally. In that case, EMPH, LRCK, and PCMD can be connected directly with EMPHI, LRCKI,
and PCMDI respectively. (See the Application Circuit.)
– 43 –
1
– 44 –
PCMDI
BCKI
(4.23M)
LRCKI
(88.2k)
RO
1
2
2
3
Lch MSB (15)
Double-Speed Playback
PCMDI RO
BCKI
(2.12M)
LRCKI
(44.1k)
Normal-Speed Playback
5
Lch MSB (15)
4
6
7
8
L14
10
L13
11
L12
24
L11
LO
12
Rch MSB
L10
L9
Fig. 4-4. Input Timing for DAC Block
9
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2508AQ/AR
CXD2508AQ/AR
4-4. Description of Functions
No-Sound Data Detection
The no-sound data detection function detects low-level data on both the left and right channels in audio data
from the 1Fs 48-bit slot and outputs a zero detection signal when that data continues unchanged for a certain
period of time.
The audio data is in two's complement format and data in which the upper 12 bits are all "0" or all "1" is
regarded as low level data. When this data continues unchanged for 32,768 samples (743ms when Fs =
44.1kHz), the zero detection signal is output. In other words, once a certain period of time during which lowlevel data is detected elapses, the signal is regarded to be in the no-sound state.
The zero detection signal is output from ZEROL (left channel) and ZEROR (right channel) pins. The zero
detection output timing is shown in Fig. 4-5.
Lch
Rch
LRCK
32,768th sample of
low-level data
32,768th sample of
low-level data
ZEROR and ZEROL
Lch
LRCK
Rch
Lch
Low-level data Low-level data
Sound data
Rch
Lch
Rch
Lch
Rch
Lch
Sound data Low-level data Low-level data Low-level data Low-level data Low-level data
ZEROL
ZEROR
Fig. 4-5. Zero Detection Output Timing
– 45 –
CXD2508AQ/AR
Forced Mute
The forced mute can be executed independently for DSP block and DAC block.
DSP can be forcibly muted by setting "1" in MUTE for D1 of register A. This mute can be released by setting
"0" in MUTE for D1 of register A. Also, the both of left and right channels can be forcibly muted by inputting a
high signal to MUTE pin for DAC block (in this event, a soft mute is not performed). In this instance, a fixed
pattern is output for the PWM output. To release the mute, input a low signal to MUTE pin.
Digital De-emphasis
When EMPHI pin (Pin 63) is set high, de-emphasis can be applied by using the IIR filter. However, in normalplayback mode the time constants are as follows:
τ1 = 50µs, τ2 = 15µs.
– 46 –
CXD2508AQ/AR
Application Circuit
ZEROR
ZEROL
ZEROR
VDD
DTS1
NLPWM
AVDD2
LPWM
XTAI
AVDD3
XTA0
AVss3
AVss2
77 76 75 74 73 72 71 70 69 68 67 66 65
NRPWM
DTS2
RPWM
WFCK 64
2 SBSO
EXCK
EMPH 62
4 SQSO
DOUT 61
5 SQCK
C4M 60
MNT1 57
MNT3 56
XROF 55
11 CLOK
XROF
C2PO 54
12 Vss
CXD2508AQ
Vss 53
13 SEIN
RFCK 52
14 CNIN
GFS 51
15 DATO
XPCK 50
16 XLTO
XUGF 49
17 CLKO
GTOP 48
18 SPOA
BCKI 47
19 SPOB
GND
9 DATA
10 XLAT
GND
MNT0
MNT1
MNT2
MNT3
GND
MNT0 58
8 XRST
GND
DOUT
FSTT 59
7 SENS
RFCK
GFS
XPCK
XUGF
GTOP
BCK 46
20 SPOC
PCMDI 45
21 XTSL
PCMD 44
22 XLON
LRCKI 43
ASYE
ASYO
ASYI
BIAS
RF
AVDD1
CLTV
AVSS1
VDO
PCO
FILI
FILO
TEST
LOCK
MDP
24 MON
MDS
23 FOK
LRCK 42
WDCK 41
WDCK
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
GND
GND
DR IVER
to CPU
6 MUTE
LDON
FOK
SENS
XRST
DATA
XLAT
CLK
GFS
SQSO
SQCK
SCOR
MUTE
COUT
VDD
GND
WFCK
GND
3
EMPHI 63
LDON
GND
RF
RF
SSP
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 47 –
to error rate counter
1 SCOR
DTS3
80 79 78
ZEROL
GND
CXD2508AQ/AR
Package Outline
Unit: mm
CXD2508AQ
80PIN QFP (PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
64
0.15
41
65
16.3
+ 0.4
14.0 – 0.1
17.9 ± 0.4
40
A
80
+ 0.2
0.1 – 0.05
1
24
0.8
0.12
+ 0.15
0.35 – 0.1
M
0.8 ± 0.2
25
+ 0.35
2.75 – 0.15
0° to 10°
DETAIL A
PACKAGE STRUCTURE
SONY CODE
QFP-80P-L01
EIAJ CODE
∗QFP080-P-1420-A
JEDEC CODE
PACKAGE MATERIAL
EPOXY RESIN
LEAD TREATMENT
SOLDER PLATING
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.6g
CXD2508AQ
80PIN QFP (PLASTIC)
24.0 ± 0.3
+ 0.4
20.0 – 0.1
+ 0.
0.15 – 1
0.05
25
1
24
0.8
± 0.12 M
+ 0.15
0.35 – 0.1
16.6
80
0.7 ± 0.
40
+ 0.4
14.0 – 0.1
65
1
41
18.0 ± 0.3
64
+ 0.2
0.1 – 0.05
2.7 ± 0.1
0° to 10°
3.1 MAX
0.15
22.6
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L121
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP080-P-1420-AX
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
1.6g
JEDEC CODE
– 48 –
CXD2508AQ/AR
CXD2508AQ
QFP 80PIN (PLASTIC)
23.9 ± 0.2
∗20.0 ± 0.2
0.15 ± 0.05
40
24
.2
1
0.35 ± 0.1
C1
15°
15°
25
80
A
4 – 1.0
∗14.0 ± 0.2
17.9 ± 0.2
65
0.8
41
64
4 – 0.8
0.15
M
1.45
0.8 ± 0.15
1.95 ± 0.15
0.15
2.94 ± 0.15
15°
0.24 ± 0.15
+ 0.20
2.7 – 0.16
15°
0° to 10°
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L051
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP080-P-1420-AH
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
1.6g
JEDEC CODE
CXD2508AR
80PIN LQFP (PLASTIC)
14.0 ± 0.2
∗
12.0 ± 0.1
60
41
40
(13.0)
61
0.5 ± 0.2
A
21
(0.22)
80
1
20
+ 0.08
0.18 – 0.03
0.5 ± 0.08
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0.5 ± 0.2
0.1 ± 0.1
0° to 10°
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
LQFP-80P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP080-P-1212-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.5g
JEDEC CODE
– 49 –