SONY CXD2589Q

CXD2589Q
CD Digital Signal Processor
Description
The CXD2589Q is a digital signal processor LSI for
CD players and is equipped with built-in digital
filters, zero detection circuit, 1-bit DAC, and analog
low-pass filter on a single chip.
Features
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV
(Constant Angular Velocity)
– Frame jitter-free
– Allows 0.5 to double-speed continuous playback
– Allows relative rotational velocity readout
– Supports external spindle control
• Wide capture range playback mode
– Spindle rotational velocity following method
– Supports normal-speed and double-speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• Serial bus-based CPU interface
• Error correction monitor signals, etc. are output
from a new CPU interface.
• Servo auto sequencer
• Digital audio interface output
• Digital peak meter
80 pin QFP (Plastic)
Absolute Maximum Ratings
–0.3 to +7.0
V
• Supply voltage VDD
• Input voltage
VI
–0.3 to +7.0
V
(Vss – 0.3V to VDD + 0.3V)
• Output voltage VO
–0.3 to +7.0
V
• Storage temperature
Tstg
–40 to +125
°C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3
V
VDD – AVDD –0.3 to +0.3
V
Note) AVDD includes XVDD, and AVSS includes XVSS.
Recommended Operating Conditions
• Supply voltage VDD
3.4 to 5.25
V
• Operating temperature
Topr
–20 to +75
°C
Note) The VDD (min.) for the CXD2589Q varies
according to the playback speed selection.
VDD (min.) [V]
Digital Filter, DAC, Analog Low-Pass Filter Block
• DBB (Digital Bass Boost)
• Supports double-speed playback
• Digital de-emphasis
• Digital attenuation function
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more (master clock: 384Fs typ.)
Logical value: 109dB
• THD + N: 0.007% or less
(master clock: 384Fs typ.)
• Rejection band attenuation: –60dB or less
Playback
speed
DAC block
VCO high VCO normal
speed
speed
2×
3.4
1×
3.4
3.5
1×∗1
3.4
3.5
4.5
3.4
∗1 When the internal operation of the CD-DSP
side is set to double-speed mode and the
crystal oscillation frequency is halved,
normal-speed playback results.
Applications
CD players
Structure
Silicon gate CMOS IC
CD-DSP block
Input/Output Capacitances
• Input capacitance CI
12 (max.)
• Output capacitance CO
12 (max.)
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
pF
pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96Y02A73
CXD2589Q
PCMDI
BCKI
55 40 42 44 62
SYSM
43
LRCKI
EMPHI
47 49 54 56
LRCK
50 39 41
C2PO
WFCK
EMPH
GFS
XUGF
BCK
27 28
PCMD
51 25 26
VCTL
V16M
VPCO
VCKI
XTSL
Block Diagram
24 TES1
23 TEST
OSC
Clock
Generator
C4M 52
Error
Corrector
79 XRST
D/A
Interface
EFM
demodurator
RF 35
Serial-In
Interface
3
RMUT
2
LMUT
ASYI 37
ASYO 38
Asymmetry
Corrector
70 XTAI
Timing
Logic
BIAS 36
71 XTAO
Over Sampling
Digital Filter
16K
RAM
XPCK 48
Digital
PLL
FILI 31
3rd-Order
Noise Shaper
Digital
OUT
FILO 30
Sub Code
Processor
PCO 29
PWM
CLTV 33
21
22
53
74
75
76
67
66 65
MDP
PWMI
DOUT
LOUT2
AIN2
AOUT2
LOUT1
AOUT1
–2–
AIN1
4
SQCK
EXCK
SQSO
CLOK
SBSO
XLAT
17 57 58 59 5
SCOR
9 15 16
XLON
8
SPOB
7
SPOA
6
XLTO
12 13 14
SENS
Digital
CLV
DATA
CPU
Interface
CLKO
CNIN 11
Servo
Auto
Sequencer
DATO
FOK 18
SEIN 10
PWM
CXD2589Q
PCMD
PCMDI
BCKI
BCK
Vss
VDD
XUGF
XPCK
GFS
C2PO
XTSL
C4M
DOUT
EMPH
EMPHI
WFCK
SCOR
SBSO
EXCK
Vss
Pin Configuration
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VDD 61
40 LRCKI
SYSM 62
39 LRCK
AVss 63
38 ASYO
AVDD 64
37 ASYI
AOUT1 65
36 BIAS
35 RF
AIN1 66
LOUT1 67
34 AVDD
AVss 68
33 CLTV
XVDD 69
32 AVss
XTAI 70
31 FILI
XTAO 71
30 FILO
XVss 72
29 PCO
AVss 73
28 VCTL
LOUT2 74
27 V16M
AIN2 75
26 VCKI
AOUT2 76
25 VPCO
AVDD 77
24 TES1
AVss 78
23 TEST
XRST 79
22 PWMI
VDD 80
–3–
Vss
VDD
FOK
XLON
SPOB
SPOA
CLKO
XLTO
DATA
9 10 11 12 13 14 15 16 17 18 19 20
DATO
SENS
8
SEIN
7
CNIN
6
XLAT
5
CLOK
4
SQCK
3
SQSO
2
LMUT
Vss
1
RMUT
21 MDP
CXD2589Q
Pin Description
Pin
No.
Symbol
I/O
Description
GND
1
VSS
—
—
2
LMUT
O
1, 0
Left-channel zero detection flag.
3
RMUT
O
1, 0
Right-channel zero detection flag.
4
SQCK
I
5
SQSO
O
1, 0
Sub Q 80-bit serial output.
6
SENS
O
1, 0
SENS output to CPU.
7
DATA
I
Serial data input from CPU.
8
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
9
CLOK
I
Serial data transfer clock input from CPU.
10
SEIN
I
SENS input from SSP.
11
CNIN
I
Track jump count signal input.
12
DATO
O
1, 0
Serial data output to SSP.
13
XLTO
O
1, 0
Serial data latch output to SSP. Latched at the falling edge.
14
CLKO
O
1, 0
Serial data transfer clock output to SSP.
15
SPOA
I
Microcomputer extended interface (input A).
16
SPOB
I
Microcomputer extended interface (input B).
17
XLON
O
18
FOK
I
19
VDD
—
—
Power supply (+5V).
20
VSS
—
—
GND
21
MDP
O
22
PWMI
I
Spindle motor external control input.
23
TEST
I
TEST pin; normally GND.
24
TES1
I
TEST pin; normally GND.
25
VPCO
O
26
VCKI
I
27
V16M
O
28
VCTL
I
29
PCO
O
1, Z, 0 Master PLL charge pump output.
30
FILO
O
Analog Master PLL (slave = digital PLL) filter output.
31
FILI
I
32
AVSS
—
33
CLTV
I
34
AVDD
—
35
RF
I
SQSO readout clock input.
1, 0
Microcomputer extended interface (output).
Focus OK input.
Used for SENS output and the servo auto sequencer.
1, Z, 0 Spindle motor servo control.
1, Z, 0 Charge pump output for the wide-band EFM PLL.
VCO2 oscillation input for the wide-band EFM PLL.
1, 0
VCO2 oscillation output for the wide-band EFM PLL.
VCO2 control voltage input for the wide-band EFM PLL.
Master PLL filter input.
—
Analog GND.
Master VCO control voltage input.
—
Analog power supply (+5V).
EFM signal input.
–4–
CXD2589Q
Pin
No.
Symbol
I/O
Description
36
BIAS
I
Constant current input of the asymmetry circuit.
37
ASYI
I
Asymmetry comparator voltage input.
38
ASYO
O
1, 0
EFM full-swing output (low = VSS, high = VDD).
39
LRCK
O
1, 0
D/A interface. LR clock output f = Fs.
40
LRCKI
I
41
PCMD
O
42
PCMDI
I
43
BCK
O
44
BCKI
I
45
VSS
—
—
GND
46
VDD
—
—
Power supply (+5V).
47
XUGF
O
1, 0
XUGF output. Switched to MNT1 or RFCK output by a command.
48
XPCK
O
1, 0
XPLCK output. Switched to MNT0 output by a command.
49
GFS
O
1, 0
GFS output. Switched to MNT3 or XRAOF output by a command.
50
C2PO
O
1, 0
C2PO output. Switched to GTOP output by a command.
51
XTSL
I
52
C4M
O
1, 0
4.2336MHz output. 1/4 frequency-divided VCKI output in CAV-W mode.
53
DOUT
O
1, 0
Digital Out output.
54
EMPH
O
1, 0
Outputs a high signal when the playback disc has emphasis, and a low
signal when there is no emphasis.
55
EMPHI
I
56
WFCK
O
1, 0
WFCK output.
57
SCOR
O
1, 0
Outputs a high signal when either subcode sync S0 or S1 is detected.
58
SBSO
O
1, 0
Sub P to W serial output.
59
EXCK
I
60
VSS
—
—
GND
61
VDD
—
—
Power supply (+5V).
62
SYSM
I
63
AVSS
—
—
Analog GND.
64
AVDD
—
—
Analog power supply (+5V).
65
AOUT1
O
Left-channel analog output.
66
AIN1
I
Left-channel operational amplifier input.
67
LOUT1
O
Left-channel LINE output.
68
AVSS
—
69
XVDD
70
XTAI
I
Crystal oscillation circuit input. Input the external master clock via this pin.
71
XTAO
O
Crystal oscillation circuit output.
LR clock input.
1, 0
D/A interface. Serial data output (two's complement, MSB first).
D/A interface. Serial data input (two's complement, MSB first).
1, 0
D/A interface. Bit clock output.
D/A interface. Bit clock input.
Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz.
Inputs a high signal when de-emphasis is on, and a low signal when
de-emphasis is off.
SBSO readout clock input.
Mute input. Active when high.
—
Analog GND.
Power supply for master clock.
–5–
CXD2589Q
Pin
No.
Symbol
I/O
Description
GND for master clock.
72
XVSS
73
AVSS
—
74
LOUT2
O
Right-channel LINE output.
75
AIN2
I
Right-channel operational amplifier input.
76
AOUT2
O
Right-channel analog output.
77
AVDD
—
—
Analog power supply (+5V).
78
AVSS
—
—
Analog GND.
79
XRST
I
80
VDD
—
—
Analog GND.
System reset. Reset when low.
—
Power supply (+5V).
Notes) • PCMD is an MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)
• XUGF is the frame sync obtained from the EFM signal, and a negative pulse. It is the signal before
sync protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK
and the EFM signal transition point coincide.
• GFS goes high when the frame sync and the insertion protection timing match.
• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs (during normal speed).
• C2PO represents the data error status.
• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.
–6–
CXD2589Q
Electrical Characteristics
DC Characteristics
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C) ∗
Item
Conditions
Min.
Input voltage High level input voltage VIH (1)
(1)
Low level input voltage VIL (1)
0.7VDD
Input voltage High level input voltage VIH (2)
Schmitt input
(2)
Low level input voltage VIL (2)
0.8VDD
Input voltage
Input voltage
(3)
Typ.
Max.
V
0.3VDD
VIN (3) Analog input
Unit
V
0.2VDD
V
Vss
VDD
V
VDD – 0.5
VDD
V
0
0.4
V
VDD – 0.5
VDD
V
0
0.4
V
High level output voltage VOH (1) IOH = –1mA
Output
voltage (2)
High level output voltage VOH (2) IOH = –1mA
Output
voltage (4)
High level output voltage VOH (4) IOH = –0.28mA VDD – 0.5
VDD
V
Low level output voltage VOL (4) IOL = 0.36mA
0
0.4
V
Low level output voltage VOL (2) IOL = 2mA
∗1
V
Output
voltage (1)
Low level output voltage VOL (1) IOL = 1mA
Applicable
pins
∗2
∗3
∗4
∗5
∗6
Input leak current
ILI
VI = 0 to 5.50V
–5
5
µA
∗1, ∗2, ∗3
Tri-state pin output leak current
ILO
VO = 0 to 5.50V
–5
5
µA
∗7
Applicable pins
∗1 XTSL, DATA, XLAT, PWMI, SYSM, EMPHI, PCMDI
∗2 CLOK, XRST, EXCK, SQCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, SPOA, SPOB
∗3 CLTV, FILI, RF, VCTL, AIN1, AIN2
∗4 MDP, PCO, VPCO
∗5 ASYO, DOUT, C4M, SBSO, SQSO, SCOR, EMPH, DATO, CLKO, XLTO, SENS, WFCK, V16M, LMUT,
RMUT, XLON, LRCK, PCMD, BCK, XUGF, XPCK, GFS, RFCK, C2PO
∗6 FILO
∗7 SENS, PCO, VPCO
∗note) : XVDD and XVSS are included for AVPP and AVSS, respectively.
Those are the same for the explanation from the next page.
–7–
CXD2589Q
AC Characteristics
1. XTAI pin
(1) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Symbol
Oscillation frequency fMAX
Min.
Typ.
15
Max.
Unit
34
MHz
(2) When inputting pulses to XTAI pin
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Symbol
tWHX
Low level pulse width tWLX
High level pulse width
Max.
Unit
13
500
ns
13
500
ns
1,000
ns
Min.
Typ.
Pulse cycle
tCK
26
Input high level
VIHX
VDD – 1.0
Input low level
VILX
0.8
V
Rise time, fall time
tR, tF
10
ns
V
tCK
tWLX
tWHX
VIHX
VIHX × 0.9
VDD/2
XTAI
VIHX × 0.1
VILX
tR
tF
(3) When inputting sine waves to XTAI pin via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Input amplitude
Symbol
Min.
V1
2.0
Typ.
Max.
Unit
VDD + 0.3 Vp-p
–8–
CXD2589Q
2. CLOK, DATA, XLAT, CNIN, SQCK and EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Clock frequency
fCK
Clock pulse width
Latch pulse width
tWCK
tSU
tH
tD
tWL
EXCK SQCK frequency
fT
Setup time
Hold time
Delay time
EXCK SQCK pulse width
Min.
Typ.
Max.
Unit
0.65
MHz
750
ns
300
ns
300
ns
300
ns
750
ns
0.65∗
MHz
750∗
fWT
ns
1/fCK
tWCK
tWCK
CLK
DATA
XLT
tSU
tH
EXCK
CNIN
SQCK
tD
tWT
tWL
tWT
1/fT
SQSO
SBSO
tSU
tH
∗ In pseudo double-speed playback mode, except when SQSO is Sub Q Read, the maximum operating
frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs.
3. BCKI, LRCKI and PCMDI pins
Item
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Symbol Conditions
BCK pulse width
tW
tSU
tH
tSU
DATAL, R setup time
DATAL, R hold time
LRCK setup time
Min.
Typ.
Unit
94
ns
18
ns
18
ns
18
ns
tW(BCKI) tW(BCKI)
BCKI
Max.
VDD/2
VDD/2
tSU
tH
(PCMDI) (PCMDI)
PCMDI
tSU
(LRCKI)
LRCKI
–9–
CXD2589Q
1-bit DAC, LPF Block Analog Characteristics
Analog Characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)
Symbol
Item
Total
harmonic
distortion
THD
S/N ratio
S/N
Typ.
Max.
384Fs
0.0050
0.0070
768Fs
0.0045
0.0065
Min.
Crystal
Conditions
1kHz, 0dB data
1kHz, 0dB data
(using A-weighting filter)
384Fs
96
100
768Fs
96
100
For both items, Fs = 44.1kHz.
The total harmonic distortion and S/N ratio measurement circuits are shown below.
12k
AOUT1 (2)
680p
12k
12k
SHIBASOKU (AM51A)
AIN1 (2)
150p
LOUT1 (2)
Audio Analyzer
22µ
100k
LPF External Circuit Diagram
768Fs/384Fs
DATA
TEST DISC
Rch
A
Lch
B
RF
CXD2589Q
Block Diagram for Measuring Analog Characteristics
– 10 –
Audio Analyzer
Unit
%
dB
CXD2589Q
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = – 20 to +75°C)
Item
Symbol
Output voltage
VOUT
Load resistance
RL
Min.
Typ.
1.12∗
8
Max.
Unit
Applicable pins
Vrms
∗1
kΩ
∗1
∗ Measured using the circuits on the previous page when a sine wave of 1kHz and 0dB is
output.
Applicable pins
∗1 LOUT1, LOUT2
– 11 –
CXD2589Q
Description of Functions
1. CPU Interface and Commands
• CPU Interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
D1
D2
Data
D3
D0
D1
D2
D3
750ns or more
Address
XLAT
Registers 4 to E
Valid
300ns max
• Information on each address and the data is provided in Table 1-1.
• The internal registers are initialized by a reset when XRST is low; the initialization data is shown in Table 1-2.
Note) When XLAT is low, SQCK must be set high.
– 12 –
– 13 –
1
1
1
1
Serial bus
CTRL
Servo coefficient
setting
CLV CTRL
CLV mode
B
C
D
E
0
0
1
1
1
1
1
1
0
0
1
0
1
1
0
0
1
Audio CTRL
1
A
0
0
1
MODE
specification
8
9
0
0
0
Auto sequence
(N) track jump
count
7
Function
specification
1
1
0
Kick (D)
6
1
0
1
0
Blind (A, E),
Overflow (C)
Brake (B)
5
1
0
1
0
Auto sequence
4
D1
D2
Address
D3
Command
Register name
Command Table
0
1
0
1
0
0
1
1
0
1
0
1
0
D0
D2
D1
D0
—
—
—
D3
—
—
—
D2
—
—
—
D1
Data 2
0
0
Mute ATT
Mute ATT
0
SL0 CPUSR
0
0
DSPB
ON/OFF
TB
TP
SYCOF
SYCOF
—
—
ZDPL ZMUT
ZDPL ZMUT
Table 1-1
0
—
1
2
—
—
—
D1
0
—
0
1
—
—
—
D0
0
—
—
—
—
DCOF
—
—
—
—
—
—
—
—
D2
D3
0
—
—
—
—
—
—
D1
Data 5
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D3
D0
—
—
—
—
—
—
—
—
D2
—
—
—
—
—
—
—
—
D1
Data 6
—
—
—
—
—
—
—
—
D0
—
0
0
—
Gain Gain
CAV1 CAV0
—
—
—
0
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT LRWO BSBST BBSL
—
—
0
0
0
0
0
4
—
—
—
D2
Data 4
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0
0
0
8
—
—
—
D3
Gain
VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
CLVS
—
16
—
—
—
D0
—
—
32
—
—
—
D1
—
—
0
OPSL2
EMPH SMUT
1
0
OPSL1
MCSL
1
OPSL1
MCSL
0
OPSL2
EMPH SMUT
0
0
64
—
—
—
D2
VCO
KSL3 KSL2 KSL1 KSL0
SEL2
128
—
—
—
D3
Data 3
CM3 CM2 CM1 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON
0
0
0
0
0
SOCT
256
—
—
—
D0
TRMI TRMO MTSL1 MTSL0
0
0
0
0
0
0
DSPB
ON/OFF
0
0
VCO
DOUT DOUT
WSEL
SEL1
Mute ON/OFF
Gain Gain Gain Gain
MDP1 MDP0 MDS1 MDS0
SL1
0
0
0
0
CDROM
32768 16384 8192 4096 2048 1024 512
11.6ms 5.8ms 2.9ms 1.45ms
0.36ms 0.18ms 0.09ms 0.05ms
0.18ms 0.09ms 0.05ms 0.02ms
AS3 AS2 AS1 AS0
D3
Data 1
CXD2589Q
– 14 –
1
Servo coefficient
setting
CLV CTRL
CLV mode
C
D
E
1
1
1
1
Function
specification
9
Serial bus
CTRL
1
MODE
specification
8
B
0
Auto sequence
(N) track jump
count setting
7
1
0
Kick (D)
6
Audio CTRL
0
Blind (A, E),
Overflow (C)
Brake (B)
5
A
0
Auto sequence
4
D3
Command
Register name
Reset Initialization
0
0
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
1
1
D1
D2
Address
0
1
0
1
0
1
0
1
0
1
0
D0
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
1
0
0
0
0
0
1
1
0
D2
0
0
1
1
1
0
0
0
1
0
0
D1
Data 1
0
0
0
0
1
0
0
0
1
1
0
D0
0
1
—
0
0
0
0
0
—
—
—
D3
0
1
—
1
0
0
0
0
—
—
—
D2
0
1
—
0
0
0
0
0
—
—
—
D1
Data 2
0
0
—
0
0
0
0
0
—
—
—
D3
0
0
—
0
0
0
0
0
—
—
—
D2
Table 1-2
0
0
—
0
0
0
0
1
—
—
—
D0
0
0
—
0
0
0
1
0
—
—
—
D1
Data 3
0
0
—
0
0
0
0
0
—
—
—
D0
0
—
—
—
0
0
0
0
—
—
—
D3
0
—
—
—
0
0
0
0
—
—
—
D2
0
—
—
—
0
0
1
0
—
—
—
D1
Data 4
0
—
—
—
0
0
0
0
—
—
—
D0
—
—
—
—
0
0
—
—
—
—
—
D3
—
—
—
—
0
0
—
—
—
—
—
D2
—
—
—
—
0
0
—
—
—
—
—
D1
Data 5
—
—
—
—
0
0
—
—
—
—
—
D0
—
—
—
—
0
—
—
—
—
—
—
D3
—
—
—
—
0
—
—
—
—
—
—
D2
—
—
—
—
0
—
—
—
—
—
—
D1
Data 6
—
—
—
—
0
—
—
—
—
—
—
D0
CXD2589Q
CXD2589Q
1-1. The meaning of the data for each address is explained below.
$4X commands
AS3
AS2
AS1
AS0
CANCEL
0
0
0
0
FOCUS-ON
0
1
1
1
1 TRACK JUMP
1
0
0
RXF
10 TRACK JUMP
1
0
1
RXF
2N TRACK JUMP
1
1
0
RXF
N TRACK MOVE
1
1
1
RXF
Command
RXF = 0 FORWARD
RXF = 1 REVERSE
• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the Track jump/move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is
interrupted.
$5X commands
Auto sequence timer setting
Setting timers: A, E, C, B
Command
D3
D2
D1
D0
Blind (A, E), Over flow (C)
0.18ms
0.09ms
0.05ms
0.02ms
Brake (B)
0.36ms
0.18ms
0.09ms
0.05ms
Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)
A = E = C = 0.11ms
B = 0.23ms
$6X commands
Auto sequence timer setting
Setting timer: D
Command
KICK (D)
D3
D2
D1
D0
11.6ms
5.8ms
2.9ms
1.45ms
Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)
D = 10.15ms
$7X commands
Auto sequence track jump/move count setting (N)
Data 1
Command
Data 2
Data 3
Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Auto sequence track jump 15 14 13 12 11 10
2
2
2
2
2
2
count setting
29
28
27
26
25
24
23
22
21
20
This command is used to set N when a 2N-track jump and an N-track move are executed for auto sequence.
• The maximum track count is 65,535, but note that with 2N-track jumps the maximum track jump count is
determined by the mechanical limitations of the optical system.
• The number of tracks jumped is counted according to the signals input from the CNIN pin.
– 15 –
CXD2589Q
$8X commands
Data 1
Command
D3
D2
D1
Data 2
D0
D3
DOUT DOUT
VCO
MODE
CDROM
WSEL
Mute ON/OFF
SEL1
specification
Data 3
D2
D1
D0
D3
D2
D1
D0
0
SOCT
VCO
SEL2
KSL3
KSL2
KSL1
KSL0
See the $BX commands.
Data 4
D3
D2
D1
D0
0
0
1
0
Command bit
C2PO timing
Processing
CDROM = 1
See Timing Chart
1-1.
CDROM mode; average value interpolation and pre-value hold
are not performed.
CDROM = 0
See Timing Chart
1-1.
Audio mode; average value interpolation and pre-value hold
are performed.
Command bit
Processing
DOUT Mute = 1
Digital Out output is muted. (DA output is not muted.)
DOUT Mute = 0
When no other mute conditions are set, Digital Out output is not muted.
Command bit
Processing
DOUT ON/OFF = 1
Digital Out is output from the DOUT pin.
DOUT ON/OFF = 0
Digital Out is not output from the DOUT pin.
WSEL = 1
Sync protection window width
±26 channel clock∗1
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
Command bit
Application
∗1 In normal-speed playback, channel clock = 4.3218MHz.
– 16 –
CXD2589Q
Command bit
Processing
VCOSEL1
KSL3
KSL2
0
0
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/1
frequency-divided.
0
0
1
Multiplier PLL VCO1 is set to normal speed, and the output is 1/2
frequency-divided.
0
1
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/4
frequency-divided.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Multiplier PLL VCO1 is set to normal speed, and the output is 1/8
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/1
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/2
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/4
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/8
frequency-divided.
∗1 Approximately twice the normal speed.
Command bit
Processing
VCOSEL2
KSL1
KSL0
0
0
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/1
frequency-divided.
0
0
1
Wide-band PLL VCO2 is set to normal speed, and the output is 1/2
frequency-divided.
0
1
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/4
frequency-divided.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Wide-band PLL VCO2 is set to normal speed, and the output is 1/8
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/1
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/2
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/4
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/8
frequency-divided.
∗2 Approximately twice the normal speed.
– 17 –
– 18 –
C2PO
CDROM = 1
C2PO
CDROM = 0
LRCK
Timing Chart 1-1
C2 Pointer for lower 8bits
Rch C2 Pointer
C2 Pointer for upper 8bits
Rch 16bit C2 Pointer
C2 Pointer for lower 8bits
Lch C2 Pointer
C2 Pointer for upper 8bits
Lch 16bit C2 Pointer
If C2 Pointer = 1,
data is NG
CXD2589Q
CXD2589Q
∗ Data 2 D0 and subsequent data are DF/DAC function settings.
$9X commands (OPSL1= 0)
Data 1
Command
Function
specification
D3
D2
D1
0
DSPB
ON/OFF
0
Data 2
D0 D3 to D1 D0
0
Data 4
Data 3
000 SYCOF
D3
D2
D1
D0
0
MCSL
0
0
D3
ZDPL ZMUT
OPSL1
Function
specification
Data 1
D3
D2
D1
0
DSPB
ON/OFF
0
D1
D0
—
—
Data 5
D3
D2
D1
D0
—
—
—
—
∗ Data 2 D0 and subsequent data are DF/DAC function settings.
$9X commands (OPSL1= 1)
Command
D2
Data 3
Data 2
D0 D3 to D1 D0
0
000 SYCOF
Data 4
D3
D2
D1
D0
1
MCSL
0
0
D3
D2
ZDPL ZMUT
OPSL1
DSPB = 1
Double-speed playback (CD-DSP block)
DSPB = 0
Normal-speed playback (CD-DSP block)
SYCOF = 1
LRCK asynchronous mode
SYCOF = 0
Normal operation
D1
D0
0
DCOF
0
0
Processing
OPSL1 = 1
DCOF can be set.
OPSL1 = 0
DCOF cannot be set.
Command bit
Processing
MCSL = 1
DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz)
MCSL = 0
DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz)
– 19 –
0
D2
∗ Set SYCOF = 0 in advance when setting the $AX command LRWO to 1.
Command bit
0
D3
Processing
Command bit
D0
Data 5
Processing
Command bit
D1
CXD2589Q
Processing
Command bit
ZDPL = 1
LMUT and RMUT pins are high when muted.
ZDPL = 0
LMUT and RMUT pins are low when muted.
∗ See "Mute flag output" for the mute flag output conditions.
Processing
Command bit
ZMUT = 1
Zero detection mute is on.
ZMUT = 0
Zero detection mute is off.
Processing
Command bit
DCOF = 1
DC offset is off.
DCOF = 0
DC offset is on.
∗ DCOF can be set when OPSL1 = 1.
∗ Set DC offset to off when zero detection mute is on.
∗ Data 2 and subsequent data are DF/DAC function settings.
$AX commands (OPSL2 = 0)
Command
Audio CTRL
Data 1
Data 3
Data 2
D3
D2
D1
D0
D3
D2
D1
0
0
Mute
ATT
0
0
0
D0
D3
EMPH SMUT
D2
0
OPSL2
Data 3
Data 4
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
∗ Data 2 and subsequent data are DF/DAC function settings.
$AX commands (OPSL2 = 1)
Command
Audio CTRL
Data 6
Data 5
Data 3
Data 2
Data 1
D3
D2
D1
D0
D3
D2
D1
0
0
Mute
ATT
0
0
1
D0
D3
EMPH SMUT
D2
0
OPSL2
Data 3
Data 4
Data 6
Data 5
D1
D0
D3
D2
D1
D0
D3
D2
D1
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
– 20 –
D0
D3
D2
D1
D0
AD0 FMUT LRWO BSBST BBSL
CXD2589Q
Processing
Command bit
Mute = 1
CD-DSP block mute is on. 0 data is output from the CD-DSP block.
Mute = 0
CD-DSP block mute is off.
Processing
Command bit
ATT = 1
CD-DSP block output is attenuated (–12dB).
ATT = 0
CD-DSP block attenuation is off.
Meaning
Command bit
OPSL2 = 1
FMUT, LRWO, BSBST and BBSL can be set.
OPSL2 = 0
FMUT, LRWO, BSBST and BBSL cannot be set.
Processing
Command bit
EMPH = 1
De-emphasis is on.
EMPH = 0
De-emphasis is off.
∗ If either the EMPHI pin or EMPH is high, de-emphasis is on.
Processing
Command bit
SMUT = 1
Soft mute is on.
SMUT = 0
Soft mute is off.
∗ If either the SMUT pin or SMUT is high, soft mute is on.
Meaning
Command bit
AD9 to 0
Attenuation data.
The attenuation data consists of 10 bits, and is set as follows.
Attenuation data
Audio output
3FFh
0dB
3FEh
3FDh
:
001h
–0.0085dB
–0.017dB
The attenuation data (AD9 to AD0) consists of 10bits, and
can be set in 1023 different ways.
The audio output from 001h to 3FFh is obtained using the
following equation.
–60.198dB
Audio output = 20 log
000h
–∞
– 21 –
Attenuation data
1024
[dB]
CXD2589Q
Command bit
Meaning
FMUT = 1
Forced mute is on.
FMUT = 0
Forced mute is off.
∗ FMUT can be set when OPSL2 = 1.
Meaning
Command bit
LRWO = 1
Forced synchronization mode Note)
LRWO = 0
Normal operation.
∗ LRWO can be set when OPSL2 = 1.
Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need
to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1.
Processing
Command bit
BSBST = 1
Bass boost is on.
BSBST = 0
Bass boost is off.
∗ BSBST can be set when OPSL2 = 1.
Processing
Command bit
BBSL = 1
Bass boost is Max.
BBSL = 0
Bass boost is Mid.
∗ BBSL can be set when OPSL2 = 1.
– 22 –
1
0
0
0
1
1
– 23 –
1
0
1
0
1
0
1
0
0
L1
SPOB
L0
mode D
Peak meter
PER1
PER0
mode C
PER2
VF1
PER1
C
B
A
SubQ
D
SENS
L2
0
PER2
VF2
PER3
Peak meter
SubQ
mode
CPUSR
D1
VF0
SPOA
D2
SL0
SL0
PER0
SL1
D3
Data 1
mode B
mode A
SQCK
XLAT
1
1
0
1
0
0
1
0
0
1
SL1
SOCT
Serial bus
CTRL
Command
$BX commands
L3
WFCK
PER3
VF3
PER4
0
D0
D2
D1
D0
L4
SCOR
PER4
VF4
PER5
L5
GFS
PER5
VF5
PER6
L6
GTOP
PER6
VF6
PER7
L7
EMPH
PER7
VF7
C1F1
R0
FOK
0
ALOCK
C1F2
R1
LOCK
C1F1
C1F1
0
0
0
C2F2
R2
R3
RFCK XRAOF
C1F2
C1F2
C2F1
R4
C1F1
C2F1
C2F1
0
R5
C1F2
C2F2
C2F2
FOK
R6
C2F1
0
0
GFS
R7
C2F2
FOK
FOK
LOCK
The SQSO pin output can be switched to the various
signals by setting the SOCT command of $8X and the SL1
and SL0 commands of $BX. Set SQCK to high at the
falling edge of XLAT.
Except for Sub Q and peak meter, the signals are loaded
to the register when they are set at the falling edge of
XLAT. Sub Q is loaded to the register with each SCOR,
and Peak meter is loaded when a peak is detected.
TRM1 TRM0 MTSL1 MTSL0
D3
Data 2
GFS
GFS
LOCK
LOCK
EMPH ALOCK
EMPH
EMPH
VF0
VF1
VF2
VF3
VF4
VF5
VF6
VF7
CXD2589Q
CXD2589Q
Signal
Description
PER0 to 7
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
FOK
Focus OK
GFS
High when the frame sync and the insertion protection timing match.
LOCK
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
consecutive samples, a low signal is output.
EMPH
High when the playback disc has emphasis.
ALOCK
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
output. If GFS is low eight consecutive samples, a low signal is output.
VF0 to 7
Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.)
VF0 = LSB, VF7 = MSB.
SPOA, B
SPOA and B pin inputs.
WFCK
Write frame clock output.
SCOR
High when either subcode sync S0 or S1 is detected.
GTOP
High when the sync protection window is open.
RFCK
Read frame clock output.
XRAOF
Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.
L0 to L7,
R0 to R7
Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak
data. L0 and R0 are LSB.
C1F1
C1F2
0
0
1
1
C1 correction status
C2F1
C2F2
No Error
0
0
No Error
0
Single Error Correction
1
0
Single Error Correction
1
Irretrievable Error
1
1
Irretrievable Error
Processing
Command bit
CPUSR = 1
XLON pin is high.
CPUSR = 0
XLON pin is low.
– 24 –
C2 correction status
CXD2589Q
Peak meter
XLAT
SQCK
SQSO
L0
L1
L2
L3
L4
L5
L6
L7
R0
R1
R2
R3
R4
R5
R6
R7
(Peak meter)
Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively,
results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data
values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16
clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change
during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant
of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is
restarted 270µs to 400µs after SQCK input.
The peak register is reset with each readout (16 clocks input to SQCK).
The maximum value in peak detection mode is detected and held in this status until the next readout. When
switching to peak detection mode, readout should be performed one time initially to reset the peak detection
register.
Peak detection can also be performed for previous value hold and average value interpolation data.
Traverse monitor count value setting
These bits are set when monitoring the traverse condition of the SENS output according to the CNIN frequency
division.
Command bit
Processing
TRM1
TRM0
0
0
1/64 frequency division
0
1
1/128 frequency division
1
0
1/256 frequency division
1
1
1/512 frequency division
Monitor output switching
The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B.
Mode description
Pin No.
Command bit
47
48
49
50
MTSL1
MTSL0
0
0
XUGF
XPCK
GFS
C2PO
0
1
MNT1
MNT0
MNT3
C2PO
1
0
RFCK
XPCK
XROF
GTOP
– 25 –
CXD2589Q
$CX commands
Command
Servo coefficient setting
D3
D2
D1
D0
Gain
MDP1
Gain
MDP0
Gain
MDS1
Gain
MDS0
Gain
CLVS
CLV CTRL ($DX)
• CLV mode gain setting: GCLVS
Gain
MDS1
Gain
MDS0
Gain
CLVS
GCLVS
0
0
0
–12dB
0
0
1
–6dB
0
1
0
–6dB
0
1
1
0dB
1
0
0
0dB
1
0
1
+6dB
• CLVP mode gain setting: GMDP: GMDS
Gain
MDP1
Gain
MDP0
GMDP
Gain
MDS1
Gain
MDS0
GMDS
0
0
–6dB
0
0
–6dB
0
1
0dB
0
1
0dB
1
0
+6dB
1
0
+6dB
– 26 –
CXD2589Q
$DX commands
Command
CLV CTRL
Data 1
Data 3
Data 2
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
0
TB
TP
Gain
CLVS
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
See the $CX commands.
Command bit
Description
TB = 0
Bottom hold at a cycle of RFCK/32 in CLVS mode.
TB = 1
Bottom hold at a cycle of RFCK/16 in CLVS mode.
TP = 0
Peak hold at a cycle of RFCK/4 in CLVS mode.
TP = 1
Peak hold at a cycle of RFCK/2 in CLVS mode.
The rotational velocity R of the spindle can be
expressed with the following equation.
Command bit
Description
VP0 to 7 = F0 (H)
Playback at half (normal) speed
to
Playback at normal (double)
speed
:
VP0 to 7 = E0 (H)
R=
256 – n
32
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
Note) • Values in parentheses are for when DSPB is 1.
• Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.
• VP0 to 7 setting values are valid in CAV-W mode.
R – Relative velocity [multiple]
2
1.5
B=
1
P
DS
1
B=0
DSP
0.5
F0
VP0 to 7 setting value [HEX]
Fig. 1-1
– 27 –
E0
CXD2589Q
$EX commands
Data 1
Command
CLV mode
Data 2
D3
D2
D1
CM3
CM2
CM1
D0
D2
D3
Data 3
D1
D0
CM0 EPWM SPDC ICAP
Command bit
Mode
D3
SFSL VC2C
D2
D1
D0
HIFC LPWR VPON
Description
CM3
CM2
CM1
CM0
0
0
0
0
STOP
Spindle stop mode.∗1
1
0
0
0
KICK
Spindle forward rotation mode.∗1
1
0
1
0
BRAKE
1
1
1
0
CLVS
Rough servo mode. When the RF-PLL circuit isn't locked,
this mode is used to pull the disc rotations within the RFPLL capture range.
1
1
1
1
CLVP
PLL servo mode.
0
1
1
0
CLVA
Automatic CLVS/CLVP switching mode.
Used for normal playback.
Spindle reverse rotation mode. Valid only when LPWR = 0,
in any mode.∗1
∗1 See Timing Charts 1-2 to 1-6.
Command bit
EPWM SPDC
Mode
ICAP
SFSL
VC2C
HIFC
LPWR VPON
Description
0
0
0
0
0
0
0
0
CLV-N
Crystal reference CLV servo.
0
0
0
0
1
1
0
0
CLV-W
Used for normal-speed
playback in CLV-W mode.∗2
0
1
1
0
0
1
0
1
CAV-W
Spindle control with VP0 to 7.
1
0
1
0
0
1
0
1
CAV-W
Spindle control with the external
PWM.
∗2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.
– 28 –
CXD2589Q
Data 4
Command
SPD mode
D3
D2
Gain Gain
CAV1 CAV0
Gain
CAV1
Gain
CAV0
Gain
0
0
0dB
0
1
–6dB
1
0
–12dB
1
1
–18dB
Mode
CLV-N
LPWR
0
0
CLV-W
1
0
CAV-W
1
D1
D0
0
0
• This sets the gain when controlling the spindle with the phase comparator
in CAV-W mode.
Command
Timing chart
KICK
1-2 (a)
BRAKE
1-2 (b)
STOP
1-2 (c)
KICK
1-3 (a)
BRAKE
1-3 (b)
STOP
1-3 (c)
KICK
1-4 (a)
BRAKE
1-4 (b)
STOP
1-4 (c)
KICK
1-5 (a)
BRAKE
1-5 (b)
STOP
1-5 (c)
KICK
1-6 (a)
BRAKE
1-6 (b)
STOP
1-6 (c)
Mode
LPWR
Timing chart
CLV-N
0
1-7
0
1-8
1
1-9
0
1-10 (EPWM = 0)
1
1-11 (EPWM = 0)
0
1-12 (EPWM = 1)
1
1-13 (EPWM = 1)
CLV-W
CAV-W
– 29 –
CXD2589Q
Timing Chart 1-2
CLV-N mode LPWR = 0
KICK
BRAKE
Z
H
MDP
STOP
MDP
Z
MDP
L
(a) KICK
(b) BRAKE
Z
(c) STOP
Timing Chart 1-3
CLV-W mode (when following the spindle rotational velocity) LPWR = 0
KICK
MDP
BRAKE
STOP
Z
H
MDP
Z
(b) BRAKE
(a) KICK
Z
MDP
L
(c) STOP
Timing Chart 1-4
CLV-W mode (when following the spindle rotational velocity) LPWR = 1
KICK
BRAKE
H
MDP
Z
MDP
Z
(a) KICK
STOP
MDP
(b) BRAKE
Z
(c) STOP
Timing Chart 1-5
CAV-W mode LPWR = 0
KICK
BRAKE
STOP
H
MDP
MDP
(a) KICK
L
MDP
(b) BRAKE
Z
(c) STOP
Timing Chart 1-6
CAV-W mode LPWR = 1
KICK
MDP
H
(a) KICK
BRAKE
MDP
Z
(b) BRAKE
– 30 –
STOP
MDP
Z
(c) STOP
CXD2589Q
Timing Chart 1-7
CLV-N mode LPWR = 0
n · 236 (ns) n = 0 to 31
Acceleration
MDP
Z
132kHz
Deceleration
7.6µs
Timing Chart 1-8
CLV-W mode LPWR = 0
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Timing Chart 1-9
CLV-W mode LPWR = 1
Acceleration
MDP
Z
264kHz
3.8µs
The BRAKE pulse is masked when LPWR = 1.
Timing Chart 1-10
CAV-W mode EPWM = LPWR = 0
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Timing Chart 1-11
CAV-W mode EPWM = LPWR = 1
Acceleration
MDP
Z
264kHz
3.8µs
The BRAKE pulse is masked when LPWR = 1.
– 31 –
CXD2589Q
Timing Chart 1-12
CAV-W mode EPWM = 1, LPWR = 0
H
PWMI
L
Acceleration
H
MDP
L
Deceleration
Timing Chart 1-13
CAV-W mode EPWM = LPWR = 1
H
PWMI
L
Acceleration
H
MDP
Z
The BRAKE pulse is masked when LPWR = 1.
– 32 –
CXD2589Q
1-2. Description of SENS Output
The following signals are output from SENS, depending on the microcomputer serial register value (latching
not required).
Microcomputer serial
register value
(latching not required)
SENS
output
$0X, 1X, 2X, 3X
SEIN
SEIN, a signal input to this LSI from the SSP, is output.
$4X
XBUSY
Low while the auto sequencer is in operation, high when operation
terminates.
$5X
FOK
Outputs the signal input to the FOK pin. Normally, FOK (from RF) is
input. High for "focus OK".
$6X
SEIN
SEIN, a signal input to this LSI from the SSP, is output.
$AX
GFS
High when the regenerated frame sync is obtained with the correct timing.
$EX
OV64
Low when the EFM signal, after passing through the sync detection
filter, is lengthened by 64 channel clock pulses or more.
$7X, 8X, 9X, BX, DX, FX “L”
$CX
CNIN
division
Meaning
SENS pin is fixed to low.
Calculates the number of tracks from the frequency division ratio set
by $B.High when $C is latched; toggles each time CNIN is input the
number of times set in register B.
Note that the SENS output can be read out from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0.
(See the $BX commands.)
2. Subcode Interface
This section explains the subcode interface.
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2589Q.
Sub Q can be read out after checking the CRC of the 80bits in the subcode frame.
Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
2-1. P to W Subcode Readout
Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
2-2. 80-bit Sub Q Readout
Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC
check circuit.
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80bits are
loaded into the parallel/serial register.
When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the
CPU determines that new data (which passed the CRC check) has been loaded.
• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
• The retriggerable monostable multivibrator has a time constant from 270µs to 400µs. When the duration
when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this
interval, the serial/parallel register is not loaded into the parallel/serial register.
• While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others. (See Timing Chart 2-2.)
• The high and low intervals for SQCK should be between 750ns and 120µs.
– 33 –
CXD2589Q
Timing Chart 2-1
Internal
PLL clock
4.3218 ± ∆MHz
WFCK
SCOR
EXCK
400ns max
SBSO
S0 · S1
Q
R
WFCK
SCOR
EXCK
SBSO
S0·S1 Q R S T U V W S0·S1
Same
P1
Q R S T U V W
P1
Same
Sub Code P.Q.R.S.T.U.V.W Read Timing
– 34 –
P2
P3
SUBQ
SI
LD
H G F E D C B A
A B C D E F G H
SIN
Order
Inversion
– 35 –
CRCC
SUBQ
8
LD
(ASEC)
8
(AMIN)
80bit P/S Register
8
80bit S/P Register
Mono/Multi
LD
(AFRAM)
LD
SHIFT
8
8
8
8
LD
Mix
CRCF
8
SHIFT
SQSO
8
ADDRS CTRL
LD
Fig. 2-1. Block Diagram
SQCK
SO
CXD2589Q
LD
LD
– 36 –
SQSO
SQCK
CRCF
Mono/multi (Internal)
SQCK
SQSO
SCOR
WFCK
Timing Chart 2-2
CRCF1
1
2
Order
Inversion
ADR1
3
2
1
94
Determined by mode
93
92
91
ADR2
ADR3
CTL0
270µs to 400µs for SQCK = High
Registere load forbidder
80 Clock
750ns to 120µs
300ns max
ADR0
3
95
L
CTL1
96
CTL2
97
CTL3
CRCF2
98
CXD2589Q
CXD2589Q
Timing Chart 2-3
Measurement interval (approximately 3.8µs)
Reference window
(132.2kHz)
Measurement pulse
(VCKI/2)
Measurement counter
Load
m
VF0 to 7
The relative velocity R of the disc can be expressed with the following equation.
R=
m+1
32
(R: Relative velocity, m: Measurement results)
VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated
from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is
rotating at double speed (when DSPB is low).
– 37 –
CXD2589Q
3. Description of Modes
This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations
for each mode are described below.
3-1. CLV-N Mode
This mode is compatible with the CXD2507AQ, and operation is the same as for the conventional control.
The PLL capture range is ±150kHz.
3-2. CLV-W Mode
This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc.
This rotational following control has two types: using the built-in VCO2 or providing an external VCO. The
spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described
below. (When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the
output from the low-pass filter as the control voltage for the external VCO, and input the oscillation output
from the VCO to the VCKI pin.)
While starting to rotate a disc and/or speeding up to the lock range from the condition where the disc is
stopped, CAV-W mode should be used. This is because the capture range for CLV-W mode is wider than
the conventional lock range. Concretely, first send $E6650 to set CAV-W mode and kick the disc, then send
$E60C0 to set CLV-W mode when ALOCK is high. Playback is normally performed in CLV-W mode. The
microcomputer monitors the serial data output, and must return the operation to the speed adjusting state
(CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software is
shown in Fig. 3-2.
In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly
performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is
set to high, deceleration pulses are not output, thereby achieving low power consumption mode.
Note) The capture range for CLV-W mode has theoretically the range up to the signal processing limit.
3-3. CAV-W Mode
This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to variable
rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM.
When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E6650 command and controlling
VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low-speed to double-speed.
(See the $DX commands.) Also, when controlling the spindle with the external PWM, the PWMI pin is binary
input which becomes KICK during high intervals and BRAKE during low intervals.
The microcomputer can know the rotational velocity using V16M. The reference for the velocity
measurement is a signal of 132.2kHz obtained by 1/128-frequency dividing the crystal (384Fs). The velocity
is obtained by counting V16M/2 pulses while the reference is high, and the result is output from the new CPU
interface as 8bits (VF0 to 7). These measurement results are 31 when the disc is rotating at normal speed or
63 when it is rotating at double speed. These values match those of the 256-n for control with VP0 to 7.
In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire
system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other
output signals from this LSI change according to the rotational velocity of the disc (excluding DATO, CLKO
and XLTO).
Note) The capture range for this mode is theoretically up to the signal processing limit.
– 38 –
CXD2589Q
CAV-W
CLV-W
Operation mode
Rotational velocity
CLVS
CLVP
Spindle mode
Target velocity
KICK
Time
LOCK
ALOCK
Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode
CLV-W Mode
CLV-W MODE
START
KICK
$E8000
Mute OFF $A0XXXXX
CAV-W $E6650
(CLVA)
NO
ALOCK = H ?
YES
CLV-W $E60C0
(CLVA)
(WFCK PLL)
YES
ALOCK = L ?
NO
Fig. 3-2. CLV-W Mode Flow Chart
– 39 –
CXD2589Q
4. Description of Other Functions
4-1. Channel Clock Regeneration by the Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a
result, T, that is the channel clock, is necessary.
In an actual player, the PLL is necessary to regenerate the channel clock because the fluctuation in the
spindle rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 4-1.
The CXD2589Q has a built-in three-stage PLL.
• The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is
necessary; when not using the internal VCO2, external LPF and VCO are required.
The output of this first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition
to the conventional secondary loop.
– 40 –
CXD2589Q
Block Diagram 4-1
CLV-W
CAV-W
Spindle rotation information
1/32
XTSL
1/2
1/n
Phase comparator
1/2
Selector
OSC
VPCO
CLV-N
CLV-W
CAV-W /CLV-N
Microcomputer
control
n = 1 to 256
(VP7 to 0)
1/K
(KSL1, 0)
LPF
VCOSEL2
VCTL
VCO2
V16M
2/1 MUX
VCKI
VPON
1/M
1/N
Phase comparator
X'tal
PCO
FILI
FILO
1/K
(KSL3, 2)
CLTV
VCO1
VCOSEL1
Digital PLL
RFPLL
CXD2589Q
– 41 –
CXD2589Q
4-2. Frame Sync Protection
• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is
used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be
recognized, the data is processed as error data because the data cannot be recognized. As a result,
recognizing the frame sync properly is extremely important for improving playability.
• In the CXD2589Q, window protection and forward protection/backward protection have been adopted for
frame sync protection. These functions achieve very powerful frame sync protection. There are two window
widths: one for cases where a rotational disturbance affects the player and the other for cases where there
is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the
backward protection counter to 3. Concretely, when the frame sync is being played back normally and then
cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot
be detected for 13 frames or more, the window opens to resynchronize the frame sync.
In addition, immediately after the window opens and the resynchronization is executed, if a proper frame
sync cannot be detected within 3 frames, the window opens immediately.
4-3. Error Correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the
code is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.
• The CXD2589Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to
achieve high playability.
• The correction status can be monitored externally.
See Table 4-1.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3
MNT1
MNT0
Description
0
0
0
No C1 errors
0
0
1
One C1 error corrected
0
1
1
C1 correction impossible
1
0
0
No C2 errors
1
0
1
One C2 error corrected
1
1
1
C2 correction impossible
Table 4-1.
– 42 –
CXD2589Q
Timing Chart 4-1
Normal-speed PB
t = Dependent on error
condition
MNT3
C1 correction
C2 correction
MNT1
MNT0
Strobe
Strobe
4-4. DA Interface
• The CXD2589Q DA interface is as described below.
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is
high, the data is for the left channel.
– 43 –
R0
1
2
3
– 44 –
PCMD
BCK
(4.23M)
LRCK
(88.2k)
R0
1
2
4
5
Lch MSB (15)
Lch MSB (15)
48bit slot Double-Speed Playback
PCMD
BCK
(2.12M)
LRCK
(44.1k)
48bit slot Normal-Speed Playback
Timing Chart 4-2
6
7
8
9
L14
10
L13
11
L12
12
L0
24
L11
L9
Rch MSB
L10
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2589Q
CXD2589Q
4-5. Digital Out
There are three Digital Out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for
home use, and the type 2 form 2 format for the manufacture of software.
The CXD2589Q supports type 2 form 1.
Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bit 0 to 3)
of the channel status.
Digital Out C bit
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0
0
From sub Q
0
ID0
16
1
0
ID1 COPY Emph
0
0
0
32
48
0
176
Bits 0 to 3...Sub Q control bits that matched twice with CRCOK
Bit 29..........1 when VPON is 1
Table 4-2.
4-6. Servo Auto Sequencer
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1-track jump, 2N-track jumps, and N-track move are
executed automatically.
SSP (servo signal processor LSI) is used in an exclusive manner during the auto sequence execution (when
XBUSY = low), so that commands from the CPU are not transferred to the SSP, but can be sent to the
CXD2589Q.
Connect the CPU, RF and SSP as shown in Fig. 4-2.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point. This is to prevent the transfer of erroneous data to the SSP when XBUSY changes
from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low).
– 45 –
CXD2589Q
(a) Auto Focus ($47)
Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-3. The auto focus starts
with focus search-up, and the pickup should be lowered beforehand (focus search-down). In addition, blind
E of register 5 is used to eliminate FZC chattering. In other words, the focus servo is turned on at the falling
edge of FZC after FZC has been continuously high for a longer time than E.
Connection diagram for using auto sequencer (example)
RF
FOK
FOK
DATA
CXD2589Q
SSP
CLOK
Micro-computer
XLAT
C. out
CNIN
SENS
SEIN
DATA
DATO
CLK
CLKO
XLT
XLTO
SENS
Fig. 4-2.
Auto focus
Focus search up
FOK = H
NO
YES
(Checks whether FZC is continuously high
for the period of time E set with register 5)
FZC = H
NO
YES
FZC = L
NO
YES
Focus servo ON
END
Fig. 4-3-(a). Auto Focus Flow Chart
– 46 –
CXD2589Q
$47latch
XLT
FOK
SEIN (FZC)
BUSY
Command for SSP
Blind E
$08
$03
Fig. 4-3-(b). Auto Focus Timing Chart
(b) Track Jump
1, 10, and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled
servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not
involved in this sequence.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance
with Fig. 4-4. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in
accordance with Fig. 4-5. The principal difference from the 1-track jump is to kick the sled. In addition, after
kicking the actuator, when 5 tracks have been counted through CNIN, the brake is applied to the actuator.
Then, when the actuator speed is found to have slowed up enough (determined by the CNIN cycle
becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in
accordance with Fig. 4-6. The track jump count N is set with register 7. Although N can be set to 216 tracks,
note that the setting is actually limited by the actuator. CNIN is used for counting the number of jumps.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
• N-track move
When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in
accordance with Fig. 4-7. N can be set to 216 tracks. CNIN is used for counting the number of jumps. This
N-track move is executed only by moving the sled, and is therefore suited for moving across several
thousand to several ten-thousand tracks.
– 47 –
CXD2589Q
Track
Track FWD kick
sled servo OFF
(REV kick for REV jump)
WAIT
(Blind A)
CNIN =
NO
YES
Track REV
kick
(FWD kick for REV jump)
WAIT
(Brake B)
Track, sled
servo ON
END
Fig. 4-4-(a). 1-Track Jump Flow Chart
$48 (REV = $49) latch
XLT
CNIN
BUSY
Brake B
Blind A
Command for SSP
$28 ($2C)
$2C ($28)
Fig. 4-4-(b). 1-Track Jump Timing Chart
– 48 –
$25
CXD2589Q
10 Track
Track, sled
FWD kick
WAIT
(Blind A)
CNIN = 5 ?
(Counts CNIN × 5)
NO
YES
Track, REV
kick
C = Overflow ?
NO
(Checks whether the CNIN cycle
is longer than overflow C)
YES
Track, sled
servo ON
END
Fig. 4-5-(a). 10-Track Jump Flow Chart
$4A (REV = $4B) latch
XLT
CNIN
BUSY
Blind A
CNIN 5 count
Overflow C
Command for SSP
$2E ($2B)
$2A ($2F)
Fig. 4-5-(b). 10-Track Jump Timing Chart
– 49 –
$25
CXD2589Q
2N Track
Track, sled
FWD kick
WAIT
(Blind A)
CNIN = N
NO
YES
Track REV
kick
C = Overflow
NO
YES
Track servo
ON
WAIT
(Kick D)
Sled servo
ON
END
Fig. 4-6-(a). 2N-Track Jump Flow Chart
$4C (REV = $4D) latch
XLT
CNIN
BUSY
CNIN
N count
Blind A
Command for SSP
$2A ($2F)
Overflow
$2E ($2B)
$26 ($27)
Fig. 4-6-(b). 2N-Track Jump Timing Chart
– 50 –
Kick D
$25
CXD2589Q
N Track move
Track servo OFF
Sled FWD kick
WAIT
(Blind A)
CNIN = N
NO
YES
Track, sled
servo OFF
END
END
Fig. 4-7-(a). N-Track Move Flow Chart
$4E (REV = $4F) latch
XLT
CNIN
BUSY
Blind A
Command for SSP
CNIN N count
$20
$22 ($23)
Fig. 4-7-(b). N-Track Move Timing Chart
– 51 –
CXD2589Q
4-7. Digital CLV
Fig. 4-8 shows the Block Diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the
signal sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other
modes.
In addition, the digital spindle servo gain is variable.
Digital CLV
CLVS U/D
MDS Error
MDP Error
Measure
Measure
Over Sampling
Filter-1
2/1 MUX
CLV P/S
Gain
MDS
Gain
MDP
1/2
MUX
Over Sampling
Filter-2
CLV P/S
Noise Shape
Modulation
KICK, BRAKE, STOP
PWMI
LPWR
Mode Select
MDP
CLVS U/D:
MDS error:
MDP error:
PWMI:
Up/down signal from CLVS servo
Frequency error for CLVP servo
Phase error for CLVP servo
Spindle drive signal from the microcomputer for CAV servo
Fig. 4-8. Block Diagram
– 52 –
CXD2589Q
4-8. Asymmetry Compensation
CXD2589Q
ASYO
47
R1
RF
35
R1
R2
R1
ASYI
46
R1
36
BIAS
R1
2
=
R2
5
Fig. 4-9. Example of Asymmetry Compensation Application Circuit
– 53 –
CXD2589Q
5. 1bit DAC Block
5-1. DAC Block Input Timing
Timing Chart 5-1 shows the input timing for the DAC block.
Audio data is not transferred from the CD signal processer block to the DAC block inside the CXD2589Q.
This is to allow data to be sent to the DAC block via the audio DSP, etc.
When data is input to the DAC block without using the audio DSP, the data must be connected outside the
LSI. In this case, EMPH, LRCK, BCK and PCMD can be connected directly with EMPHI, LRCKI, BCKI and
PCMDI, respectively.
5-2. Description of DAC Block Functions
Zero data detection
When the condition where the lower 4bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued for approximately 300ms, zero data is detected. Zero data detection is performed
independently for the left and right channels.
Mute flag output
The LMUT and RMUT pins go active when any one of the following conditions is met.
The polarity can be selected by the ZDPL command of $9X.
• When zero data is detected
• When a high signal is input to the SYSM pin
• When the SMUT command of $AX is set
Attenuation operation
Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and
Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1
continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then
approaches Y3 from the value (B or C in the figure) at that point.
0dB
7F (H)
A
Y1
B
Y3
C
Y2
–∞
00 (H)
23.2 [ms]
– 54 –
CXD2589Q
DAC block mute operation
Soft mute
Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.
• When attenuation data of "000" (high) is set
• When the SMUT command of $AX is set to 1
• When a high signal is input to the SYSM input pin
Soft mute off
Soft mute on
Soft mute off
0dB
– ∞dB
23.2 [ms]
23.2 [ms]
Forced mute
Forced mute results when the FMUT command of $AX is set to 1.
Forced mute fixes the PWM output that is input to the LPF block to low.
∗ When setting FMUT, set OPSL2 to 1. (See the $AX commands.)
Zero detection mute
Forced mute is applied when the $9X command ZMUT is set to 1 and the zero data is detected for the left
and right channels.
(See "Zero data detection".)
– 55 –
1
– 56 –
PCMDI
BCKI
(4.23M)
LRCKI
(88.2k)
R0
1
2
2
3
Lch MSB (15)
Double-Speed Playback
PCMDI R0
BCKI
(2.12M)
LRCKI
(44.1k)
Normal-Speed Playback
Timing Chart 5-1
5
Lch MSB (15)
4
6
7
8
L14
10
L13
11
L12
12
L0
24
L11
Rch MSB
L10
Input Timing for DAC Block
9
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2589Q
CXD2589Q
LRCK Synchronization
Synchronization is performed at the first falling edge of the LRCK input during reset.
After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be
performed.
The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed
changes such as the following cases.
• When the XTSL pin switches between high and low
• When the DSPB command of $9X setting changes
• When the MCSL command of $9X setting changes
LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC
block. Resynchronization must be performed in this case as well.
For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set
LRWO to 0.
∗ When setting LRWO, set OPSL2 to 1. (See the $AX commands.)
SYCOF
When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback
can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1.
Normally, the memory proof, etc., is used for playback in CAV-W mode.
In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is
frequently lost.
Setting SYCOF of address 9 to 1 ignores that the LRCKI input synchronization is lost, facilitating playback.
However, the playback is not perfect because pre-value hold or data skip occurs due to the wow flutter in the
LRCKI input.
∗ Set SYCOF to 0 except when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI,
respectively, and performing playback in CAV-W mode.
∗ Set SYCOF to 0 in advance when LRCK resynchronization is applied with LRWO=1.
Digital Bass Boost
Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels:
Mid. and Max. BSBST and BBSL of address A are used for the setting.
See Graph 5-2 for the digital bass boost frequency response.
10.00
8.00
Normal
6.00
DBB MID
4.00
DBB MAX
2.00
[dB]
0.00
–2.00
–4.00
–6.00
–8.00
–10.00
–12.00
–14.00
10
30
100
300
1k
3k
Digital Bass Boost Frequency Response [Hz]
Graph 5-2.
– 57 –
10k
30k
CXD2589Q
6. LPF Block
The CXD2589Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an
operational amplifier with reference voltage.
The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly.
The reference voltage (VC) is (AVDD – AVSS)/2.
The LPF block application circuit is shown below.
In this circuit, the cut-off frequency is fc ≈ 40kHz.
The external capacitors' values when fc = 30kHz and 50 kHz are noted below as a reference.
The resistors' values do not change at this time.
• When fc ≈ 30kHz:
C1 = 200pF, C2 = 910pF
• When fc ≈ 50kHz:
C1 = 120pF, C2 = 560pF
LPF Block Application Circuit
12k
AOUT1 (2)
C2
680p
12k
AIN1 (2)
Vc
C1
150p
12k
Analog out
LOUT1 (2)
Fig. 6-1. LPF External Circuit
– 58 –
CXD2589Q
7. Setting Method of the CXD2589Q Playback Speed (in CLV-N mode)
(A) CD-DSP block
The playback modes shown below can be selected by the combination of the crystal, XTSL pin and
DSPB command of $9X.
CD-DSP block playback speed
X'tal
XTSL
DSPB
CD-DSP block playback speed
768Fs
1
0
1×
768Fs
1
1
2×
384Fs
0
0
1×
384Fs
0
1
384Fs
1
1
2×
1×∗1
Fs = 44.1kHz
∗1 Low power consumption mode. The CD-DSP processing speed is halved, allowing the power consumption
to be decreased.
(B) 1-bit DAC block
The operating speed of the DAC block is determined by the crystal and the MCSL command of $9X
regardless of the operating conditions of the CD-DSP block mentioned above. This allows the playback
mode for the DAC block and CD-DSP block to be set independently.
1-bit DAC block playback speed
X'tal
MCSL
DAC block playback speed
768Fs
1
1×
768Fs
0
2×
384Fs
0
1×
Fs = 44.1kHz
– 59 –
XPCK
BCK
BCKI
Vss
XUGF
GFS
DATO
C2PO
CNIN
XTSL
SEIN
DOUT
XLAT
C4M
CLOK
EMPHI
EMPH
WFCK
SBSO
RMUT
SCOR
SQCK
EXCK
RF 35
74 LOUT2
80 VDD
79 XRST
78 AVss
77 AVDD
2
Vss
1
76 AOUT2
75 AIN2
4
7
6
5
8
9
PCO 29
3
FILO 30
71 XTAO
72 XVss
LMUT
SSP
LS
DRIVER
RF
Application circuits shown are typical examples illustrating the operation of the
devices. Sony cannot assume responsibility for any problems arising out of the
use of these circuits or for any infringement of third party patent and other right
due to same.
10 11 12 13 14 15 16 17 18 19 20
MDP 21
PWMI 22
TEST 23
TES1 24
VPCO 25
VCKI 26
V16M 27
VCTL 28
FILI 31
70 XTAI
73 AVss
CLTV 33
AVss 32
SQSO
69 XVDD
SENS
FOK
SENS
XRST
DATA
XLAT
CLK
GFS
SQSO
SQCK
SCOR
MUTE
DATA
68 AVss
AVDD 34
67 LOUT1
66 AIN1
BIAS 36
CLKO
ASYI 37
SPOB
65 AOUT1
XLON
ASYO 38
FOK
63 AVss
LRCKI 40
LRCK 39
PCMD
64 AVDD
XLTO
61 VDD
VDD
Vss
62 SYSM
PCMDI
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VDD
SPOA
VDD
Vss
– 60 –
Vss
Application Circuit
CXD2589Q
CXD2589Q
Package Outline
Unit: mm
80PIN QFP (PLASTIC)
+ 0.35
1.5 – 0.15
+ 0.1
0.127 – 0.05
16.0 ± 0.4
+ 0.4
14.0 – 0.1
60
0.1
41
40
80
21
(15.0)
61
+ 0.15
0.3 – 0.1
20
± 0.12 M
0° to 10°
0.5 ± 0.2
1
0.65
+ 0.15
0.1 – 0.1
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-80P-L03
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
LQFP080-P-1414
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.6g
JEDEC CODE
– 61 –