CXG1081TN Receiving Dual-Band Mixer Description The CXG1081TN is a receiving dual-band mixer MMIC. This IC is designed using the Sony's GaAs JFET process. 16 pin TSSOP (Plastic) Features • High conversion gain Gc = 9.5 to 10.0dB (Typ.) • Low noise figure NF = 4.6 to 4.7dB (Typ.) • Single 2.7V power supply operation • Low LO input power operation PLO = –15dBm • Single CTL pin achieved by the built-in inverter circuit • 10-pin small package Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 4.5 V • Input power PIN +5 dBm • Current consumption IDD (Mixer block) 15 mA • Operating temperature Topr –35 to +85 °C • Storage temperature Tstg –65 to +150 °C Applications 800MHz Japan digital cellular telephones (PDC) Structure GaAs J-FET MMIC Recommended Operating Conditions • Supply voltage VDD 2.7 to 3.3 • Control voltage Block Diagram RFIN1 6 IF OUT 10 VCTL (H) VCTL (L) 2.4 to 3.3 0 to 0.3 V V V Pin Configuration RFIN1 6 5 RFIN2 CTL 7 4 OPT GND 8 3 GND VDD1 (LO AMP1) 9 2 VDD2 (LO AMP2) IF OUT/VDD3 (MIX) 10 1 LO IN 5 RFIN2 1 LO IN Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E99654A9Z-PS CXG1081TN Electrical Characteristics Conditions: VDD = 2.7V, VCTL (H) = 2.7V, VCTL (L) = 0V, fRF1 = 870MHz, fRF2 = 820MHz, fLO = fRF – 130MHz, PLO = –15dBm, unless otherwise specified (Ta = 25°C) Item Current consumption Control current Symbol IDD ICTL Min. Typ. Max. Unit — 5.7 7.3 mA H — 35 70 L –1 0 — H 8 9.5 11.5 L — –17 –12 H — –19 –14 L 8 10 11.5 RFIN1 → IFOUT H — 4.6 6.5 RFIN2 → IFOUT L — 4.7 6.5 RFIN1 → IFOUT H 0 –2.5 — RFIN2 → IFOUT L 0.5 3 — LOIN → RFIN1 H — –29 –23 LOIN → RFIN2 L — –29 –23 Path VCTL VDD1, VDD2 VDD3 → GND H CTL → GND CTL → GND RFIN1 → IFOUT Conversion gain GC RFIN2 → IFOUT Noise figure Input IP3 LO to RF leak level NF L IIP3 PLK Measurement condition When no signal µA dB When a small signal dB PRF = –25dBm, offset = 100kHz dBm Conversion by the IM3 suppression ratio for two-wave input dBm fLO = 740MHz fLO = 690MHz Note) The values shown above are the specified values on the Sony's recommended evaluation board. –2– CXG1081TN Recommended Evaluation Circuit RFIN1 L7 L6 L9 6 50Ω L10 RFIN2 5 L8 L11 50Ω R1 7 4 8 3 9 2 CTL L4 VDD1 (LO AMP1) C5 L5 C4 IF OUT C6 L1 L3 10 50Ω C2 L2 VDD2 (LO AMP2) C7 LO IN 1 50Ω C1 C3 VDD3 (MIX) L1 120nH L11 15nH L2 82nH C1 6pF L3 27nH C2 1000pF L4 33nH C3 1000pF L5 39nH C4 100pF L6 27nH C5 1000pF L7 15nH C6 100pF L8 18nH C7 1000pF L9 33nH R1 470Ω L10 8.2nH –3– CXG1081TN Example of Representative Characteristics (Ta = 25°C) Path RFIN1 → IFOUT GC, NF vs. fRF Path RFIN2 → IFOUT GC, NF vs. fRF 10 12 Gc – Conversion gain, NF – Noise figure [dB] Gc – Conversion gain, NF – Noise figure [dB] 12 VDD = 2.7V VCTL = 2.7V fLO = fRF – 130MHz PLO = –15dBm GC 8 6 NF 4 2 800 820 860 840 880 10 GC 8 6 NF 4 2 800 900 820 fRF – RF frequency [MHz] 10 10 0 POUT –10 –20 –30 –40 IM3 VDD = 2.7V VCTL = 2.7V fRF1 = 870MHz fRF2 = 870.1MHz fLO = 740MHz PLO = –15dBm –50 –60 –70 –10 0 10 PIN – RF input power [dBm] POUT – IF output power [dBm] POUT – IF output power [dBm] 20 –20 860 880 900 Path RFIN2 → IFOUT POUT , IM3 vs. PIN 20 –30 840 fRF – RF frequency [MHz] Path RFIN1 → IFOUT POUT, IM3 vs. PIN –80 –40 VDD = 2.7V VCTL = 0V fLO = fRF – 130MHz PLO = –15dBm 0 POUT –10 –20 –30 –40 IM3 VDD = 2.7V VCTL = 0V fRF1 = 820MHz fRF2 = 820.1MHz fLO = 690MHz PLO = –15dBm –50 –60 –70 –80 –40 –30 –20 –10 0 PIN – RF input power [dBm] –4– 10 CXG1081TN Path RFIN1 → IFOUT GC, NF vs. PLO Path RFIN2 → IFOUT GC, NF vs. PLO GC 10 VDD = 2.7V VCTL = 2.7V fRF1 = 870MHz fLO = 740MHz 8 6 NF 4 –20 –15 –10 –5 VDD = 2.7V VCTL = 0V fRF2 = 820MHz fLO = 690MHz 8 6 NF 4 –20 –15 –10 –5 PLO – LO input power [dBm] PLO – LO input power [dBm] Path RFIN1 → IFOUT IIP3, PLK vs. PLO Path RFIN2 → IFOUT IIP3, PLK vs. PLO 8 VDD = 2.7V VCTL = 2.7V fRF1 = 870MHz fRF2 = 870.1MHz fLO = 740MHz PLO = –15dBm 7 IP3 – Input IIP3 [dBm] 10 2 –25 0 6 PLK –22.5 8 –25 7 –27.5 5 –30 4 –32.5 –35 3 IIP3 IP3 – Input IIP3 [dBm] 2 –25 GC 0 –22.5 VDD = 2.7V VCTL = 0V fRF1 = 820MHz fRF2 = 820.1MHz fLO = 690MHz PLO = –15dBm 6 –25 –27.5 PLK 5 –30 4 –32.5 3 –35 IIP3 2 1 –25 –20 –15 –10 –5 0 –37.5 2 –40 1 –25 PLO – LO input power [dBm] –37.5 –20 –15 –10 –5 PLO – LO input power [dBm] –5– –40 0 PLK – LO leak power [dBm] Gc – Conversion gain, NF – Noise figure [dB] 12 PLK – LO leak power [dBm] Gc – Conversion gain, NF – Noise figure [dB] 12 CXG1081TN Example of Characteristics for Option Resistance R1 Changed (Ta = 25°C) IDD3 (MIX) vs. R1 IDD3 – Mixer block current consumption [mA] 10 VDD = 2.7V VCTL = 2.7V or VCTL = 0V 8 6 4 2 0 OPEN 1500 820 680 560 470 270 150 R1 – Option resistance [Ω] Path RFIN1 → IFOUT GC, NF vs. R1 Path RFIN2 → IFOUT GC, NF vs. R1 GC VDD = 2.7V VCTL = 2.7V fRF = 870MHz fLO = 740MHz PLO = –15dBm 8 6 NF 4 820 680 560 470 270 6 NF 4 2 OPEN 1500 150 820 680 560 470 R1 – Option resistance [Ω] Path RFIN1 → IFOUT IIP3, PLK vs. R1 Path RFIN2 → IFOUT IIP3, PLK vs. R1 –20 –24 –28 4 PLK –32 2 IIP3 –36 0 820 680 560 470 270 270 8 6 IP3 – Input IIP3 [dBm] VDD = 2.7V VCTL = 2.7V fRF = 870MHz fLO = 740MHz PLO = –15dBm –2 OPEN 1500 VDD = 2.7V VCTL = 0V fRF = 820MHz fLO = 690MHz PLO = –15dBm 8 R1 – Option resistance [Ω] 8 6 GC 10 –20 VDD = 2.7V VCTL = 0V fRF = 820MHz fLO = 690MHz PLO = –15dBm R1 – Option resistance [Ω] –24 PLK 4 IIP3 –32 0 –36 820 680 560 470 R1 – Option resistance [Ω] –6– –28 2 –2 OPEN 1500 –40 150 150 270 –40 150 PLK – LO leak power [dBm] 10 2 OPEN 1500 IP3 – Input IIP3 [dBm] Gc – Conversion gain, NF – Noise figure [dB] 12 PLK – LO leak power [dBm] Gc – Conversion gain, NF – Noise figure [dB] 12 CXG1081TN Recommended Evaluation Board 25mm Front SONY CXG1081TN EVB RFIN1 RFIN2 L7 L10 L8 L11 L9 L6 R1 L5 C6 C7 C5C4 L4 25mm C1 L3 L1 C3 L2 C2 IFOUT LOIN CTL VDD3 GND VDD1/2 Back VDD1/2 GND VDD3 CTL Glass fabric-base 4-layer epoxy board (thickness: 0.2mm × 2), total thickness: 0.8mm GND for the whole 2nd and 3rd layers –7– CXG1081TN Package Outline Unit: mm 10PIN TSSOP(PLASTIC) 1.2MAX ∗2.8 ± 0.1 0.1 10 + 0.15 0.1 – 0.05 0.45 ± 0.15 3.2 ± 0.2 ∗2.2 ± 0.1 6 5 1 0.5 0.22 0.1 0.25 0° to 10° M (0.1) + 0.025 0.12 – 0.015 A (0.2) + 0.08 0.22 – 0.07 DETAIL A NOTE: “∗” Dimensions do not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING EIAJ CODE LEAD MATERIAL COPPER ALLOY JEDEC CODE PACKAGE MASS 0.02g SONY CODE TSSOP-10P-L01 –8–