ICX069AL Diagonal 4.5mm (Type 1/4) CCD Image Sensor for CCIR B/W Video Cameras Description The ICX069AL is an interline CCD solid-state image sensor suitable for CCIR black-and-white video cameras. High sensitivity and low dark current are achieved through the adoption of HAD (HoleAccumulation Diode) sensors. This chip features a field period readout system and an electronic shutter with variable charge-storage time. The package is a 10mm-square 14-pin DIP (Plastic). 14 pin DIP (Plastic) AAAAA AAAAA AAAAA AAAAA AAAAA Pin 1 Features • High resolution, high sensitivity and low dark current • Horizontal register: 3.6 to 5.0V drive • No voltage adjustment (Reset gate and substrate bias are not adjusted.) • Low smear • Continuous variable-speed shutter Device Structure • Interline CCD image sensor • Image size: • Number of effective pixels: • Total number of pixels: • Chip size: • Unit cell size: • Optical black: • Number of dummy bits: • Substrate material: 2 V 3 Pin 8 H 12 40 Optical black position (Top View) Diagonal 4.5mm (Type 1/4) 752 (H) × 582 (V) approx. 440K pixels 795 (H) × 596 (V) approx. 470K pixels 4.47mm (H) × 3.80mm (V) 4.85µm (H) × 4.65µm (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels Horizontal 22 Vertical 1 (even fields only) Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96503D99 ICX069AL GND NC Vφ1 Vφ2 Vφ3 Vφ4 7 6 5 4 3 2 1 Vertical Register VOUT Block Diagram and Pin Configuration (Top View) Note) Horizontal Register Pin No. Symbol VL 13 14 Hφ2 φSUB Description 12 Hφ1 11 RG 10 GND Pin Description 9 VDD Note) 8 Pin No. : Photo sensor Description Symbol 1 Vφ4 Vertical register transfer clock 8 VDD Supply voltage 2 Vφ3 Vertical register transfer clock 9 GND GND 3 Vφ2 Vertical register transfer clock 10 φSUB Substrate clock 4 Vφ1 Vertical register transfer clock 11 VL Protective transistor bias 5 NC 12 RG Reset gate clock 6 GND GND 13 Hφ1 Horizontal register transfer clock 7 VOUT Signal output 14 Hφ2 Horizontal register transfer clock Absolute Maximum Ratings Item Ratings Unit –0.3 to +40 V VDD, VOUT – GND –0.3 to +18 V VDD, VOUT – φSUB –30 to +9 V Vφ1, Vφ2, Vφ3, Vφ4 – GND –15 to +16 V to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +16 V Hφ1, Hφ2 – Vφ4 –16 to +16 V Hφ1, Hφ2 – GND –10 to +15 V Hφ1, Hφ2 – φSUB –55 to +10 V VL – φSUB –65 to +0.3 V Vφ1, Vφ3, VDD, VOUT – VL –0.3 to +27.5 V RG – GND –0.3 to +20.5 V Vφ2, Vφ4, Hφ1, Hφ2, GND – VL –0.3 to +17.5 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C Substrate clock φSUB – GND Supply voltage Clock input voltage Vφ1, Vφ2, Vφ3, Vφ4 – φSUB ∗1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –2– Remarks ∗1 ICX069AL Bias Conditions Item Symbol Supply voltage VDD Protective transistor bias VL Substrate clock φSUB Min. Typ. Max. Unit 14.55 15.0 ∗1 15.45 V Remarks ∗2 ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. DC Characteristics Symbol Item Supply current Min. IDD Typ. Max. Unit 6 8 mA Remarks Clock Voltage Conditions Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Min. Typ. Max. Unit Waveform diagram VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –8.0 –7.5 –7.0 V 2 VVL = (VVL3 + VVL4)/2 VφV 6.8 7.5 8.05 V 2 VφV = VVHn – VVLn (n = 1 to 4) Symbol VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.3 V 2 High-level coupling VVHL 0.3 V 2 High-level coupling VVLH 0.3 V 2 Low-level coupling VVLL 0.3 V 2 Low-level coupling VφH 3.3 5.0 5.25 V 3 VHL –0.05 0 0.05 V 3 4.5 5.0 5.5 V 4 Input through 0.01µF capacitance 0.8 V 4 Low-level coupling VDD + VDD + VDD + 0.3 0.6 0.9 V 4 21.5 V 5 VφRG Reset gate clock voltage Remarks VRGLH – VRGLL VRGH Substrate clock voltage VφSUB 22.5 –3– 23.5 ICX069AL Clock Equivalent Circuit Constant Item Symbol Min. Typ. Max. Unit CφV1, CφV3 680 pF CφV2, CφV4 470 pF CφV12, CφV34 220 pF CφV23, CφV41 220 pF CφV13 75 pF CφV24 75 pF Capacitance between horizontal transfer clock and GND CφH1, CφH2 33 pF Capacitance between horizontal transfer clocks CφHH 30 pF Capacitance between reset gate clock and GND CφRG 5 pF Capacitance between substrate clock and GND CφSUB 170 pF Vertical transfer clock series resistor R1, R2, R3, R4 82 Ω Vertical transfer clock ground resistor RGND 15 Ω Horizontal transfer clock series resistor RφH 39 Ω Reset gate clock series resistor RφRG 39 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vφ1 Remarks Vφ2 CφV12 R1 R2 RφH RφH Hφ1 CφV1 CφV41 CφV23 CφH1 CφH2 CφV13 CφV24 CφV4 R4 Hφ2 CφHH CφV2 RGND CφV3 R3 CφV34 Vφ4 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit RφRG RGφ CφRG Reset gate clock equivalent circuit –4– ICX069AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II φM VVT φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVHH VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVH VVHH VVHH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVH2 VVHL VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) –5– VVL ICX069AL (3) Horizontal transfer clock waveform tr twh tf 90% twl VφH 10% VHL (4) Reset gate clock waveform tr twh tf VRGH twl Point A VφRG RG waveform VRGL + 0.5V VRGLH VRGL VRGLL Hφ1 waveform 2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VφRG = VRGH – VRGL (5) Substrate clock waveform 100% 90% φM VφSUB 10% VSUB 0% (A bias generated within the CCD) tr twh –6– φM 2 tf ICX069AL Clock Switching Characteristics Item Symbol VT Vertical transfer clock Vφ1, Vφ2, Vφ3, Vφ4 Horizontal transfer clock Readout clock During imaging twl twh tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 0.5 0.5 µs Hφ1 19 24 21 26 10 15 10 15 Hφ2 21 26 19 24 10 15 10 15 5.38 Reset gate clock φRG 11 Substrate clock φSUB 1.5 1.8 13 During readout 250 ns ∗1 15 During Hφ1 parallel-serial Hφ2 conversion Unit Remarks 0.01 0.01 5.38 0.01 0.01 51 3 3 0.5 ns ∗2 µs ns 0.5 µs During drain charge ∗1 When vertical transfer clock driver CXD1267AN is used. ∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be at least VφH/2 [V]. Item Horizontal transfer clock Symbol Hφ1, Hφ2 two Min. Typ. 16 20 Max. Unit Remarks ns ∗3 ∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. –7– ICX069AL Image Sensor Characteristics Item (Ta = 25°C) Symbol Min. Typ. Sensitivity S 220 280 Saturation signal Vsat 540 Smear Sm Video signal shading SH Max. Unit Measurement method mV 1 mV 2 % 3 20 % 4 Zone 0 and I 25 % 4 Zone 0 to II’ 0.009 0.015 Remarks Ta = 60°C Dark signal Vdt 2 mV 5 Ta = 60°C Dark signal shading ∆Vdt 1 mV 6 Ta = 60°C Flicker F 2 % 7 Lag Lag 0.5 % 8 Zone Definition of Video Signal Shading 752 (H) 12 12 8 H 8 V 10 H 8 Zone 0, I Zone II, II' V 10 582 (V) 6 Ignored region Effective pixel region –8– ICX069AL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [∗A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs × 250 50 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 × × × 100 [%] (1/10V method conversion value) 10 200 500 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax – Vmin)/200 × 100 [%] –9– ICX069AL 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula. F = (∆Vf/200) × 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) × 100 [%] FLD V1 Light Strobe light timing Signal output 200mV Output – 10 – Vlag (lag) RG Hφ1 Hφ2 XV4 XSG2 XV3 XSG1 XV1 XV2 XSUB 13 12 11 8 9 10 22/20V 14 7 15 16 5 6 17 4 CXD1267AN 18 3 22/16V 0.01 1/35 V 5 14 13 12 11 10 1/20V 100k 6 9 ICX069 (BOTTOM VIEW) 4 3 2 1 0.1 100k Hφ1 19 Vφ4 RG 2 Vφ3 VL 20 GND 7 VOUT 1 GND 15V Vφ1 Vφ2 Hφ2 NC φSUB – 11 – 8 VDD Drive Circuit 3.3/20V 0.01 2SK523 3.9k 100 2200p 3.3/16V 1M [∗A] CCD OUT –7.5V ICX069AL ICX069AL Spectral Sensitivity Characteristics (excludes both lens characteristics and light source characteristics) 1.0 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 800 900 1000 Wave Length [nm] Sensor Readout Clock Timing Chart V1 2.6 V2 Odd Field V3 V4 33.6 1.5 2.6 2.6 2.6 0.2 V1 V2 Even Field V3 V4 unit : µs – 12 – – 13 – CCD OUT V4 V3 V2 V1 HD BLK VD FLD 581 582 625 1 2 3 4 5 620 Drive Timing Chart (Vertical Sync) 15 24 6 1 3 5 2 4 6 1 3 5 315 582 581 330 1 3 5 2 4 6 335 1 3 5 2 4 6 ICX069AL 340 325 320 310 25 20 10 – 14 – SUB V4 V3 V2 V1 RG H2 H1 BLK HD 30 20 10 750 752 1 3 5 745 Drive Timing Chart (Horizontal Sync) ICX069AL 20 10 20 22 1 2 3 1 2 3 10 1 2 3 5 40 ICX069AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) AAAA AAAA AAAA AAAA AAAA AAAA Cover glass 50N 50N 1.2Nm Plastic package Compressive strength Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. – 15 – ICX069AL c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to the other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength are the same. Structure A Structure B AAA Package Chip Metal plate (lead frame) Cross section of lead frame The cross section of lead frame can be seen on the side of the package for structure A. – 16 – – 17 – 1.0 2.5 0.5 1.27 ~ ~ GOLD PLATING 42 ALLOY 0.6g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT M Plastic 0.3 7.0 8.9 10.0 ± 0.1 H PACKAGE MATERIAL 1 V 14 5.0 ~ 2.5 7 8 A 0.3 0.46 1.0 2.5 7.0 PACKAGE STRUCTURE B 5.0 B' C 1.7 7 8 1.7 1 14 9. The notch of the package is used only for directional index, that must not be used for reference of fixing. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 25µm. The tilt of the effective image area relative to the top “D” of the cover glass is less than 25µm. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm. The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1°. 4. The center of the effective image area relative to “B” and “B'” is (H, V) = (5.0, 5.0) ± 0.15mm. 3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference. 2. The two points “B” of the package are the horizontal reference. The point “B'” of the package is the vertical reference. 1. “A” is the center of the effective image area. D 14 pin DIP (400mil) 8.9 10.0 ± 0.1 2.6 10.16 Unit: mm 3.35 ± 0.15 1.27 3.5 ± 0.3 0° to 9° 0.25 Package Outline ICX069AL