ICX039DLB Diagonal 8mm (Type 1/2) CCD Image Sensor for CCIR Black-and-White Video Cameras Description The ICX039DLB is an interline CCD solid-state image sensor suitable for CCIR black-and-white video cameras with a diagonal 8mm (Type 1/2) system. Smear, sensitivity, D-range, S/N and other characteristics have been greatly improved compared with the ICX039BLB. High sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system and an electronic shutter with variable charge-storage time. Also, this outline is miniaturized by using original package. This chip is compatible with and can replace the ICX039BLB. 16 pin DIP (Ceramic) AAAAA AAAAA AAAAA AAAAA AAAAA Pin 1 2 V 12 Features 3 40 H • Low smear (–20dB compared with the ICX039BLB) Pin 9 • High sensitivity (+3.0dB compared with the ICX039BLB) Optical black position • High D range (+2.5dB compared with the ICX039BLB) (Top View) • High S/N • High resolution and low dark current • Excellent antiblooming characteristics • Continuous variable-speed shutter • Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V) • Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V) • Horizontal register: 5V drive • Maximum package dimensions: φ13.2mm Device Structure • Interline CCD image sensor • Image size: Diagonal 8mm (Type 1/2) • Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels • Total number of pixels: 795 (H) × 596 (V) approx. 470K pixels • Chip size: 7.95mm (H) × 6.45mm (V) • Unit cell size: 8.6µm (H) × 8.3µm (V) • Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction : Front 12 pixels, rear 2 pixels • Number of dummy bits: Horizontal 22 Vertical 1 (even fields only) • Substrate material: Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E96127B99 ICX039DLB VDD VL Vφ1 φSUB Vφ2 Vφ3 Vφ4 8 7 6 5 4 3 2 1 Vertical Register VOUT Block Diagram and Pin Configuration (Top View) Note) Horizontal Register 13 RD φRG 14 15 : Photo sensor 16 Hφ2 12 Hφ1 11 VDSUB 10 GND VGG 9 VSS Note) Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 Vφ4 Vertical register transfer clock 9 VGG Output circuit gate bias 2 Vφ3 Vertical register transfer clock 10 VSS Output circuit source 3 Vφ2 Vertical register transfer clock 11 GND GND 4 φSUB Substrate clock 12 RD Reset drain bias 5 Vφ1 Vertical register transfer clock 13 φRG Reset gate clock 6 VL Protective transistor bias 14 VDSUB Substrate bias circuit supply voltage 7 VDD Output circuit supply voltage 15 Hφ1 Horizontal register transfer clock 8 VOUT Signal output 16 Hφ2 Horizontal register transfer clock –2– ICX039DLB Absolute Maximum Ratings Item Ratings Unit –0.3 to +50 V VDD, VRD, VDSUB, VOUT, VSS – GND –0.3 to +18 V VDD, VRD, VDSUB, VOUT, VSS – φSUB –55 to +10 V Vφ1, Vφ2, Vφ3, Vφ4 – GND –15 to +20 V Vφ1, Vφ2, Vφ3, Vφ4 – φSUB to +10 V Voltage difference between vertical clock input pins to +15 V Voltage difference between horizontal clock input pins to +17 V Hφ1, Hφ2 – Vφ4 –17 to +17 V φRG, VGG – GND –10 to +15 V φRG, VGG – φSUB –55 to +10 V VL – φSUB –65 to +0.3 V Pins other than GND and φSUB – VL –0.3 to +30 V Storage temperature –30 to +80 °C Operating temperature –10 to +60 °C Substrate clock φSUB – GND Supply voltage Clock input voltage ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%. –3– Remarks ∗1 ICX039DLB Bias Conditions 1 [when used in substrate bias internal generation mode] Item Symbol Min. Typ. Max. Unit Output circuit supply voltage VDD 14.55 15.0 15.45 V Reset drain voltage VRD 14.55 15.0 15.45 V Output circuit gate voltage VGG 1.75 2.0 2.25 V Output circuit source VSS Grounded with 390Ω resistor Protective transistor bias VL ∗1 Substrate bias circuit supply voltage VDSUB Substrate clock φSUB 14.55 15.0 ∗2 15.45 Remarks VRD = VDD V ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. Bias Conditions 2 [when used in substrate bias external adjustment mode] Item Symbol Min. Typ. Max. Unit Remarks Output circuit supply voltage VDD 14.55 15.0 15.45 V Reset drain voltage VRD 14.55 15.0 15.45 V Output circuit gate voltage VGG 1.75 2.0 2.25 V Output circuit source VSS Protective transistor bias VL Substrate bias circuit supply voltage VDSUB Substrate voltage adjustment range VSUB 6.0 14.0 V ∗5 Substrate voltage adjustment precision ∆VSUB –3 +3 % ∗5 VRD = VDD Grounded with 390Ω resistor ∗3 ∗4 ∗3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗4 Connect to GND or leave open. ∗5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in substrate bias internal generation mode. VSUB code — one character indication Code and optimal setting correspond to each other as follows. VSUB code E f G h J K L m N P Q R S T U V W Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 <Example> "L" → VSUB = 9.0V DC Characteristics Item Output circuit supply current Symbol IDD Min. Typ. Max. Unit 5.0 10.0 mA –4– Remarks ICX039DLB Clock Voltage Conditions Symbol Item Readout clock voltage Vertical transfer clock voltage Horizontal transfer clock voltage Min. Typ. Max. Unit Remarks VVT 14.55 15.0 15.45 V 1 VVH1, VVH2 –0.05 0 0.05 V 2 VVH3, VVH4 –0.2 0 0.05 V 2 VVL1, VVL2, VVL3, VVL4 –9.6 –9.0 –8.5 V 2 VVL = (VVL3 + VVL4)/2 VφV 8.3 9.65 Vp-p 2 VφV = VVHn – VVLn (n = 1 to 4) 0.1 V 2 9.0 I VVH1 – VVH2 I VVH = (VVH1 + VVH2)/2 VVH3 – VVH –0.25 0.1 V 2 VVH4 – VVH –0.25 0.1 V 2 VVHH 0.5 V 2 High-level coupling VVHL 0.5 V 2 High-level coupling VVLH 0.5 V 2 Low-level coupling VVLL 0.5 V 2 Low-level coupling VφH 4.75 5.0 5.25 Vp-p 3 VHL –0.05 0 ∗1 0.05 V 3 V 4 5.0 5.5 Vp-p 4 0.8 4 VRGL Reset gate clock voltage∗1 Waveform diagram VφRG 4.5 VRGLH – VRGLL Substrate clock voltage VφSUB 23.0 24.0 V 25.0 Vp-p Low-level coupling 5 ∗1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications. Item Reset gate clock voltage Symbol Min. Typ. Max. Unit VRGL –0.2 0 VφRG 8.5 9.0 –5– 0.2 V 9.5 Vp-p Waveform diagram 4 4 Remarks ICX039DLB Clock Equivalent Circuit Constant Item Symbol Min. Typ. Max. Unit Remarks CφV1, CφV3 1800 pF CφV2, CφV4 2200 pF CφV12, CφV34 450 pF CφV23, CφV41 270 pF Capacitance between horizontal transfer clock and GND CφH1 64 pF CφH2 62 pF Capacitance between horizontal transfer clocks CφHH 47 pF Capacitance between reset gate clock and GND CφRG 8 pF Capacitance between substrate clock and GND CφSUB 400 pF Vertical transfer clock series resistor R1, R2, R3, R4 68 Ω Vertical transfer clock ground resistor RGND 15 Ω Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vφ1 Vφ2 CφV12 R1 R2 Hφ1 CφV1 Hφ2 CφHH CφV2 CφV41 CφV23 CφH1 CφH2 CφV4 RGND CφV3 R4 Vφ4 CφV34 R3 Vφ3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit –6– ICX039DLB Drive Clock Waveform Conditions (1) Readout clock waveform VVT 100% 90% II II φM φM 2 10% 0% tr twh 0V tf (2) Vertical transfer clock waveform Vφ1 Vφ3 VVHH VVH1 VVHH VVH VVHL VVHL VVH3 VVHL VVL1 VVH VVHH VVHH VVHL VVL3 VVLH VVLH VVLL VVLL VVL VVL Vφ2 Vφ4 VVHH VVHH VVH VVH VVHH VVHH VVHL VVH2 VVHL VVHL VVH4 VVL2 VVHL VVLH VVLH VVLL VVLL VVL VVL4 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VφV = VVHn – VVLn (n = 1 to 4) –7– VVL ICX039DLB (3) Horizontal transfer clock waveform tr twh tf 90% twl VφH 10% VHL (4) Reset gate clock waveform tr twh tf VRGH twl Point A VφRG RG waveform VRGL + 0.5V VRGLH VRGL VRGLL Hφ1 waveform +2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VφRG = VRGH – VRGL –8– ICX039DLB (5) Substrate clock waveform 100% 90% φM Vφ SUB 10% 0% VSUB tr twh φM 2 tf Clock Switching Characteristics Item Symbol VT Vertical transfer clock Vφ1, Vφ2, Vφ3, Vφ4 Horizontal transfer clock Readout clock During imaging twl twh tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 Hφ 0.5 20 During parallel- Hφ1 serial Hφ2 conversion 20 15 5.38 Reset gate clock φRG 11 Substrate clock φSUB 1.5 1.8 13 Horizontal transfer clock Symbol µs 15 250 ns ∗1 ns ∗2 19 15 0.01 0.01 5.38 0.01 0.01 51 3 3 0.5 Hφ1, Hφ2 two Min. Typ. 16 20 Max. 19 µs ns 0.5 Unit Remarks ns ∗3 ∗3 The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two. –9– During readout 0.5 ∗1 When vertical transfer clock driver CXD1267AN is used. ∗2 tf ≥ tr – 2ns. Item Unit Remarks µs During drain charge ICX039DLB Image Sensor Characteristics (Ta = 25°C) Symbol Min. Typ. Unit Measurement method Sensitivity S 500 600 mV 1 Saturation signal Vsat 720 mV 2 Smear Sm % 3 Video signal shading SH 20 % 4 Zone 0 and I 25 % 4 Zone 0 to II' Dark signal Vdt 2 mV 5 Ta = 60°C Dark signal shading ∆Vdt 1 mV 6 Ta = 60°C Flicker F 2 % 7 Lag Lag 0.5 % 8 Item Max. 0.00032 0.00056 Zone Definition of Video Signal Shading 752 (H) 12 12 8 H 8 V 10 H 8 Zone 0, I Zone II, II' V 10 582 (V) 6 Ignored region Effective pixel region – 10 – Remarks Ta = 60°C ICX039DLB Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (When used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.) 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [∗A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250 s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs × 250 50 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 × × × 100 [%] (1/10V method conversion value) 10 200 500 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax – Vmin)/200 × 100 [%] – 11 – ICX039DLB 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then substitute the value into the following formula. F = (∆Vf/200) × 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) × 100 [%] FLD V1 Light Strobe light timing Signal output 200mV Output – 12 – Vlag (lag) RG Hφ2 Hφ1 XV4 XSG2 XV3 XSG1 XV1 XV2 XSUB 22/20V 10 11 12 13 8 9 14 7 15 16 CXD1267AN 5 6 17 4 22/16V 0.01 1/35V 1 2 3 4 6 ICX039DLB 5 7 9 390 3.9k 100 180k VOUT 1/ 6.3V 47/6.3V 8 0.01 16 15 14 13 12 11 10 Vφ4 Hφ2 19 18 Vφ3 Hφ1 2 3 Vφ2 VDSUB 100k φSUB φRG 20 Vφ1 RD 1 GND 15V VL VDD Vss – 13 – VGG Drive Circuit 1 (substrate bias internal generation mode) 27k 3.3/20V 1 0.01 [∗A] CCD OUT 1M 3.3/16V –9V ICX039DLB RG Hφ2 Hφ1 XV4 XSG2 XV3 XSG1 XV1 XV2 XSUB 13 12 11 8 9 10 22/20V 14 7 15 16 CXD1267AN 5 6 17 4 22/16V 1/35V 1/35V 0.01 1/35V 1 2 3 100k 4 27k 7 6 ICX039DLB 5 0.1 8 390 3.9k 100 180k 0.01 39k 270k 1/ 6.3V 47/6.3V 16 15 14 13 12 11 10 9 Vφ4 Hφ2 19 18 Vφ2 VDSUB 2 3 Vφ3 Hφ1 0.1 56k φSUB φRG 20 Vφ1 RD 1 VL GND VOUT 15V VDD Vss – 14 – VGG Drive Circuit 2 (substrate bias external adjustment mode) 27k 3.3/20V 15k 0.1 47k 15k 0.01 [∗A] CCD OUT 1M 3.3/16V –9V ICX039DLB ICX039DLB Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 Relative Response 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 700 600 800 900 1000 Wave Length [nm] Sensor Readout Clock Timing Chart V1 2.5 V2 Odd Field V3 V4 1.5 33.6 2.6 2.5 2.5 0.2 V1 V2 Even Field V3 V4 unit : µs – 15 – – 16 – CCD OUT V4 V3 V2 V1 HD BLK VD FLD 581 582 625 1 2 3 4 5 620 Drive Timing Chart (Vertical Sync) 15 24 6 1 3 5 2 4 6 1 3 5 315 582 581 330 1 3 5 2 4 6 335 1 3 5 2 4 6 ICX039DLB 340 325 320 310 25 20 10 – 17 – SUB V4 V3 V2 V1 RG H2 H1 BLK HD 30 20 10 750 752 1 3 5 745 Drive Timing Chart (Horizontal Sync) ICX039DLB 20 10 20 22 1 2 3 1 2 3 10 1 2 3 5 40 ICX039DLB Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensors. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Operate in clean environments (around class 1000 is appropriate). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. 5) Exposure to high temperature or high humidity will affect the characteristics. Accordingly, avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical shocks. – 18 – – 19 – 1.5 ~ B' 1st. pin Index B φ1 0. 2 GOLD PLATING 42 ALLOY 0.9g LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT 1.5 ~ ~ 0.7 12.35 ± 0.3 12.0 ± 0.15 6.175 H Ceramic 1 V PACKAGE MATERIAL 1.27 0.6 3 16 ± 3. 1.84 PACKAGE STRUCTURE 1.84 1.5 8 9 6.175 0.3 1.0 A 0.3 12.35 ± 0.3 M C 8 9 ~ 7.62 0.25 4.0 ∗ Center of the package : The center is halfway between two pairs of opposite sides, as measured from “B”, “B'”. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 7. The tilt of the effective image area relative to the bottom “C” is less than 60µm. 6. The height from the bottom “C” to the effective image area is 1.41 ± 0.15mm. 5. The rotation angle of the effective image area relative to H and V is ± 1°. 4. The center of the effective image area relative to the center of the package (∗) is (H, V) = (0, 0) ± 0.15mm. 3. The bottom “C” of the package is the height reference. 2. The point “B” of the package is the horizontal reference. The point “B'” of the package is the vertical reference. 1 16 4.0 1. “A” is the center of the effective image area. 2.54 3.29 ± 0.3 16pin DIP (300mil) 12.0 ± 0.15 4.0 ± 0.2 Unit: mm ~ Package Outline ICX039DLB