ICX088AK
Diagonal 4.5mm (Type 1/4) CCD Image Sensor for NTSC Color Video Cameras
Description
The ICX088AK is an interline CCD solid-state
image sensor suitable for NTSC color digital video
cameras. This chip supports DV standard SD mode,
and can drive at 13.5MHz.
High sensitivity, wide dynamic range and low dark
current are achieved through the adoption of Super
HAD CCD technology. In addition, high resolution is
achieved through the adoption of Ye, Cy, Mg and G
complementary color mosaic filters.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
The package is a 14-pin DIP (Plastic), and both
top and bottom surface reference can be assured at
the same time.
14 pin DIP (Plastic)
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Pin 1
V
Features
• Supports DV standard SD mode (13.5MHz)
2
• High resolution, high sensitivity and wide dynamic range
40
H
Pin 8
• Low dark current and low smear
• Excellent antiblooming characteristics
Optical black position
• Supply voltage: 12V
(Top View)
• Horizontal register drive amplitude: 2.7 to 3.6V
• No voltage adjustment (Reset gate and substrate bias are not adjusted.)
• Continuous variable-speed shutter
• Recommended range of exit pupil distance: –20 to –100mm
• Ye, Cy, Mg and G complementary color mosaic filters on chip
• 14-pin high precision plastic package (both top and bottom surface reference possible)
Device Structure
• Interline CCD image sensor
• Image size:
• Total number of pixels:
• Total number of effective pixels:
• Chip size:
• Unit cell size:
• Optical black:
• Number of dummy bits:
• Substrate material:
2
12
Diagonal 4.5mm (Type 1/4)
766 (H) × 508 (V) approx. 390K pixels
724 (H) × 494 (V) approx. 360K pixels
4.60mm (H) × 3.97mm (V)
5.05µm (H) × 5.55µm (V)
Horizontal (H) direction: Front 2 pixels, rear 40 pixels
Vertical (V) direction:
Front 12 pixels, rear 2 pixels
Horizontal 20
Vertical 1 (even fields only)
Silicon
∗Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97707A99
ICX088AK
GND
VL
Vφ1
Vφ2
Vφ3
Vφ4
7
6
5
4
3
2
1
Vertical Register
VOUT
Block Diagram and Pin Configuration
(Top View)
Cy
Ye
Cy
Mg
G
Mg
Ye
G
Cy
Ye
Cy
Ye
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Note)
Horizontal Register
11
GND
φSUB
CSUB
Pin Description
Pin No. Symbol
Description
12
13
14
Hφ2
10
Hφ1
9
φRG
8
VDD
Note)
Pin No. Symbol
: Photo sensor
Description
1
Vφ4
Vertical register transfer clock
8
VDD
Supply voltage
2
Vφ3
Vertical register transfer clock
9
GND
GND
3
Vφ2
Vertical register transfer clock
10
φSUB
4
Vφ1
Vertical register transfer clock
11
CSUB
Substrate clock
Substrate bias ∗1
5
VL
Protective transistor bias
12
φRG
Reset gate clock
6
GND
GND
13
Hφ1
Horizontal register transfer clock
7
VOUT
Signal output
14
Hφ2
Horizontal register transfer clock
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
Absolute Maximum Ratings
Item
Ratings
Unit Remarks
VDD, VOUT, φRG – φSUB
–40 to +8
V
Vφ1, Vφ3 – φSUB
–50 to +15
V
Vφ2, Vφ4, VL – φSUB
–50 to +0.3
V
Hφ1, Hφ2, GND – φSUB
–40 to +0.3
V
–25 to
V
VDD, VOUT, φRG, CSUB – GND
–0.3 to +18
V
Vφ1, Vφ2, Vφ3, Vφ4 – GND
–10 to +18
V
Hφ1, Hφ2 – GND
–10 to +5
V
Vφ1, Vφ3 – VL
–0.3 to +28
V
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL
–0.3 to +15
V
to +15
V
–5 to +5
V
–13 to +13
V
Storage temperature
–30 to +80
°C
Operating temperature
–10 to +60
°C
Against φSUB
CSUB – φSUB
Against GND
Against VL
Voltage difference between vertical clock input pins
Between input clock
pins
Hφ1 – Hφ2
Hφ1, Hφ2 – Vφ4
∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
∗2
ICX088AK
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
11.64
12.0
∗1
12.36
V
Supply voltage
VDD
Protective transistor bias
VL
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
Remarks
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Symbol
Supply current
Min.
Typ.
IDD
Max.
Unit
5.0
Remarks
mA
Clock Voltage Conditions
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Min.
Typ.
Max.
Unit
Waveform
diagram
VVT
11.64
12.0
12.36
V
1
VVH1, VVH2
–0.05
0
0.05
V
2
VVH3, VVH4
–0.2
0
0.05
V
2
VVL1, VVL2,
VVL3, VVL4
–6.85
–6.5
–6.15
V
2
VVL = (VVL3 + VVL4)/2
VφV
5.95
6.5
6.9
V
2
VφV = VVHn – VVLn (n = 1 to 4)
VVH3 – VVH
–0.25
0.1
V
2
VVH4 – VVH
–0.25
0.1
V
2
VVHH
0.3
V
2
High-level coupling
VVHL
0.3
V
2
High-level coupling
VVLH
0.3
V
2
Low-level coupling
VVLL
0.3
V
2
Low-level coupling
Symbol
VVH = (VVH1 + VVH2)/2
VφH
2.7
3.3
3.6
V
3
VHL
–0.05
0
0.05
V
3
2.7
3.3
3.6
V
4
VRGLH – VRGLL
0.4
V
4
Low-level coupling
VRGL – VRGLm
0.5
V
4
Low-level coupling
19.3
V
5
VφRG
Reset gate clock
voltage
Remarks
Substrate clock voltage VφSUB
17.3
18.5
–3–
ICX088AK
Clock Equivalent Circuit Constant
Item
Symbol
Min.
Typ.
Max. Unit Remarks
CφV1, CφV3
680
pF
CφV2, CφV4
470
pF
CφV12, CφV34
330
pF
CφV23, CφV41
270
pF
CφV13
82
pF
CφV24
75
pF
Capacitance between horizontal transfer clock and GND
CφH1, CφH2
47
pF
Capacitance between horizontal transfer clocks
CφHH
47
pF
Capacitance between reset gate clock and GND
CφRG
5
pF
Capacitance between substrate clock and GND
CφSUB
180
pF
Vertical transfer clock series resistor
R1, R2, R3, R4
82
Ω
Vertical transfer clock ground resistor
RGND
15
Ω
Horizontal transfer clock series resistor
RφH
12
Ω
Horizontal transfer clock ground resistor
RH2
30
kΩ
Capacitance between vertical transfer clock and
GND
Capacitance between vertical transfer clocks
Vφ1
Vφ2
CφV12
R1
R2
RφH
RφH
Hφ1
CφV1
CφV41
CφV23
CφV4
Vφ4
CφH1
CφH2
RH2
CφV13
CφV24
R4
Hφ2
CφHH
CφV2
RGND CφV3
CφV34
R3
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
–4–
ICX088AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
II
II
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1
Vφ3
VVHH
VVH1
VVHH
VVH
VVHL
VVHL
VVH3
VVHL
VVL1
VVH
VVHH
VVHH
VVHL
VVL3
VVLH
VVLH
VVLL
VVLL
VVL
VVL
Vφ2
Vφ4
VVHH
VVHH
VVH
VVH
VVHH
VVHH
VVHL
VVH2 VVHL
VVHL
VVH4
VVL2
VVHL
VVLH
VVLH
VVLL
VVLL
VVL
VVL4
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
–5–
VVL
ICX088AK
(3) Horizontal transfer clock waveform
tr
twh
tf
Hφ2
90%
VCR
VφH
twl
VφH
2
10%
VHL
Hφ1
two
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr
twh
tf
VRGH
RG waveform
twl
VφRG
Point A
VRGLH
VRGLL
VRGLm
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL) /2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL.
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
φM
2
VφSUB
VSUB
(A bias generated within the CCD)
10%
0%
tr
twh
–6–
tf
ICX088AK
Clock Switching Characteristics
Item
Symbol
VT
Vertical transfer
clock
Vφ1, Vφ2,
Vφ3, Vφ4
Horizontal
transfer clock
Readout clock
During
imaging
twh
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
1.58 1.78
0.5
Unit Remarks
µs
0.5
During
readout
During
250 ns CXD1267AN
15
used
Hφ1
25
28
25
28
9
12
9
12
Hφ2
25
28
25
28
9
12
9
12
During
Hφ1
parallel-serial
conversion
Hφ2
5.36
Reset gate clock φRG
11
0.01
0.01
5.36
0.01
0.01
51
3
3
13
tf ≥ tr – 2ns
ns VφH = 2.7V
∗1
µs
ns
During
Substrate clock
φSUB
2.0 2.96
0.5
0.5
µs drain
charge
∗1 The cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be at least VφH/2 [V].
Item
two
Symbol
Horizontal transfer clock
Hφ1, Hφ2
Min.
Typ.
25
28
Max.
Unit
Remarks
ns
Spectral Sensitivity Characteristics (excludes both lens characteristics and light source characteristics)
1.0
Ye
0.8
Relative Response
Cy
G
0.6
0.4
Mg
0.2
0.0
400
450
500
550
Wave Length [nm]
–7–
600
650
700
ICX088AK
Image Sensor Characteristics
Item
(Ta = 25°C)
Symbol
Min.
Typ.
S
390
480
RMgG
0.93
1.35
2
RYeCy
1.15
1.48
2
Saturation signal
Ysat
800
Smear
Sm
Video signal shading
SHy
Sensitivity
Sensitivity ratio
Max.
Unit
Measurement method
mV
1
Remarks
mV
3
%
4
20
%
5
Zone 0 and I
25
%
5
Zone 0 to II'
∆Sr
10
%
6
∆Sb
10
%
6
Dark signal
Ydt
2
mV
7
Ta = 60°C
Dark signal shading
∆Ydt
1
mV
8
Ta = 60°C
Flicker Y
Fy
2
%
9
Flicker R-Y
Fcr
5
%
9
Flicker B-Y
Fcb
5
%
9
Line crawl R
Lcr
3
%
10
Line crawl G
Lcg
3
%
10
Line crawl B
Lcb
3
%
10
Line crawl W
Lcw
3
%
10
Lag
Lag
0.5
%
11
Uniformity between video
signal channels
0.009 0.015
Ta = 60°C
Zone Definition of Video Signal Shading
724 (H)
10
10
8
V
10
H
8
H
8
Zone 0, I
Zone II, II'
V
10
494 (V)
10
lgnored region
Effective pixel region
Measurement System
[∗Y]
Y signal output
[∗A]
CCD signal output
LPF1
(3dB down 6.3MHz)
CCD
C.D.S
AMP
SH
LPF2
S
H
[∗C]
Chroma signal output
(3dB down 1MHz)
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y], and between [∗A] and [∗C] equals 1.
–8–
ICX088AK
Image Sensor Characteristics Measurement Method
Measurement conditions
1)
In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions.
2)
In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal
output or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
Cy
Ye
Cy
Ye
G
Mg
G
Mg
Cy
Ye
Cy
Ye
G
Mg
A1
B
A2
Mg
G
As shown in the left figure, fields are read out. The charge is
mixed by pairs such as A1 and A2 in the A field. (pairs such
as B in the B field)
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
Hreg
Color Coding Diagram
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} x 1/2
= 1/2 {2B + 3G +2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} x 1/2
= 1/2 {2B + 3G +2R}
This is balanced since it is formed in the same way as for line A1.
In a like manner, the chroma (color difference) signal is approximated as follows:
–(B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and –(B – Y)
in alternation. This is also true for the B field.
–9–
ICX088AK
Definition of standard imaging conditions
1)
Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
2)
Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is
adjusted to the value indicated in each testing item by the lens diaphragm.
3)
Standard imaging condition III:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens (exit pupil distance –33mm) with CM500S (t = 1.0mm) as an IR cut filter. The
luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm.
1.
Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
S = Ys ×
2.
250
[mV]
60
Sensitivity ratio
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, and then measure the Mg signal output (SMg [mV]) and G signal output (SG
[mV]), and Ye signal output (SYe [mV]) and Cy signal output (SCy [mV]) at the center of the screen with
frame readout method. Substitute the values into the following formula.
RMgG = SMg/SG
RYeCy = SYe/SCy
3.
Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.
4.
Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
to 500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings,
measure the maximum value YSm [mV] of the Y signal output and substitute the value into the following
formula.
Sm =
5.
1
YSm
1
×
×
× 100 [%] (1/10V method conversion value)
10
200
500
Video signal shading
Set to standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
so that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.
SHy = (Ymax – Ymin)/200 × 100 [%]
6.
Uniformity between video signal channels
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin,
Cbmin [mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into
the following formula.
∆Sr = | (Crmax – Crmin)/200 | × 100 [%]
∆Sb = | (Cbmax – Cbmin)/200 | × 100 [%]
– 10 –
ICX088AK
7.
Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C
and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
8.
Dark signal shading
After measuring 7, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the Y
signal output and substitute the values into the following formula.
∆Ydt = Ydmax – Ydmin [mV]
9.
Flicker
1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]).
Then substitute the value into the following formula.
Fy = (∆Yf/200) × 100 [%]
2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, insert an R and B filter, and then measure both the difference in the signal level
between fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output
(CAr, CAb). Substitute the values into the following formula.
Fci = (∆Ci/CAi) × 100 [%] (i = r, b)
10. Line crawls
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y
signal output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following formula.
Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)
11. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the
following formula.
Lag = (Ylag/200) × 100 [%]
FLD
V1
Light
Strobe light
timing
Y signal output 200mV
Output
– 11 –
Ylag (lag)
7
8
9
10
XV3
XSG2
XV4
φRG
Hφ1
Hφ2
6
XV1
XSG1
5
XV2
CXD1267AN
3
11
12
13
14
15
16
17
18
2
4
19
22/16V
1/35V
8
14 13 12 11 10 9
0.1
5
4
0.1
2200p
ICX088
(BOTTOM VIEW)
3
2
1
7
3.3/16V
6
100k
Vφ4
φRG
20
Vφ3
Hφ1
1
Vφ2
Hφ2
VL
Vφ1
XSUB
22/20V
GND
12V
VOUT
VDD
GND
φSUB
– 12 –
CSUB
Drive Circuit
1M
0.1
3.3/20V
0.01
3.9k
2SK523
100
CCD OUT
–6.5V
ICX088AK
– 13 –
OB
CLP
CCD
OUT
V4
V3
V2
V1
HD
BLK
VD
FLD
494
493
525
1
2
3
4
5
520
Drive Timing Chart (Vertical Sync)
10
2 4 6
3 5
15
2 4 6
1 3 5
260
493
494
1 3 5
2 4 6
1 3 5
2 4 6
ICX088AK
280
275
270
265
20
– 14 –
V4
V3
V2
V1
( even field )
V4
V3
V2
V1
H1
( odd field )
0
8
8
16
16
24
Drive Timing Chart (Readout)
32
72
504
510
510
504
528
528
528
528
528
528
552
546
540
540
552
546
564
570
564
570
0
858
70
78
72
86
94
ICX088AK
– 15 –
OB
CLP
SUB
V4
V3
V2
V1
RG
H2
H1
10
11
724
1
5
–30
Ignored region
717
718
Effective region
30
20
Effective OB
–6
16
24
32
40
48
56
39
40
0
0
8
72
1
Drive Timing Chart (Horizontal Sync)
10
5
6
7
10
20
1
Ignored region
Dummy bit
30
20
Effective region
ICX088AK
ICX088AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the packege.)
AAAA
AAAA
AAAA AAAA
Cover glass
50N
50N
Plastic package
Compressive strength
AAAA
AAAA
1.2Nm
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 16 –
ICX088AK
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to the other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength
are the same.
Structure A
Structure B
AAA
Package
Chip
Metal plate
(lead frame)
Cross section of
lead frame
The cross section of lead frame can be seen on the side of the package for structure A.
– 17 –
– 18 –
1.0
1.27
5.0
~
~
GOLD PLATING
42 ALLOY
0.6g
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
M
Plastic
0.3
7.0
8.9
10.0 ± 0.1
H
PACKAGE MATERIAL
1
V
14
~
2.5
7
8
A
0.3
0.46
1.0
2.5
7.0
PACKAGE STRUCTURE
B
2.5
0.5
5.0
B'
3.35 ± 0.15
C
1.7
7
8
1.7
1
14
9. The notch of the package is used only for directional index, that must not be used for reference
of fixing.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 25µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 25µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1°.
4. The center of the effective image area relative to “B” and “B'” is (H, V) = (5.0, 5.0) ± 0.15mm.
3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
D
14 pin DIP (400mil)
10.16
Unit: mm
8.9
10.0 ± 0.1
2.6
1.27
3.5 ± 0.3
0° to 9°
0.25
Package Outline
ICX088AK