SONY ICX098BQ

ICX098BQ
Diagonal 4.5mm (Type 1/4) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX098BQ is a diagonal 4.5mm (Type 1/4)
interline CCD solid-state image sensor with a square
pixel array which supports VGA format. Progressive
scan allows all pixels signals to be output
independently within approximately 1/30 second.
Also, the adoption of monitoring mode allows output
to an NTSC monitor without passing through the
memory. This chip features an electronic shutter with
variable charge-storage time which makes it possible
to realize full-frame still image without a mechanical
shutter. High resolution and high color reproductivity
are achieved through the use of R, G, B primary color
mosaic filters. Further, high sensitivity and low dark
current are achieved through the adoption of HAD
(Hole-Accumulation Diode) sensors.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
Features
• Progressive scan allows individual readout of the
image signals from all pixels.
• High horizontal and vertical resolution (both approx.
400TV-lines) still image without a mechanical
shutter.
• Supports monitoring mode
• Square pixel
• Supports VGA format
• Horizontal drive frequency: 12.27MHz
• No voltage adjustments (reset gate and substrate
bias are not adjusted.)
• R, G, B primary color mosaic filters on chip
• High resolution, high color reproductivity, high
sensitivity, low dark current
• Continuous variable-speed shutter
• Low smear
• Excellent antiblooming characteristics
• Horizontal register: 3.3V drive
• 14-pin high precision plastic package (enables dual-surface standard)
Device Structure
• Interline CCD image sensor
• Image size:
• Number of effective pixels:
• Total number of pixels:
• Chip size:
• Unit cell size:
• Optical black:
• Number of dummy bits:
• Substrate material:
14 pin DIP (Plastic)
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Pin 1
2
V
2
Pin 8
H
8
31
Optical black position
(Top View)
Diagonal 4.5mm (Type 1/4)
659 (H) × 494 (V) approx. 330K pixels
692 (H) × 504 (V) approx. 350K pixels
4.60mm (H) × 3.97mm (V)
5.6µm (H) × 5.6µm (V)
Horizontal (H) direction: Front 2 pixels, rear 31 pixels
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
Horizontal 16
Vertical 5
Silicon
∗ Wfine CCD is a registered trademark of Sony Corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00343A0Y
Block Diagram and Pin Configuration
(Top View)
GND
VL
Vφ2B
Vφ2A
Vφ3
Vφ1
7
6
5
4
3
2
1
Vertical register
VOUT
ICX098BQ
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
Note)
Pin No.
Symbol
11
12
φSUB
CSUB
φRG
Description
Pin No.
13
14
Hφ2
10
Hφ1
9
GND
Pin Description
8
VDD
Horizontal register
Note)
Symbol
: Photo sensor
Description
1
Vφ1
Vertical register transfer clock
8
VDD
Supply voltage
2
Vφ3
Vertical register transfer clock
9
GND
GND
3
Vφ2A
Vertical register transfer clock
10
φSUB
4
Vφ2B
Vertical register transfer clock
11
CSUB
Substrate clock
Substrate bias∗1
5
VL
Protective transistor bias
12
φRG
Reset gate clock
6
GND
GND
13
Hφ1
Horizontal register transfer clock
7
VOUT
Signal output
14
Hφ2
Horizontal register transfer clock
∗1 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
Absolute Maximum Ratings
Item
Against φSUB
Ratings
Unit
VDD, VOUT, φRG – φSUB
–40 to +10
V
Vφ2A, Vφ2B – φSUB
–50 to +15
V
Vφ1, Vφ3, VL – φSUB
–50 to +0.3
V
Hφ1, Hφ2, GND – φSUB
–40 to +0.3
V
–25 to
V
VDD, VOUT, φRG, CSUB – GND
–0.3 to +18
V
Vφ1, Vφ2A, Vφ2B, Vφ3 – GND
–10 to +18
V
Hφ1, Hφ2 – GND
–10 to +5
V
Vφ2A, Vφ2B – VL
–0.3 to +28
V
Vφ1, Vφ3, Hφ1, Hφ2, GND – VL
–0.3 to +15
V
to +15
V
CSUB – φSUB
Against GND
Against VL
Voltage difference between vertical clock input pins
Between input
Hφ1 – Hφ2
clock pins
Hφ1, Hφ2 – Vφ3
–5 to +5
V
–13 to +13
V
Storage temperature
–30 to +80
°C
–10 to +60
°C
Operating temperature
∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
Remarks
∗2
ICX098BQ
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
14.55
15.0
∗1
15.45
V
Supply voltage
VDD
Protective transistor bias
VL
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗2
Remarks
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Symbol
Min.
Typ.
6.0
IDD
Supply current
Max.
Remarks
Unit
mA
Clock Voltage Conditions
Min.
Typ.
Max.
Unit
Waveform
diagram
VVT
14.55
15.0
15.45
V
1
VVH02A
–0.05
0
0.05
V
2
VVH1, VVH2A,
VVH2B, VVH3
–0.2
0
0.05
V
2
VVL1, VVL2A,
VVL2B, VVL3
–5.8
–5.5
–5.2
V
2
Vφ1, Vφ2A,
Vφ2B, Vφ3
5.2
5.5
5.8
V
2
| VVL1 – VVL3 |
0.1
V
2
VVHH
0.3
V
2
High-level coupling
VVHL
1.0
V
2
High-level coupling
VVLH
0.5
V
2
Low-level coupling
VVLL
0.5
V
2
Low-level coupling
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Symbol
Substrate clock voltage
VVH = VVH02A
VVL = (VVL1+VVL3)/2
VφH
3.0
3.3
5.25
V
3
VHL
–0.05
0
0.05
V
3
3.0
3.3
5.5
V
4
VRGLH – VRGLL
0.4
V
4
Low-level coupling
VRGL – VRGLm
0.5
V
4
Low-level coupling
21.25
V
5
VφRG
Reset gate clock
voltage
Remarks
VφSUB
19.75
20.5
–3–
ICX098BQ
Clock Equivalent Circuit Constant
Item
Symbol
Min.
Typ.
Max.
Unit
CφV1
2200
pF
CφV2A, CφV2B
1500
pF
CφV3
1000
pF
CφV12A, CφV2B1
390
pF
CφV2A3, CφV32B
680
pF
CφV13
820
pF
Capacitance between horizontal
transfer clock and GND
CφH1, CφH2
15
pF
Capacitance between horizontal transfer
clocks
CφHH
47
pF
Capacitance between reset gate clock
and GND
CφRG
3
pF
Capacitance between substrate clock and
GND
CφSUB
270
pF
R1
15
Ω
R2A, R2B
100
Ω
R3
62
Ω
Vertical transfer clock ground resistor
RGND
47
Ω
Horizontal transfer clock series resistor
RφH
15
Ω
Reset gate clock series resistor
RφRG
62
Ω
Capacitance between vertical transfer
clock and GND
Capacitance between vertical transfer
clocks
Vertical transfer clock series resistor
Vφ1
Remarks
Vφ2A
CφV12A
R1
R2A
RφH
RφH
Hφ1
CφV1
Hφ2
CφHH
CφV2A
CφV2B1
CφV2A3
CφH1
CφH2
CφV13
CφV2B RGND CφV3
R2B
R3
CφV32B
Vφ2B
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
RφRG
RGφ
CφRG
Reset gate clock equivalent circuit
–4–
ICX098BQ
Drive Clock Waveform Conditions
(1) Readout clock waveform
VT
100%
90%
II
II
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
Note) Readout clock is used by composing vertical transfer clocks Vφ2A and Vφ2B.
(2) Vertical transfer clock waveform
Vφ1
VVH1
VVHH
VVH
VVHL
VVLH
VVL01
VVL1
VVL
VVLL
Vφ2A, Vφ2B
VVH02A, VVH02B
VVH2A, VVH2B
VVHH
VVH
VVHL
VVLH
VVL2A, VVL2B
VVL
VVLL
Vφ3
VVH3
VVHH
VVH
VVHL
VVLH
VVL03
VVL
VVLL
VVH = VVH02A
VVL = (VVL01 + VVL03) /2
VVL3 = VVL03
VφV1 = VVH1 – VVL01
VφV2A = VVH02A – VVL2A
VφV2B = VVH02B – VVL2B
VφV3 = VVH3 – VVL03
–5–
ICX098BQ
(3) Horizontal transfer clock waveform
tr
twh
tf
Hφ2
90%
VCR
VφH
twl
VφH
2
10%
VHL
Hφ1
two
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr
twh
tf
VRGH
RG waveform
twl
VφRG
Point A
VRGLH
VRGLL
VRGLm
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and
VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
φM
2
VφSUB
10%
0%
VSUB
(A bias generated within the CCD)
tr
twh
–6–
tf
ICX098BQ
Clock Switching Characteristics
Item
Symbol
VT
Vertical transfer
clock
Vφ1,Vφ2A,
Vφ2B, Vφ3
Horizontal
transfer clock
Readout clock
Hφ1
During
imaging
Hφ2
twh
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
2.3 2.5
0.5
0.5
15
25.5 30.5
28
28
33
33
25.5 30.5
During
Hφ1
parallel-serial
Hφ2
conversion
Reset gate clock
φRG
11
Substrate clock
φSUB
1.5 1.8
12
63.5
350
9
16.5
9
16.5
9
14
9
14
0.01
0.01
0.01
0.01
3
3
0.5
Unit
Remarks
µs
During
readout
ns
∗1
ns
∗2
µs
ns
0.5
µs
During
drain
charge
∗1 When vertical transfer clock driver CXD1267AN is used.
∗2 tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be
at least VφH/2 [V].
two
Item
Symbol
Horizontal transfer clock
Hφ1, Hφ2
Min. Typ. Max.
Unit
Remarks
ns
21.5 25.5
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
1.0
G
R
B
Relative Response
0.8
0.6
0.4
0.2
0
400
450
500
550
Wave Length [nm]
–7–
600
650
700
ICX098BQ
Image Sensor Characteristics
Item
(Ta = 25°C)
Measurement
method
mV
1
Min.
Typ.
Sg
460
580
R
Rr
0.4
0.55
0.7
1
B
Rb
0.3
0.45
0.6
1
Saturation signal
Vsat
500
Smear
Sm
Video signal shading
SHg
G sensitivity
Sensitivity
comparison
Max.
Unit
Symbol
Remarks
mV
2
%
3
20
%
4
Zone 0 and I
25
%
4
Zone 0 to II'
0.0008 0.0025
Ta = 60°C
Uniformity between video
signal channels
∆Srg
8
%
5
∆Sbg
8
%
5
Dark signal
Vdt
4
mV
6
Ta = 60°C
Dark signal shading
∆Vdt
1
mV
7
Ta = 60°C
Line crawl G
Lcg
3.8
%
8
Line crawl R
Lcr
3.8
%
8
Line crawl B
Lcb
3.8
%
8
Lag
Lag
0.5
%
9
Zone Definition of Video Signal Shading
659 (H)
12
12
12
V
10
H
8
H
8
Zone 0, I
Zone II, II'
V
10
494 (V)
10
Ignored region
Effective pixel region
Measurement System
CCD signal output [∗A]
Gr/Gb
CCD
C.D.S
AMP
S/H
Gr/Gb channel signal output [∗B]
R/B
S/H
R/B channel signal output [∗C]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.
–8–
ICX098BQ
Image Sensor Characteristics Measurement Method
Color coding and readout of this image sensor
Gb
B
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
The primary color filters of this image sensor are arranged in the layout
shown in the figure on the left (Bayer arrangement).
Gr and Gb denote the G signals on the same line as the R signal and
the B signal, respectively.
Horizontal register
Color Coding Diagram
All pixels signals are output successively in a 1/30s period.
The R signal and Gr signal lines and the Gb signal and B signal lines are output successively.
Readout modes
The diagram below shows the output methods for the following two readout modes.
Monitoring mode
Progressive scan mode
VOUT
7
R
G
7
R
G
6
G
B
6
G
B
5
R
G
5
R
G
4
G
B
4
G
B
3
R
G
3
R
G
2
G
B
2
G
B
1
R
G
1
R
G
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out.
1. Progressive scan mode
In this mode, all pixel signals are output in non-interlace format in 1/30s.
The vertical resolution is approximately 400TV-lines and all pixel signals within the same exposure period
are read out simultaneously, making this mode suitable for high resolution image capturing.
2. Monitoring mode
The signals for all effective areas are output during a single field period of NTSC standard (approximately 1/60s)
by repeating readout pixels and non-readout pixels every two lines. The vertical resolution is approximately
200TV-lines. Note that the same pixel signal is output for both odd and even fields.
Since signals are output in a format which conforms to NTSC, the external circuit can be simplified when
monitoring using an NTSC monitor.
–9–
ICX098BQ
Measurement conditions
1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb
signal output or the R/B signal output of the measurement system.
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter
and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the
standard sensitivity testing luminous intensity.
2) Standard imaging condition ΙΙ:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. G sensitivity, sensitivity comparison
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/100s, measure the signal outputs (VGr, VGb, VR and VB) at the center of each Gr, Gb, R and B channel
screens, and substitute the values into the following formula.
VG = (VGr + VGb)/2
Sg = VG × 100 [mV]
30
Rr = VR/VG
Rb = VB/VG
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the
average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal
outputs.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of
the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R signal
output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to 500 times the intensity
with average value of the Gr signal output, 150mV. After the readout clock is stopped and the charge drain is
executed by the electronic shutter at the respective H blankings, measure the maximum value (Vsm [mV]),
independent of the Gr, Gb, R and B signal outputs, and substitute the values into the following formula.
Sm = Vsm ÷
Gra + Gba + Ra + Ba
1
1
×
×
× 100 [%] (1/10V method conversion value)
4
500 10
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and
minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula.
SHg = (Grmax – Grmin)/150 × 100 [%]
– 10 –
ICX098BQ
5. Uniformity between video signal channels
After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal
and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values
into the following formula.
∆Srg = (Rmax – Rmin)/150 × 100 [%]
∆Sbg = (Bmax – Bmin)/150 × 100 [%]
6. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7. Dark signal shading
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
8. Line crawl
Set to standard imaging condition II. Adjusting the luminous intensity so that the average value of the Gr
signal output is 150mV, and then insert R, G, and B filters and measure the difference between G signal
lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab).
Substitute the values into the following formula.
Lci = ∆Gli × 100 [%] (i = r, g, b)
Gai
9. Lag
Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/150) × 100 [%]
VD
V2A
Light
Strobe light
timing
Gr signal output 150mV
Output
– 11 –
Vlag (Lag)
XV2B
XSG2
XV3
XV1
XV2A
XSG1
– 12 –
RG
H2
H1
CXD1267AN
11
10
22/20V
12
9
17
16
15
14
13
4
5
6
7
8
1/35V
22/16V
1/20V
100K
0.1
1 2
3 4 5
6
ICX098
(Bottom View)
Vφ3
XSUB
0.1
7
8
2200p
14 13 12 11 10 9
φRG
Vφ1
Hφ2
Hφ1
20
VL
19
18
Vφ2A
Vφ2B
CSUB
1
2
3
VDD
15V
GND
VOUT
φSUB
GND
Drive Circuit
1M
33/20V
3.9K
2SK523
100
0.01
3.3/16V
CCD OUT
–5.5V
ICX098BQ
ICX098BQ
Sensor Readout Clock Timing Chart
Progressive Scan Mode
XV1
XV2A
XV2B
XV3
XSG1
XSG2
Sensor readout clocks XSG1 and XSG2 are used by
composing XV2A and XV2B.
81.4ns (1 bit)
HD
2.53µs (31 bits)
42.2µs (520 bits)
V1
V2A
V2B
V3
– 13 –
ICX098BQ
Sensor Readout Clock Timing Chart
Monitoring Mode
XV1
XV2A
XV2B
XV3
XSG1
XSG2
Sensor readout clock XSG1 is used by
composing XV2A.
81.4ns (1 bit)
HD
2.53µs (31 bits)
42.2µs (520 bits)
V1
V2A
V2B
V3
– 14 –
– 15 –
CCD
OUT
V3
V2B
V2A
V1
HD
VD
Progressive Scan Mode
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 1011
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Drive Timing Chart (Vertical Sync)
525
1
2
3
4
5
6
7
1 2 3 4 5 6 7 8 1 2
ICX098BQ
520
510
494
504
– 16 –
CCD
OUT
V3
V2B
V2A
V1
HD
BLK
VD
FLD
520
486
489
490
493
494
Monitoring Mode
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1 2 5 6 1 2 5 6 9 1013 1417 18
260
261
262
263
264
265
486
489
490
493
494
Drive Timing Chart (Vertical Sync)
285
280
275
1 2 5 6 1 2 5 6 9 10 13 1417 18
ICX098BQ
270
– 17 –
SHD
SHP
RG
SUB
V3
V2B
V2A
V1
H2
H1
CLK
BLK
HD
780
1
Drive Timing Chart (Horizontal Sync)
Progressive Scan Mode
78
ICX098BQ
140
– 18 –
SHD
SHP
RG
SUB
V3
V2B
V2A
V1
H2
H1
CLK
BLK
HD
780
1
Drive Timing Chart (Horizontal Sync)
Monitoring Mode
78
ICX098BQ
140
ICX098BQ
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
AAAA AAAA AAAA
AAAA AAAA AAAA
Cover glass
50N
50N
1.2Nm
Plastic package
Compressive strength
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 19 –
ICX098BQ
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to the other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength
are the same.
Structure A
Structure B
AAA
Package
Chip
Metal plate
(lead frame)
Cross section of
lead frame
The cross section of lead frame can be seen on the side of the package for structure A.
– 20 –
– 21 –
1.0
1.27
5.0
~
~
42 ALLOY
0.60g
AS-D3-01(E)
LEAD MATERIAL
PACKAGE MASS
DRAWING NUMBER
GOLD PLATING
LEAD TREATMENT
M
Plastic
0.3
7.0
8.9
10.0 ± 0.1
H
PACKAGE MATERIAL
1
V
14
5.0
~
2.5
7
8
0.3
0.46
1.0
2.5
7.0
PACKAGE STRUCTURE
B
2.5
0.5
A
B'
C
1.7
7
8
1.7
1
14
9. The notch of the package is used only for directional index, that must not be used for reference
of fixing.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 25µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 25µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1˚.
4. The center of the effective image area relative to “B” and “B'” is (H, V) = (5.0, 5.0) ± 0.15mm.
3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
D
10.16
14 pin DIP (400mil)
8.9
10.0 ± 0.1
2.6
Unit: mm
3.35 ± 0.15
1.27
3.5 ± 0.3
0˚ to 9˚
0.25
Package Outline
ICX098BQ
Sony Corporation