ICX424AQ
Diagonal 6mm (Type 1/3) Progressive Scan CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX424AQ is a diagonal 6mm (Type 1/3) interline
CCD solid-state image sensor with a square pixel
array which supports VGA format. Progressive scan
allows all pixels signals to be output independently
within approximately 1/60 second. This chip features
an electronic shutter with variable charge-storage
time which makes it possible to realize full-frame still
images without a mechanical shutter. High sensitivity
and low dark current are achieved through the
adoption of the HAD (Hole-Accumulation Diode)
sensors.
This chip is suitable for applications such as FA
and surveillance cameras.
Features
• Progressive scan allows individual readout of the image signals
from all pixels.
• High vertical resolution still images without a mechanical shutter
• Square pixel
• Supports VGA format
• Horizontal drive frequency: 24.54MHz
• No voltage adjustments (reset gate and substrate bias are not
adjusted.)
• R, G, B primary color mosaic filters on chip
• High resolution, high color reproductivity, high sensitivity, low dark
current
• Continuous variable-speed shutter
• Low smear
• Excellent anti-blooming characteristics
• Horizontal register: 5.0V drive
• 16-pin high precision plastic package (enables dual-surface standard)
16 pin DIP (Plastic)
Pin 1
2
V
8
2
Pin 9
H
31
Optical black position
(Top View)
Device Structure
• Interline CCD image sensor
• Image size:
Diagonal 6mm (Type 1/3)
• Number of effective pixels: 659 (H) × 494 (V) approx. 330K pixels
• Total number of pixels:
692 (H) × 504 (V) approx. 350K pixels
• Chip size:
5.79mm (H) × 4.89mm (V)
• Unit cell size:
7.4µm (H) × 7.4µm (V)
• Optical black:
Horizontal (H) direction: Front 2 pixels, rear 31 pixels
Vertical (V) direction:
Front 8 pixels, rear 2 pixels
• Number of dummy bits:
Horizontal 16
Vertical 5
• Substrate material:
Silicon
∗ Wfine CCD is trademark of Sony corporation.
Represents a CCD adopting progressive scan, primary color filter and square pixel.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01Z29A25-PS
ICX424AQ
GND
CGG
GND
NC
Vφ1
Vφ2
Vφ3
8
7
6
5
4
3
2
1
Vertical register
VOUT
Block Diagram and Pin Configuration
(Top View)
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
G
B
G
B
R
G
R
G
Note)
Horizontal register
12
13
14
15
16
φSUB
VL
φRG
Hφ1
Hφ2
SUBCIR
11
GND
10
VDD
Note)
9
: Photo sensor
Pin Description
Pin No. Symbol
Description
Pin No. Symbol
Description
1
Vφ3
Vertical register transfer clock
9
VDD
Supply voltage
2
Vφ2
Vertical register transfer clock
10
SUBCIR
Supply voltage for the substrate
voltage generation
3
Vφ1
Vertical register transfer clock
11
GND
GND
4
NC
12
φSUB
Substrate clock
5
GND
GND
13
VL
Protective transistor bias
6
CGG
Output amplifier gate∗1
14
φRG
Reset gate clock
7
GND
GND
15
Hφ1
Horizontal register transfer clock
8
VOUT
Signal output
16
Hφ2
Horizontal register transfer clock
∗1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance
of 1000pF.
–2–
ICX424AQ
Absolute Maximum Ratings
Item
Ratings
Unit
–0.3 to +36
V
VDD, VOUT, CGG, SUBCIR – GND
–0.3 to +18
V
VDD, VOUT, CGG, SUBCIR – φSUB
–22 to +9
V
Vφ1, Vφ2, Vφ3 – GND
–15 to +16
V
to +10
V
Voltage difference between vertical clock input pins
to +15
V
Voltage difference between horizongal clock input pins
to +16
V
Hφ1, Hφ2 – Vφ3
–16 to +16
V
Hφ1, Hφ2 – GND
–10 to +15
V
Hφ1, Hφ2 – φSUB
–55 to +10
V
VL – φSUB
–65 to +0.3
V
Vφ2, Vφ3 – VL
–0.3 to +27.5
V
RG – GND
–0.3 to +20.5
V
Vφ1, Hφ1, Hφ2, GND – VL
–0.3 to +17.5
V
Storage temperature
–30 to +80
°C
Performance guarantee temperature
–10 to +60
°C
Operating temperature
–10 to +75
°C
Substrate clock φSUB – GND
Supply voltage
Clock input voltage
Vφ1, Vφ2, Vφ3 – φSUB
∗2 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed for power-on and power-off.
–3–
Remarks
∗2
ICX424AQ
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
14.55
15.0
15.45
V
Supply voltage
VDD
Protective transistor bias
VL
∗1
Substrate clock
φSUB
∗2
Reset gate clock
φRG
∗3
Remarks
∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same voltage as the VL power
supply for the V driver should be used.
∗2 Set SUBCIR pin to open when applying a DC bias to the substrate clock pin.
∗3 Do not apply a DC bias to the reset gate clock pins, because a DC bias is generated within the CCD.
DC Characteristics
Symbol
Item
Supply current
Min.
IDD
Typ.
Max.
Unit
7
9
mA
Remarks
Clock Voltage Conditions
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Symbol
Waveform
Diagram
Min.
Typ.
Max. Unit
Remarks
VVT
14.55
15.0
15.45
V
1
VVH02
–0.05
0
0.05
V
2
VVH1, VVH2, VVH3
–0.2
0
0.05
V
2
VVL1, VVL2, VVL3
–7.8
–7.5
–7.2
V
2
VVL = VVL1 (VVL3)/2
(During 24.54MHz)
VVL1, VVL2, VVL3
–8.0
–7.5
–7.0
V
2
VVL = VVL1 (VVL3)/2
(During 12.27MHz)
Vφ1, Vφ2, Vφ3
6.8
7.5
8.05
V
2
| VVL1 – VVL3 |
0.1
V
2
VVHH
1.0
V
2
High-level coupling
VVHL
2.3
V
2
High-level coupling
VVLH
1.0
V
2
Low-level coupling
VVLL
1.0
V
2
Low-level coupling
VVH = VVH02
VφH
4.75
5.0
5.25
V
3
VHL
–0.05
0
0.05
V
3
VCR
0.8
2.5
V
3
VφRG
4.5
5.0
5.5
V
4
VRGLH – VRGLL
0.8
V
4
Low-level coupling
VRGL – VRGLm
0.5
V
4
Low-level coupling
23.5
V
5
Substrate clock voltage VφSUB
21.5
22.5
–4–
Cross-point voltage
ICX424AQ
Clock Equivalent Circuit Constants
Symbol
Item
Capacitance between vertical transfer clock and GND
Capacitance between vertical transfer clocks
Min.
Typ.
Max.
Unit
CφV1
3900
pF
CφV2
3300
pF
CφV3
3300
pF
CφV12
1000
pF
CφV23
1000
pF
CφV31
1000
pF
47
pF
Capacitance between horizontal transfer clock and GND CφH1, CφH2
Capacitance between horizontal transfer clocks
CφHH
30
pF
Capacitance between reset gate clock and GND
CφRG
6
pF
Capacitance between substrate clock and GND
CφSUB
560
pF
R1, R2
33
Ω
R3
18
Ω
Vertical transfer clock ground resistor
RGND
100
Ω
Horizontal transfer clock series resistor
RφH1, RφH2
10
Ω
Reset gate clock series resistor
RφRG
39
Ω
Vertical transfer clock series resistor
Vφ1
R1
R2
CφV12
CφV1
Vφ2
CφV2
RφH1
RφH2
Hφ1
Hφ2
RGND
CφV31
Remarks
CφHH
CφV3
CφV23
CφH1
CφH2
R3
Vφ3
Vertical transfer clock equivalent circuit
φRG
Horizontal transfer clock equivalent circuit
RφRG
CφRG
Reset gate clock equivalent circuit
–5–
ICX424AQ
Drive Clock Waveform Conditions
(1) Readout clock waveform
VT
100%
90%
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
Note) Readout clock is used by composing vertical transfer clocks Vφ2 and Vφ3.
(2) Vertical transfer clock waveform
VVH1
Vφ1
VVHH
VVH
VVHL
VVLH
VVL01
VVL1
VVL
VVLL
Vφ2
VVH02
VVH2
VVHH
VVH
VVHL
VVLH
VVL2
VVL
VVLL
VVH3
Vφ3
VVHH
VVH
VVHL
VVLH
VVL03
VVL
VVLL
VVH = VVH02
VVL = (VVL01 + VVL03)/2
VVL3 = VVL03
–6–
VφV1 = VVH1 – VVL01
VφV2 = VVH02 – VVL2
VφV3 = VVH3 – VVL03
ICX424AQ
(3) Horizontal transfer clock waveform
tr
Hφ1, Hφ 2
tf
twh
Hφ2
90%
VCR
VφH
twl
VφH
2
10%
Hφ1
VHL
two
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
φRG
tr
twh
tf
VRGH
RG waveform
twl
VφRG
Point A
VRGLH
VRGLL
VRGLm
VRGL
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
φSUB
100%
90%
φM
VφSUB
10%
VSUB
0%
(A bias generated within the CCD)
tr
twh
–7–
φM
2
tf
ICX424AQ
Clock Switching Characteristics (Horizontal drive frequency: 24.54MHz)
twh
Item
Symbol
twl
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Readout clock
VT
2.3 2.5
Vertical transfer
clock
Vφ1, Vφ2,
Vφ3
Horizontal
transfer clock
Hφ1
10.5 14.6
10.5 14.6
6.4 10.5
6.4 10.5
Hφ2
10.5 14.6
10.5 14.6
6.4 10.5
6.4 10.5
Reset gate clock φRG
Substrate clock
0.5
15
6
φSUB
0.5
8
25.8
4
0.75 0.9
Symbol
Horizontal transfer clock
Hφ1, Hφ2
3
0.5
two
Item
250
Min. Typ. Max.
10.5 14.6
Unit
Remarks
ns
∗1
Unit
Remarks
µs
During
readout
ns
When using
CXD3400N
ns
tf ≥ tr – 2ns
ns
0.5
µs
During drain
charge
Unit
Remarks
Clock Switching Characteristics (Horizontal drive frequency: 12.27MHz)
twh
Item
Symbol
VT
Vertical transfer
clock
Vφ1, Vφ2,
Vφ3
Horizontal
transfer clock
Hφ1
Reset gate clock φRG
Substrate clock
φSUB
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
4.6 5.0
Readout clock
Hφ2
twl
0.5
0.5
15
24
30
26.5 31.5
11
25 31.5
10 17.5
10 17.5
25
30
10
10
62.5
3
13
1.5 1.8
Item
Symbol
Horizontal transfer clock
Hφ1, Hφ2
350
15
3
0.5
two
Min. Typ. Max.
21.5 25.5
Unit
Remarks
ns
∗1
∗1 The overlap period of twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
–8–
15
µs
During
readout
ns
When using
CXD3400N
ns
tf ≥ tr – 2ns
ns
0.5
µs
During drain
charge
ICX424AQ
Image Sensor Characteristics
Item
(Ta = 25°C)
Unit
Measurement
method
mV
1
Symbol
Min.
Typ.
G Sensitivity
Sg
600
750
Sensitivity
comparison
Rr
0.4
0.55
0.7
1
Rb
0.3
0.45
0.6
1
Saturation signal
Vsat
500
Smear
Sm
Video signal shading
SHg
Max.
Remarks
1/30s accumulation
mV
2
–92
dB
3
20
%
4
Zone 0 and I
25
%
4
Zone 0 to II'
∆Srg
Uniformity between
video signal channels ∆Sbg
8
%
5
8
%
5
Dark signal
Vdt
2
mV
6
Ta = 60°C
Dark signal shading
∆Vdt
0.5
mV
7
Ta = 60°C
Line crawl G
Lcg
3.8
%
8
Line crawl R
Lcr
3.8
%
8
Line crawl B
Lcb
3.8
%
8
Lag
Lag
0.5
%
9
–100
Ta = 60°C
Note) All image sensor characteristic data noted above is for operation in 1/60s progressive scan mode.
Zone Definition of Video Signal Shading
659 (H)
12
12
12
H
8
V
10
H
8
Zone 0, I
494 (V)
10
Zone II, II'
Ignored region
Effective pixel region
V
10
Measurement System
CCD signal output [∗A]
Gr/Gb
CCD
C.D.S
AMP
S/H
Gr/Gb channel signal output [∗B]
R/B
S/H
R/B channel signal output [∗C]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.
–9–
ICX424AQ
Image Sensor Characteristics Measurement Method
Measurement conditions
(1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions.
(2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb
channel signal output or the R/B channel signal output of the measurement system.
Color coding of this image sensor & Readout
Gb
B
Gb
B
R
Gr
R
Gr
Gb
B
Gb
B
R
Gr
R
Gr
The primary color filters of this image sensor are arranged in
the layout shown in the figure on the left (Bayer arrangement).
Gr and Gb denote the G signals on the same line as the R
signal and the B signal, respectively.
Horizontal register
Color Coding Diagram
All pixels signals are output successively in a 1/60s period.
The R signal and Gr signal lines and Gb signal and B signal lines are output successively.
– 10 –
ICX424AQ
Image sensor readout mode
The diagram below shows the output methods for the following two readout modes.
(1) Progressive scan mode
R
G
G
B
R
G
G
B
R
G
VOUT
1. Progressive scan mode
In this mode, all pixel signals are output in non-interlace format in 1/60s.
All pixel signals within the same exposure period are read out simultaneously, making this mode suitable for
high resolution image capturing.
(2) Center scan mode
Undesired portions (Swept by vertical register high-speed transfer)
Picture center cut-out portion
2. Center scan mode
This is the center scan mode using the progressive scan method.
The undesired portions are swept by vertical register high-speed transfer, and the picture center portion is
cut out.
There are the mode (120 frames/s) which outputs 222 lines of an output line portion, and the mode
(240 frames/s) which outputs 76 lines.
– 11 –
ICX424AQ
Definition of standard imaging conditions
(1) Standard imaging condition I:
Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
(2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. G Sensitivity,sensitivity comparison
Set to standard imaging condition I. After setting the electronic shutter mode with a shutter speed of
1/100s, measure the signal outputs (VGr, VGb, VR and VB ) at the center of each Gr, Gb, R and B channel
screens, and substitute the values into the following formula.
VG = (VGr + VGb)/2
Sg = VG × 100 [mV]
30
Rr = VR/VG
Rb = VB/VG
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the
average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B signal
outputs.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average value of
the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal output, R
signal output and B signal output (Gra, Gba, Ra and Ba), and then adjust the luminous intensity to 500
times the intensity with average value of the Gr signal output, 150mV. After the readout clock is stopped and
the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum
value (Vsm [mV]), independent of the Gr, Gb, R and b signal outputs, and substitute the values into the
following formula.
(
Sm = 20 × log Vsm ÷
Gra + Gba + Ra + Ba
× 1 × 1
4
500
10
)
[dB] (1/10V method conversion value)
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the Gr signal output is 150mV. Then measure the maximum (Grmax [mV]) and
minimum (Grmin [mV]) values of the Gr signal output and substitute the values into the following formula.
SHg = (Grmax –Grmin)/150 × 100 [%]
– 12 –
ICX424AQ
5. Uniformity between video signal channels
After measuring 4, measure the maximum (Rmax [mV]) and minimum (Rmin [mV]) values of the R signal
and the maximum (Bmax [mV]) and minimum (Bmin [mV]) values of the B signal, and substitute the values
into the following formula.
∆Srg = | (Rmax – Rmin)/150 | × 100 [%]
∆Sbg = | (Bmax – Bmin)/150 | × 100 [%]
6. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
7. Dark signal shading
After measuring 6, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
8. Line crawls
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Gr signal
output is 150mV, and then insert R, G, and B filters and measure the difference between G signal lines
(∆Glr, Glg, Glb [mV]).as well as the average value of the G signal output (Gar, Gag, Gab). Substitute the
values into the following formula.
Lci =
∆Gli
× 100 [%] (i = w, r, g, b)
Gai
9. Lag
Adjust the Gr signal output value generated by strobe light to 150mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/150) × 100 [%]
VD
V2
Light
Strobe light
timing
Signal output 150mV
Output
– 13 –
Vlag (lag)
6
XV2
φRG
Hφ1
Hφ2
XV1
XSG2
16
5
XSG3
11
12
9
10
13
14
8
7
17
4
15
18
3
XV3
CXD3400N
19
2
XSUB
0.1
1/35V
0.1
0.1
1
Vφ3
Hφ2
9
16 15 14 13 12 11 10
ICX424
(BOTTOM VIEW)
8
7
6
5
4
3
2
Vφ2
Hφ1
1000p
Vφ1
3.3/16V
φRG
20
NC
VL
1
GND
φSUB
3.3V
0.1
0.1
CGG
2200p
GND
100k
GND
15V
VOUT
SUBCIR
– 14 –
VDD
Drive Circuit
1M
3.3/20V
0.01
4.7k
2SC4250
CCD
OUT
–7.5V
ICX424AQ
ICX424AQ
Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics)
1.0
G
0.9
R
0.8
B
Relative Response
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
450
500
550
Wave Length [nm]
– 15 –
600
650
700
– 16 –
OUT
V3
V2
V1
510
494
1
2
HD
"a"
7
1
2
3
4
5
6
7
8
1
2
3
525
1
VD
510
508
494
1
2
Progressive Scan Mode
7
1
2
3
4
5
6
7
8
Drive Timing Chart (Vertical Sync)
ICX424AQ
525
1
V3
V2
V1
H1
"a" Enlarged
12 12 12 12 12 12
Drive Timing Chart (Vertical Sync "a" Enlarged)
520
62
582
50
Progressive Scan Mode/Center Scand Mode
12 12 12 12 12 12
ICX424AQ
– 17 –
– 18 –
780
1
RG
1
1
SUB
35
1
1
1
1
V3
V2
V1
SHD
SHP
H2
H1
CLK
12 1
Progressive Scan Mode
24
1
37 1
36 1
36 1
23 1
36 1
1 72 107
12
12
24
36
123
125
16
Drive Timing Chart (Horizontal Sync)
ICX424AQ
– 19 –
OUT
V3
V2
V1
HD
245
246
356
357
"a"
"b"
261
262
1
2
3
4
5
6
7
8
1
"d"
"c"
24
136
137
VD
"d"
245
246
356
357
Center Scan Mode 1
"a"
"b"
261
262
1
2
3
4
5
6
7
8
1
20
21
Drive Timing Chart (Vertical Sync)
ICX424AQ
– 20 –
V3
V2
V1
H2
H1
#142
#1
10920 bits = 14H
12 12 12 12 12 12
Center Scan Mode 1 (Frame Shift) ("b")
12 12 12 12 12 12
72
35
Drive Timing Chart (Horizontal Sync)
ICX424AQ
– 21 –
V3
V2
V1
H2
H1
#167
#1
12480 bits = 16H
12 12 12 12 12 12
Center Scan Mode 1 (High-speed Sweep) ("d")
12 12 12 12 12 12
72
35
Drive Timing Chart (Horizontal Sync)
ICX424AQ
– 22 –
OUT
V3
V2
V1
"d"
105
106
283
284
"a"
"b"
129
130
131
1
2
3
4
5
6
7
8
1
HD
"c"
30
209
210
VD
"d"
105
106
283
284
Center Scan Mode 2
"a"
"b"
129
130
131
1
2
3
4
5
6
7
8
1
26
27
Drive Timing Chart (Vertical Sync)
ICX424AQ
– 23 –
V3
V2
V1
H2
H1
#215
#1
15600 bits = 20H
12 12 12 12 12 12
Center Scan Mode 2 (Frame Shift) ("b")
12 12 12 12 12 12
72
35
Drive Timing Chart (Horizontal Sync)
ICX424AQ
– 24 –
V3
V2
V1
H2
H1
#255
#1
18720 bits = 24H
12 12 12 12 12 12
Center Scan Mode 2 (High-speed Sweep) ("d")
12 12 12 12 12 12
72
35
Drive Timing Chart (Horizontal Sync)
ICX424AQ
ICX424AQ
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W
soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount,
cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero-cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operations as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load
more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to
limited portions. (This may cause cracks in the package.)
Cover glass
50N
50N
1.2Nm
Plactic package
Torsional strength
Compressive strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 25 –
ICX424AQ
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
– 26 –
– 27 –
1.2
~
~
42 ALLOY
0.90g
AS-C2.2-01(E)
LEAD MATERIAL
PACKAGE MASS
DRAWING NUMBER
GOLD PLATING
LEAD TREATMENT
M
Plastic
0.3
1.27
9.2
10.3
12.2 ± 0.1
H
PACKAGE MATERIAL
V
~
2.5
0.46
0.3
A
1.2
2.5
8.4
(For the first pin only)
0.69
5.7
PACKAGE STRUCTURE
B
6.1
D
B'
9.5
11.4 ± 0.1
3.1
2.5
0.5
C
1
8
11.6
16
9
2.5
2-R0.5
9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1˚.
4. The center of the effective image area relative to “B” and “B'”
is (H, V) = (6.1, 5.7) ± 0.15mm.
3. The bottom “C” of the package, and the top of the cover glass “D”
are the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
16 pin DIP (450mil)
11.43
Unit: mm
3.35 ± 0.15
1.27
3.5 ± 0.3
0˚ to 9˚
0.25
Package Outline
ICX424AQ
Sony Corporation