TI SN65LVDS109

SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
D
D
D
D
D
D
D
D
D
D
D
D
Two Line Receivers and Eight (’109) or
Sixteen (’117) Line Drivers Meet or Exceed
the Requirements of ANSI EIA/TIA-644
Standard
Designed for Signaling Rates up to 632
Mbps
Outputs Arranged in Pairs From Each Bank
Enabling Logic Allows Individual Control of
Each Driver Output Pair, Plus all Outputs
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100Ω Load
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
Propagation Delay Times < 4.5 ns
Output Skew Less Than 550 ps
Bank Skew Less Than 150 ps
Part-to-Part Skew Less Than 1.5 ns
Total Power Dissipation Typically < 500 mW
With All Ports Enabled and at 200 MHz
Driver Outputs or Receiver Input Equals
High Impedance When Disabled or With
VCC < 1.5 V
Bus-Pin ESD Protection Exceeds 12 kV
Packaged in Thin Shrink Small-Outline
Package With 20 mil Terminal Pitch
SN65LVDS109
DBT PACKAGE
(TOP VIEW)
GND
VCC
GND
NC
ENM
ENA
ENB
1A
1B
GND
2A
2B
ENC
END
NC
NC
GND
VCC
GND
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
description
The SN65LVDS109 and SN65LVDS117 are
configured as two identical banks, each bank
having one differential line receiver connected to
either four (’109) or eight (’117) differential line
drivers. The outputs are arranged in pairs having
one output from each of the two banks. Individual
output enables are provided for each pair of
outputs and an additional enable is provided for all
outputs.
A1Y
A1Z
A2Y
A2Z
NC
B1Y
B1Z
B2Y
B2Z
NC
C1Y
C1Z
C2Y
C2Z
NC
D1Y
D1Z
D2Y
D2Z
SN65LVDS117
DGG PACKAGE
(TOP VIEW)
GND
VCC
VCC
GND
NC
ENM
ENA
ENB
ENC
END
NC
GND
1A
1B
GND
VCC
VCC
GND
2A
2B
GND
NC
ENE
ENF
ENG
ENH
NC
NC
GND
VCC
VCC
GND
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
A1Y
A1Z
A2Y
A2Z
B1Y
B1Z
B2Y
B2Z
C1Y
C1Z
C2Y
C2Z
D1Y
D1Z
D2Y
D2Z
E1Y
E1Z
E2Y
E2Z
F1Y
F1Z
F2Y
F2Z
G1Y
G1Z
G2Y
G2Z
H1Y
H1Z
H2Y
H2Z
The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling
(LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise
emission, high noise immunity, and high switching speeds. It can be used to transmit data at speeds up to at
least 622 Mbps and over relatively long distances. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
description (continued)
The intended application of these devices, and the LVDS signaling technique, is for point-to-point or
point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of
approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The
large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced
signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is
particularly advantageous for implementing system clock and data distribution trees.
The SN65LVDS109 and SN65LVDS117 are characterized for operation from –40°C to 85°C.
2
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SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
logic diagram (positive logic)
SN65LVDS109
SN65LVDS117
A1Y
A1Y
ENA
A1Z
ENA
A1Z
ENM
A2Y
ENM
A2Y
ENB
A2Z
A2Z
B1Y
B1Y
B1Z
ENB
B2Y
1A
1B
ENC
2A
2B
END
B2Z
C1Y
C1Z
B1Z
B2Y
1A
1B
ENC
B2Z
C1Y
C1Z
C2Y
C2Y
C2Z
C2Z
D1Y
D1Y
D1Z
END
D1Z
D2Y
D2Y
D2Z
D2Z
E1Y
ENE
E1Z
E2Y
E2Z
F1Y
ENF
F1Z
F2Y
2A
2B
ENG
F2Z
G1Y
G1Z
G2Y
G2Z
H1Y
ENH
H1Z
H2Y
H2Z
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• DALLAS, TEXAS 75265
3
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
selection guide to LVDS splitters
The SN65LVDS109 and SN75LVDS117 are both members of a family of LVDS splitters and repeaters. A brief
overview of the family is provided by the following table.
LVDS SPLITTER AND REPEATER FAMILY
NUMBER
OF INPUTS
NUMBER OF
OUTPUTS
SN65LVDS104
1 LVDS
4 LVDS
16-pin D
4-port LVDS repeater
SN65LVDS105
1 LVTTL
4 LVDS
16-pin D
4-port TTL-to-LVDS repeater
SN65LVDS108
1 LVDS
8 LVDS
38-pin DBT
8-port LVDS repeater
SN65LVDS109
2 LVDS
8 LVDS
38-pin DBT
Dual 4-Port LVDS repeater
SN65LVDS116
1 LVDS
16 LVDS
64-pin DGG
16-port LVDS repeater
SN65LVDS117
2 LVDS
16 LVDS
64-pin DGG
Dual 8-port LVDS repeater
DEVICE
PACKAGE
COMMENTS
FUNCTION TABLE
OUTPUTS
INPUTS
VID = VA – VB
X
ENM
ENx
xY
xZ
L
X
Z
Z
X
X
L
Z
Z
VID ≥ 100 mV
–100 mV < VID < 100 mV
H
H
H
L
H
H
?
?
VID ≤–100 mV
H
H
L
H
equivalent input and output schematic diagrams
VCC
VCC
VCC
300 kΩ
(ENM Only)
300 kΩ
300 kΩ
50 Ω
Enable
Inputs
A Input
B Input
10 kΩ
7V
7V
(ENx Only)
4
Y or Z
Output
7V
300 kΩ
7V
5Ω
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage range, Enable inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
A, B, Y or Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Electrostatic discharge, Y, Z, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:12 kV, B: 500 V
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 4 kV, B: 400 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
DBT
1277 mW
10.2 mW/°C
644 mW
DGG
2094 mW
16.7 mW/°C
1089 mW
TA = 85°C
POWER RATING
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k)
with no air flow.
recommended operating conditions
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
Low-level input voltage, VIL
Magnitude of differential input voltage, VID
0.1
V
Ť
Common-mode input voltage, VIC
Operating free-air temperature, TA
ID
2
• DALLAS, TEXAS 75265
UNIT
3.6
V
V
0.8
V
3.6
V
V
Ť
–40
POST OFFICE BOX 655303
MAX
Ť
2.4 –
ID
2
Ť
VCC – 0.8
85
V
V
°C
5
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VITH+
VITH–
Positive-going differential input voltage threshold
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude
between logic states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
Negative-going differential input voltage threshold
SN65LVDS109
ICC
Supply current
SN65LVDS117
Input current (A or B inputs)
II(OFF)
IIH
Power-off input current (A or B inputs)
IIL
Low-level input current (enables)
High-level input current (enables)
Short circuit output current
Short-circuit
IOZ
IO(OFF)
High-impedance output current
CIN
Input capacitance (A or B inputs)
See Figure 3
Enabled,
–100
247
340
50
1.125
1.375
–50
50
RL = 100 Ω
RL = 100 Ω
50
150
46
64
6
8
85
122
6
–2
–1.2
Power-off output current
VCC = 1.5 V,
VO = 3.6 V
VI = 0.4 sin (4E6πt) + 0.5 V
VI = 0.4 sin (4E6πt) + 0.5 V, Disabled
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
V
mV
mA
µA
µA
20
µA
10
µA
±12
9.4
mV
20
±24
VOD = 0 V
VO = 0 V or VCC
mV
8
–20
VI = 2.4 V
UNIT
454
–50
Disabled
VCC = 1.5 V,
VIH = 2 V
MAX
100
Disabled
Enabled,
TYP†
VIL = 0.8 V
VOY or VOZ = 0 V
CO
Output capacitance (Y or Z outputs)
† All typical values are at 25°C and with a 3.3 V supply.
6
RL= 100 Ω
Ω,
VID= ±100 mV
mV,
See Figure 1 and Figure 2
VI = 0 V
VI = 2.4 V
II
IOS
See Figure 1 and Table 1
MIN
mA
±1
µA
±1
µA
pF
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
switching characteristics over recommended operating conditions (unless otherwise noted)
MIN
TYP†
MAX
tPLH
tPHL
Propagation delay time, low-to-high-level output
1.6
2.8
4.5
Propagation delay time, high-to-low-level output
1.6
2.8
4.5
tr
tf
Differential output signal rise time
0.3
0.8
1.2
0.3
0.8
1.2
140
500
100
550
40
150
ps
1.5
ns
PARAMETER
tsk(p)
tsk(o)
tsk(b)
tsk(pp)
TEST CONDITIONS
RL = 100 Ω,
CL = 10 pF,
pF
See Figure 4
Differential output signal fall time
Pulse skew (|tPHL - tPLH|)‡
Output skew§
Bank skew¶
Part-to-part skew#
tPZH
tPZL
Propagation delay time, high-impedance-to-high-level output
tPHZ
tPLZ
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, high-impedance-to-low-level output
See Figure 5
Propagation delay time, low-level-to-high-impedance output
5.7
15
7.7
15
3.2
15
3.2
15
UNIT
ns
ns
ps
ns
ns
† All typical values are at 25°C and with a 3.3 V supply.
‡ tsk(p) is the magnitude of the time difference between the tPLH and tPHL of any output of a single device.
§ tsk(o) is the magnitude of the time difference between the tPLH or tPHL of any outputs with both inputs tied together.
¶ tsk(b) is the magnitude of the time difference between the tPLH and tPHL of the two outputs of any bank of a single device.
# tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
IIA
IIB
VID
IOY
A
Y
B
Z
VIA
IOZ
VOD
VOY
VOZ
VIB
VOC
(VOY + VOZ)/2
Figure 1. Voltage and Current Definitions
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• DALLAS, TEXAS 75265
7
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VIA
1.25 V
VIB
1.15 V
VID
100 mV
VIC
1.2 V
1.15 V
1.25 V
-100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
-100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
-100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
-600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
-600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
-600 mV
0.3 V
3.75 kΩ
Y
100 Ω
3.75 kΩ
VOD
Input
Z
±
0 V ≤ VTEST ≤ 2.4 V
Figure 2. VOD Test Circuit
49.9 Ω ± 1% (2 Places)
Y
Input
Input
VI
1.4 V
VI
1V
Z
50 pF
VOC(PP)
VOC
VOC(SS)
VO
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulsewidth = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
A
Y
B
Z
Input
1.4 V
1.2 V
1V
VIB
Input
VIA
tPLH
VOD
tPHL
100 Ω ± 1 %
VOD(H)
Output
CL = 10 pF
(2 Places)
100%
80%
0V
VOD(L)
20%
0%
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulsewidth = 10 ±0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
Y
1 V or 1.4 V
49.9 Ω ± 1% (2 Places)
Z
1.4 V or 1 V
+
Inputs
EN
CL = 10 pF
(2 Places)
VOY
VOZ
2V
1.4 V
0.8 V
Input
VOY
or
VOZ
1.2 V
–
tPZH
tPHZ
100%, ≅ 1.4 V
50%
0%, 1.2 V
tPZL
tPLZ
100%, 1.2 V
VOZ
50%
or
0%, ≅ 1 V
VOY
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 5. Enable and Disable Time Circuit and Definitions
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9
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
SN65LVDS109
SN65LVDS117
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
140
220
120
200
I CC – Supply Current – mA
I CC – Supply Current – mA
TYPICAL CHARACTERISTICS
VCC = 3.6 V
100
VCC = 3 V
80
60
VCC = 3.3 V
40
180
VCC = 3.6 V
160
VCC = 3 V
140
120
VCC = 3.3 V
20
100
All Outputs Loaded
and Enabled
0
0
50
100
150
200
250
300
All Outputs Loaded
and Enabled
80
350
0
50
100
f – Frequency – MHz
150
Figure 6
3.6
3.5
VCC = 3.3 V
VCC = 3 V
3.3
3.2
–25
0
25
50
75
100
TA – Free–Air Temperature – °C
t PHL – High-To-Low Propagation Delay Time – ns
t PLH – Low-To-High Propagation Delay Time – ns
3.7
3.1
–50
350
400
3.7
3.6
3.5
3.4
3.3
VCC = 3.3 V
VCC = 3.6 V
VCC = 3 V
3.2
3.1
3.0
2.9
–50
–25
0
25
Figure 9
POST OFFICE BOX 655303
50
TA – Free–Air Temperature – °C
Figure 8
10
300
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.8
VCC = 3.6 V
250
Figure 7
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.4
200
f – Frequency – MHz
• DALLAS, TEXAS 75265
75
100
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
Figure 10. Typical Differential Eye Pattern at 400 Mbps
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11
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
The SN65LVDS109 and SN65LVDS117 devices solve several problems common to the distribution of timing
critical clock and data signals. These problems include:
D
D
D
D
D
Excessive skew between the signals
Noise pickup over long signaling paths
High power consumption
Control of which signal paths are enabled or disabled
Elimination of radiation from unterminated lines
Buffering and splitting the two related signals on the same silicon die minimizes corruption of the timing relation
between the two signals. Buffering and splitting the two signals in separate devices will introduce considerably
higher levels of uncontrolled timing skew between the two signals. Higher speed operation and more timing
tolerance for other components of the system is enabled by the tighter system timing budgets provided by the
single die implementations of the SN65LVDS109 and SN65LVDS117.
The use of LVDS signaling technology for both the inputs and the outputs provides superior common–mode and
noise tolerance compared to single-ended I/O technologies. This is particularly important because the signals
that are being distributed must be transmitted over longer distances, and at higher rates, than can be
accommodated with single-ended I/Os. In addition, LVDS consumes considerably less power than other
high-performance differential signaling schemes.
The enable inputs provided for each output pair may be used to turn on or off any of the paths. This function
is required to prevent radiation of signals from the unterminated signal lines on open connectors, such as when
boards or devices are being swapped in the end equipment. The individual bank enables are also required if
redundant paths are being utilized for reliability reasons.
The diagram below shows how a pair of clock (C) and data (D) input signals is being identically repeated out
two of the available output pairs. A third output pair is shown in the disabled state.
SOURCE
EQUIPMENT/
BOARD
C
D
DUAL n–PORT REPEATER
C
D
C
Output Pair Disabled
D
C
D
DESTINATION
EQUIPMENT/
BOARD #1
DESTINATION
EQUIPMENT/
BOARD #2
DESTINATION
EQUIPMENT/
BOARD #n
Figure 11. LVDS Repeating Splitter Application Example Showing Individual Path Control
12
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SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
A LVDS receiver can be used to receive various other types of logic signals. Figure 12 through Figure 20 show the
termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
VDD
25 Ω
50 Ω
A
50
Ω
1/2 VDD
B
0.1 µF
LVDS Receiver
Figure 12. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
VDD
50 Ω
A
50 Ω
B
1.35 V < VTT < 1.65 V
0.1 µF
LVDS Receiver
Figure 13. Center-Tap Termination (CTT)
1.14 V < VTT < 1.26 V
VDD
1 kΩ
50 Ω
50 Ω
A
B
2 kΩ
0.1 µF
LVDS Receiver
Figure 14. Gunning Transceiver Logic (GTL)
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• DALLAS, TEXAS 75265
13
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Z0
Z0
A
B
1.47 V < VTT < 1.62 V
0.1 µF
LVDS Receiver
Figure 15. Backplane Transceiver Logic (BTL)
3.3 V
3.3 V
50 Ω
120 Ω
120 Ω
33 Ω
ECL
A
50 Ω
33 Ω
51 Ω
B
51 Ω
LVDS Receiver
Figure 16. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
5V
5V
82 Ω
50 Ω
82 Ω
100 Ω
ECL
A
50 Ω
100 Ω
B
33 Ω
33 Ω
LVDS Receiver
Figure 17. Positive Emitter-Coupled Logic (PECL)
3.3 V
3.3 V
7.5 kΩ
A
B
7.5 kΩ
0.1 µF
LVDS Receiver
Figure 18. 3.3-V CMOS
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15
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
5V
5V
10 kΩ
560 Ω
A
B
560 Ω
3.32 kΩ
0.1 µF
LVDS Receiver
Figure 19. 5-V CMOS
5V
5V
10 kΩ
470 Ω
A
B
3.3 V
4.02 kΩ
0.1 µF
Figure 20. TTL
16
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LVDS Receiver
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
MECHANICAL DATA
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°– 8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
28
30
38
44
50
A MAX
7,90
7,90
9,80
11,10
12,60
A MIN
7,70
7,70
9,60
10,90
12,40
DIM
4073252/D 09/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
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17
SN65LVDS109, SN65LVDS117
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS
SLLS369C – AUGUST 1999 – REVISED MARCH 2000
MECHANICAL DATA
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
18
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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