TI SN65LVDS049PW

SN65LVDS049
5,0 mm x 6,4 mm
www.ti.com
SLLS575 – AUGUST 2003
DUAL LVDS DIFFERENTIAL DRIVERS AND RECEIVERS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DS90LV049 Compatible
Up to 400 Mbps Signaling Rates
Flow-Through Pin-out
50 ps Driver Channel-to-Channel Skew (Typ)
50 ps Receiver Channel-to-Channel Skew
(Typ)
3.3-V Power Supply
High-Impedance Disable for all Outputs
Internal Failsafe Biasing of Receiver Inputs
1.4 ns Driver Propagation Delay (Typ)
1.9 ns Receiver Propagation Delay (Typ)
High Impedance Bus Pins on Power Down
ANSI TIA/EIA-644-A Compliant
Receiver Input and Driver Output ESD Exceeds 10 kV
16-pin TSSOP Package
The intended application of this device and signaling
technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and
distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to
the environment, and other application specific characteristics)
The SN65LVDS049 is characterized for operation from
–40°C to 85°C
FUNCTIONAL DIAGRAM
RIN1−
•
R2
ROUT2
RIN2−
DOUT2−
Full-duplex LVDS Communications of Clock
and Data
Printers
DOUT2+
DOUT1+
DESCRIPTION
The SN65LVDS049 is a dual flow-through differential
line driver-receiver pair that uses low-voltage differential signaling (LVDS) to achieve signaling rates as high
as 400 Mbps. The TIA/EIA-644-A standard compliant
electrical interface provides a minimum differential output voltage magnitude of 250 mV into a 100-Ω load and
receipt of signals with up to 1 V of ground potential
difference between a transmitter and receiver. The
LVDS receivers have internal failsafe biasing that
places the outputs into a known high state for unconnected differential inputs.
ROUT1
RIN2+
APPLICATIONS
•
R1
RIN1+
D2
DIN2
D1
DIN1
DOUT1−
EN
EN
AND
PW PACKAGE (Marked as LVDS049)
(TOP VIEW)
RIN1 RIN1+
RIN2+
RIN2 DOUT2 DOUT2+
DOUT1+
DOUT1 -
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
EN
ROUT1
ROUT2
GND
VCC
DIN2
DIN1
EN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2003, Texas Instruments Incorporated
SN65LVDS049
www.ti.com
SLLS575 – AUGUST 2003
DRIVER TRUTH TABLE
INPUT
OUTPUTS (1)
ENABLES
DIN
EN
EN
L
H
L or OPEN
H
X
(1)
All other conditions
DOUT+
DOUT-
L
H
H
L
Z
Z
H = high level, L = low level, X = irrelevant, Z = high impedance (off)
RECEIVER TRUTH TABLE
DIFFERENTIAL INPUT
EN
EN
ROUT
VID ≥ 100 mV
H
L or OPEN
H
VID ≤ - 100 mV
L
Open/short or terminated
H
X
(1)
OUTPUT (1)
ENABLES
RIN- - RIN+
All other conditions
Z
H = high level, L = low level, X = irrelevant, Z = high impedance (off)
ENABLE FUNCTION TABLE
ENABLES
OUTPUTS
EN
EN
LVDS Out
LVCMOS Out
L or Open
L or Open
DISABLED
DISABLED
H
L or Open
ENABLED
ENABLED
L or Open
H
DISABLED
DISABLED
H
H
DISABLED
DISABLED
POWER DISSIPATION RATING
(1)
(2)
2
PACKAGE
CIRCUIT BOARD
MODEL
TA≤25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PW
Low-K (2)
774 mW
6.2 mW/°C
402 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
SN65LVDS049
www.ti.com
SLLS575 – AUGUST 2003
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage range (2), VCC
-0.3 V to 4 V
DIN, ROUT, EN, or EN
Voltage range
-0.3 V to (VCC + 0.3 V)
RIN+ or RIN-
-0.3 V to 4 V
DOUT+ or DOUTESD
Human Body Model (3)
Charged-Device Model (4)
-0.3 V to 3.9 V
RIN+, RIN-, DOUT+, and DOUT-
±10 kV
All pins
±2K V
±500 V
All pins
LVDS output short circuit duration (DOUT+, DOUT-)
Continuous
Continuous power dissipation
See Dissipation Rating Table
Storage temperature range
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
(4)
260°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC
MIN
NOM
MAX
3
3.3
3.6
Receiver input voltage
GND
Common-mode input voltage, VIC
V ID
2
Operating free-air temperature, TA
-40
UNIT
V
V
V V
VCC - 0.8
V
85
°C
2.4 ID
2
3
SN65LVDS049
www.ti.com
SLLS575 – AUGUST 2003
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
2.0
VCC
V
GND
0.8
V
INPUT DC SPECIFICATIONS (DIN, EN, EN)
VIH
Input high voltage
VIL
Input low voltage
IIH
Input high current
VIN = VCC
-10
3
10
µA
IIL
Input low current
VIN = GND
-10
1
10
µA
VCL
Input clamp voltage
ICL = -18 mA
-1.5
-0.8
250
350
450
V
-35
1
35
mV
1.125
1.2
1.375
-25
1
25
mV
V
LVDS Output DC Specifications (DOUT+, DOUT-)
|VOD|
Differential output voltage
∆|VOD|
Change in magnitude of VOD for
complimentary output states
VOS
Offset voltage
∆VOS
Change in magnitude of VOS for
complimentary output states
IOS
Output short circuit current
Enabled
DIN = VCC and DOUT+ = 0 V, or
DIN = GND and DOUT- = 0 V
-4.5
-9
mA
IOSD
Differential output short circuit current (2)
Enabled, VOD = 0 V
-3.6
-9
mA
IOFF
Power-off leakage
VCC = 0 V or Open;
VO = 0 or 3.6 V
-20
0
20
µA
IOZ
Output high-impedance current
EN = 0 V and EN = VCC,
VO = 0 or VCC
-10
0
10
µA
RL = 100 Ω, See Figure 1
V
LVDS Input DC Specifications (RIN+, RIN-)
VIT+
Differential input high threshold
VIT-
Differential input low threshold
VCMR
Common-mode voltage range
IIN
Input current
VCM = 1.2 V, 0.05 V, 2.35 V
VID = ± 100 mV
100
-100
mV
mV
0.05
2.35
V
VCC = 3.6 V, VIN = 0 V or 2.8 V
-20
20
µA
VCC= 0 V, VIN = 0 V, 2.8 V, or 3.6 V
-20
20
µA
2.7
0.05
0.25
V
0
10
µA
17
35
mA
1
25
mA
Outputs DC Specifications (ROUT)
VOH
Output high voltage
IOH = -0.4 mA, VID = 200 mV
VOL
Output Low voltage
IOL = 2 mA, VID = -200 mV
IOZ
Output high-impedance current
Disabled, VOUT = 0 V or VCC
-10
3.3
V
Device DC Specifications
ICC
Power supply current
(LVDS loaded, enabled)
EN = 3.3 V, DIN = VCC or Gnd, 100 -Ω
differential LVDS loads
ICCZ
High impedance supply current (disabled)
No loads, EN = 0 V
(1)
(2)
4
All typical values are at 25°C and with a 3.3 V supply.
Output short circuit current (IOS) is specified as magnitude only, the minus sign indicates direction only
SN65LVDS049
www.ti.com
SLLS575 – AUGUST 2003
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
1.3
2.0
ns
1.4
2.0
ns
UNIT
LVDS Outputs (DOUT+, DOUT-)
RL = 100 Ω,
CL = 15 pF distributed,
See Figure 2
tPLHD
Differential propagation delay low to high
tPHLD
Differential propagation delay high to low
tsk(p)
Differential pulse skew (|tPHL - tPLH|)
0
0.15
0.4
ns
tsk(o)
0
0.05
0.5
ns
tsk(pp)
Differential channel-to-channel skew (2)
Differential part-to-part skew (3)
1
ns
tr
Differential rise time
0.2
0.5
1
ns
tf
Differential fall time
0.2
0.5
1
ns
tPHZ
Disable time, high level to high impedance
2.7
4
ns
tPLZ
Disable time, low level to high impedance
2.7
4
ns
tPZH
Enable time, high impedance to high level
1
5
8
ns
tPZL
Enable time, high impedance to low level
Maximum operating frequency (4)
1
5
8
fMAX
0
RL = 100 Ω,
CL = 15 pF distributed,
See Figure 3
250
ns
MHz
LVCMOS Outputs (ROUT)
tPLH
Propagation delay low to high
tPHL
Propagation delay high to low
tsk(p)
Pulse skew (|tPHL - tPLH|)
tsk(o)
tsk(pp)
Channel-to-channel skew (5)
Part-to-part skew (6)
tr
Rise time
tf
Fall time
tPHZ
Disable time, high level to high impedance
tPLZ
Disable time, low level to high impedance
tPZH
Enable time, high impedance to high level
tPZL
Enable time, high impedance to low level
Maximum operating frequency (7)
fMAX
(1)
(2)
(3)
(4)
(5)
(6)
(7)
VID= 200 mV,
CL = 15 pF distributed,
See Figure 4
0.5
1.9
3.5
ns
0.5
1.7
3.5
ns
0
0.2
0.4
ns
0
0.05
0.5
ns
1
ns
0.5
1.4
ns
0.3
0.5
1.4
ns
3
7.2
9
ns
2.5
4
8
ns
2.5
4.2
7
ns
2
3.3
7
200
250
0
0.3
CL = 15 pF distributed,
See Figure 5
ns
MHz
All typical values are at 25°C and with a 3.3 V supply.
tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected
together.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output Criteria: duty cycle = 45% to 55%, VOD
> 250 mV, all channels switching.
tsk(lim) is the maximum delay time difference between drivers over temperature, VCC, and process.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both
devices operate wf(MAX) generaith the same supply voltages, at the same temperature, and have identical packages and test circuits
f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, VID = 200 mV, VCM = 1.2 V. Output criteria: duty cycle =
45% to 55%, VOH > 2.7 V, VOL < 0.25 V, all channels switching.
5
SN65LVDS049
www.ti.com
SLLS575 – AUGUST 2003
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
300 kΩ
VCC
300 kΩ
50 Ω
EN,EN,DIN
RIN
RIN
7V
7V
7V
300 kΩ
VCC
VCC
50 Ω
ROUT
50 Ω
10 kΩ
DOut
7V
7V
PARAMETER MEASUREMENT INFORMATION
DOUT+
VCC
DIN
RL/2
VOD
GND
RL/2
VOS
Driver Enabled
DOUT-
Figure 1. Driver VOD and VOS Test Circuit
6
SN65LVDS049
www.ti.com
SLLS575 – AUGUST 2003
Oscilloscope
*
DOUT+
C1
50 Ω
*
Pulse
Generator
DIN
50 Ω
*
C2
DOUT* Matched 50 Cables,
C = 15 pF Distributed
50 Ω
Blocking Capacitors
C1 = C2 = 50 nF
3V
DIN
1.5 V
1.5 V
0V
tPLHD
tPLLD
DOUT-
0 V*
*Differential
VOH
0 V*
VOL
DOUT+
VOD
80 %
0V
20 %
80 %
VOD = DOUT+ - DOUT-
t
tf
tr
0V
20 %
Figure 2. Driver Propagation Delay and Rise/Fall Time Test Circuit and Waveforms
2.4 V
1 kΩ
1 kΩ
DOUT+
VCC
DIN
100 Ω 950 Ω
GND
EN or EN
950 Ω
DOUT-
Pulse
Generator
Oscilloscope
*
50 Ω
*
50 Ω
*
50 Ω
* Matched 50 Ω Cables,
C = 15 pF Distributed
3V
EN When EN = GND or Open
1.5 V
1.5 V
0V
3V
EN When EN = VCC
1.5 V
1.5 V
0V
tPHZ
DOUT+ When DIN = VCC
tPZH
50 %
VOH
50 %
DOUT- When DIN = GND
DOUT+ When DIN = GND
DOUT- When DIN = VCC
1.2 V
1.2 V
50 %
50 %
VOL
tPLZ
tPZL
Figure 3. Driver High-Impedance State Delay Test Circuit and Waveforms
7
SN65LVDS049
www.ti.com
SLLS575 – AUGUST 2003
Oscilloscope
*
RIN+
*
Pulse
Generator
RIN-
50 Ω
ROUT
100 Ω
*
50 Ω
*
*
950 Ω
50 Ω
* Matched 50 Ω Cables,
C = 15 pF Distributed
RIN-
1.3 V
0 V Differential
RIN+
1.2 V
VID = 200 mV
1.1 V
tPLH
ROUT
tPHL
VOH
80 %
80 %
1.5 V
20 %
1.5 V
20 %
tr
VOL
tf
Figure 4. Receiver Propagation Delay and Rise/Fall Test Circuit and Waveforms
VCC
RIN+
1.4 V
ROUT
100 Ω
1V
950 Ω
RIN-
Pulse
Generator
Oscilloscope
1 kΩ
*
50 Ω
EN or EN
*
* Matched 50 Ω Cables,
C = 15 pF Distributed
50 Ω
3V
EN When EN = GND or OPEN
1.5 V
1.5 V
0V
3V
EN When EN = VCC
1.5 V
1.5 V
0V
tPHZ
tPHZ
VOH
ROUT for RIN+ = 1.4 V
and RIN- = 1 V
50 %
0.5 V
VCC/2
ROUT for RIN+ = 1 V
and RIN- = 1.4 V
VCC/2
0.5 V
50 %
VOL
tPLZ
tPZL
Figure 5. Receiver High-Impedance State Delay Test Circuit and Waveforms
(Note, VCC = 3.3 V)
8
SN65LVDS049
www.ti.com
SLLS575 – AUGUST 2003
TYPICAL CHARACTERISTICS
600
60
VCC = 3.3 V,
TA = 25°C
500
50
ICC - Supply Current - mA
|VOD | - Differential Output Voltage - mV
Power Supply Current
vs. Frequency
VOD vs. Load Resistance
400
300
200
100
40
VCC = 3.3 V,
TA = 25°C,
RL = 100 Ω,
CL = 15 pF Distributed,
VID = 400 mV p-p,
VI = 3 V
All Switching
30
Single Receiver
20
Single Driver
10
0
40
60
80
100
120
RL - Load Resistance - Ω
Figure 6.
140
160
0
0.1
1
10
100
f - Frequency - MHz
1000
Figure 7.
9
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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