Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION Z86C63/64 CMOS Z8® 32K ROM MICROCONTROLLER GENERAL DESCRIPTION The Z86C63/64 microcontroller introduces a new level of sophistication to single-chip architecture. The Z86C63/64 is a member of the Z8 single-chip microcontroller family with 32 Kbytes of ROM and 256 bytes of RAM. The Z86C63 is housed in a 40-pin DIP, and a 44-pin PLCC package, and is manufactured in CMOS technology. The ROMless pin option is available on the 44-pin version only. The Z86C64 is housed in a 64-pin DIP, and a 68-pin PLCC. Both versions of the Z86C64 have the ROMless pin option, which allows both external memory and preprogrammed ROM, enabling this Z8 microcontroller to be used in highvolume applications or where code flexibility is required. The Z86C96 ROMless Z8 will support the Z86C63/64. Zilog’s CMOS microcontroller offers fast execution, more efficient use of memory, more sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. There are three basic address spaces available to support this wide range of configurations: Program Memory, Data Memory, and 236 General-Purpose Registers. To unburden the program from coping with the real-time problems such as counting/timing and serial data communication, the Z86C63/64 offers two on-chip counter/timers with a large number of user selectable modes, and an asynchronous receiver/transmitter (UART) (see Block Diagrams). Notes: All Signals with a preceding front slash, "/", are active Low, e.g., B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power Ground VCC GND VDD VSS The Z86C63/64 architecture is characterized by Zilog’s 8-bit microcontroller core. The device offers a flexible I/O scheme, an efficient register and address space structure, multiplexed capabilities between address/data, I/O, and a number of ancillary features that are useful in many industrial and advanced scientific applications. For applications which demand powerful I/O capabilities, the Z86C63 fulfills this with 32 pins dedicated to input and output. These lines are grouped into four ports with eight lines each. The Z86C64 has 52 pins for input and output, and these lines are grouped into six, 8-bit ports and one 4-bit port. Each port is configurable under software control to provide timing, status signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory. DC-5461-02 (12-13-93) 1 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y GENERAL DESCRIPTION Output Input Vcc GND Machine Timing and Instruction Control Port 3 UART ALU Counter/ Timers (2) FLAGS Interrupt Control Prg. Memory 32,768 x 8-Bit Register Pointer Program Counter Register File 256 x 8-Bit Port 0 Port 2 4 I/O (Bit Programmable) XTAL /AS /DS R//W /RESET Port 1 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) Z86C63 Functional Block Diagram 2 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y Output Input Vcc GND Port 3 ALU Program Memory 32,768 x 8-Bit Flags Counter/ Timers (2) Register Pointer Port 6 Port 5 Port 4 Port 0 4 I/O (Bit Programmable) Program Counter Register File 256 x 8-Bit Port 2 I/O (Bit Programmable) /AS /DS R//W /RESET Machine Timing and Instruction Control UART Interrupt Control XTAL Port 1 4 Address or I/O (Nibble Programmable) 8 Address/Data or I/O (Byte Programmable) Z86C64 Functional Block Diagram 3 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y PIN DESCRIPTION Z86C63 40-Pin DIP Pin Identification VCC 1 40 P36 XTAL2 2 39 P31 XTAL1 3 38 P27 P37 4 37 P26 P30 5 36 P25 /RESET 6 35 P24 R//W 7 34 P23 /DS 8 33 P22 /AS 9 32 P21 P35 10 31 P20 30 P33 GND Z86C63 11 DIP P32 12 29 P34 P00 13 28 P17 P01 14 27 P16 P02 15 26 P15 P03 16 25 P14 P04 17 24 P13 P05 18 23 P12 P06 19 22 P11 P07 20 21 P10 Z86C63 40-Pin DIP Pin Assignments 4 Pin # Symbol Function Direction 1 2 3 4 5 VCC XTAL2 XTAL1 P37 P30 Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Input Output Input Output Input 6 7 8 9 10 /RESET R//W /DS /AS P35 Reset Read/Write Data Strobe Address Strobe Port 3, Pin 5 Input Output Output Output Output 11 12 13-20 21-28 29 GND P32 P07-P00 P17-P10 P34 Ground Input Port 3, Pin 2 Input Port 0, Pins 0,1,2,3,4,5,6,7 In/Output Port 1, Pins 0,1,2,3,4,5,6,7 In/Output Port 3, Pin 4 Output 30 31-38 39 40 P33 P27-P20 P31 P36 Port 3, Pin 3 Input Port 2, Pins 0,1,2,3,4,5,6,7 In/Output Port 3, Pin 1 Input Port 3, Pin 6 Output Z86C63/64 CPS DC-5461-02 VCC 2 1 44 43 42 41 40 P25 XTAL2 3 P26 XTAL1 4 P27 P37 5 P31 P30 6 P36 N/C P R E L I M I N A R Y /RESET 7 39 N/C R//W 8 38 P24 /DS 9 37 P23 /AS 10 36 P22 P35 11 35 P21 34 P20 Z86C63 PLCC GND 12 P32 13 33 P33 P00 14 32 P34 P01 15 31 P17 P02 16 30 P16 /ROMless 17 29 P15 N/C P14 P13 P12 P11 P10 P07 P06 P05 P04 P03 18 19 20 21 22 23 24 25 26 27 28 Z86C63 44-Pin PLCC Pin Assignments Z86C63 44-Pin PLCC Pin Identification Pin # Symbol Function Direction Pin # Symbol Function Direction 1 2 3 4 5 VCC XTAL2 XTAL1 P37 P30 Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port 3, Pin 7 Port 3, Pin 0 Input Output Input Output Input 17 18-22 23-27 28 /ROMless P07-P03 P14-P10 N/C ROM/ROMless control Port 0, Pins 3,4,5,6,7 Port 1, Pins 0,1,2,3,4 Not Connected Input In/Output In/Output Input 6 7 8 9 10 N/C /RESET R//W /DS /AS Not Connected Reset Read/Write Data Strobe Address Strobe Input Input Output Output Output 29-31 32 33 34-38 P17-P15 P34 P33 P24-P20 Port 1, Pins 5,6,7 Port 3, Pin 4 Port 3, Pin 3 Port 2, Pins 0,1,2,3,4 In/Output Output Input In/Output 11 12 13 14-16 P35 GND P32 P02-P00 Port 3, Pin 5 Ground Port 3, Pin 2 Port 0, Pins 0,1,2 Output Input Input In/Output 39 40-42 43 44 N/C P25-P27 P31 P36 Not Connected Port 2, Pins 5,6,7 Port 3, Pin 1 Port 3, Pin 6 Input In/Output Input Output 5 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y PIN DESCRIPTION (Continued) Z86C64 64-Pin DIP Pin Identification P44 1 64 P43 VCC 2 63 P42 P45 3 62 P36 XTAL2 4 61 P31 XTAL1 5 60 P41 P37 6 59 P40 P30 7 58 P27 N/C 8 57 P26 /RESET 9 56 P25 R//W 10 55 P24 /DS 11 54 P23 P46 12 53 P22 P47 13 52 P60 /AS 14 51 P61 P35 15 50 P21 /ROMless 16 49 P20 GND 17 48 GND P32 18 47 P33 P50 19 46 P34 P51 Z86C64 DIP 20 45 P62 P00 21 44 P63 P01 22 43 P17 P02 23 42 P16 P03 24 41 P15 P04 25 40 P14 P05 26 39 P13 P06 27 38 P12 P07 28 37 P57 VCC 29 36 P56 P52 30 35 P11 P53 31 34 P10 P54 32 33 P55 Z86C64 64-Pin DIP Pin Assignments 6 Pin # Symbol Function Direction 1 2 3 4 5 P44 VCC P45 XTAL2 XTAL1 Port 4, Pin 4 Power Supply Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock In/Output Input In/Output Output Input 6 7 8 9 10 P37 P30 N/C /RESET R//W Port 3, Pin 7 Port 3, Pin 0 Not Connected Reset Read/Write Output Input Input Input Output 11 12-13 14 15 /DS P47-P46 /AS P35 Data Strobe Port 4, Pin 6,7 Address Strobe Port 3, Pin 5 Output In/Output Output Output 16 17 18 19-20 /ROMless ROM/ROMless control GND Ground P32 Port 3, Pin 2 P51-P50 Port 5, Pin 0,1 Input Input Input In/Output 21-28 29 30-33 34-35 36-37 P07-P00 VCC P52-P55 P11-P10 P57-P56 Port 0, Pins 0,1,2,3,4,5,6,7 Power Supply Port 5, Pins 2,3,4,5 Port 1, Pins 0,1 Port 5, Pins 6,7 In/Output Input In/Output In/Output In/Output 38-43 44-45 46 47 48 P17-P12 P63-P62 P34 P33 GND Port 1, Pins 2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 Ground In/Output In/Output Output Input Input 49-50 51-52 53-58 59-60 P21-P20 P61-P60 P27-P22 P41-P40 Port 2, Pins 0,1 Port 6, Pins 1,0 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 In/Output In/Output In/Output In/Output 61 62 63 64 P31 P36 P42 P43 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 Port 4, Pin 3 Input Output In/Output In/Output Z86C63/64 CPS DC-5461-02 7 6 5 4 2 1 P2 5 3 8 P2 6 VC C P4 4 P4 3 P4 2 P3 6 P3 1 P4 1 P4 0 P2 7 9 /R es et P3 0 P3 7 XT AL 1 XT AL P4 2 5 P R E L I M I N A R Y 68 67 66 65 64 63 62 61 R//W 10 60 P24 /P0DS 11 59 P23 /DS 12 58 P22 P46 13 57 P60 P47 14 56 P61 /P1DS 15 55 P21 /AS 16 54 P20 /DTimers 17 53 SCLK P35 18 52 /SYNC /ROMless 19 51 GND GND 20 50 P33 P32 21 49 P34 P50 22 48 P62 P51 23 47 P63 P00 24 46 P17 P01 25 45 P16 P02 26 44 P15 Z86C64 PLCC 4 P1 7 P1 2 P1 3 P5 3 P5 4 P5 5 P1 0 P1 1 P5 6 P5 4 5 P0 6 P0 7 VC C P5 2 P0 P0 P0 3 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Z86C64 68-Pin PLCC Pin Assignments 7 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y PIN DESCRIPTION (Continued) Z86C64 68-Pin PLCC Pin Identification Pin # Symbol Function Direction Pin # Symbol Function 1-2 3 4 5 6 P44-P43 VCC P45 XTAL2 XTAL1 Port 4, Pins 3,4 Power Supply Port 4, Pin 5 Crystal, Oscillator Clock Crystal, Oscillator Clock In/Output Input In/Output Output Input 24-31 32 33-36 37-38 P07-P00 VCC P55-P52 P11-P10 Port 0, Pins 0,1,2,3,4,5,6,7 In/Output Power Supply Input Port 5, Pins 2,3,4,5 In/Output Port 1, Pins 0,1 In/Output 7 8 9 10 11 P37 P30 /RESET R//W /P0DS Port 3, Pin 7 Port 3, Pin 0 Reset Read/Write Port 0 Data Strobe Output Input Input Output Output 39-40 41-46 47-48 49 50 P56-P57 P17-P12 P63-P62 P34 P33 Port 5, Pins 6,7 Port 1, Pins 2,3,4,5,6,7 Port 6, Pins 3,2 Port 3, Pin 4 Port 3, Pin 3 In/Output In/Output In/Output Output Input 12 13-14 15 16 17 /DS Data Strobe P47-P46 Port 4, Pins 6,7 /P1DS Port 1, Data Strobe /AS Address Strobe /DTIMER DTIMER Output In/Output Output Output Input 51 52 53 54-55 56-57 GND /SYNC SCLK P21-P20 P60-P61 Ground Synchronization System Clock Port 2, Pins 0,1 Port 6, Pins 1,0 Input Output Output In/Output In/Output 18 19 20 21 22-23 P35 /ROMless GND P32 P51-P50 Output Input Input Input In/Output 58-63 64-65 66 67 68 P27-P22 P41-P40 P31 P36 P42 Port 2, Pins 2,3,4,5,6,7 Port 4, Pins 0,1 Port 3, Pin 1 Port 3, Pin 6 Port 4, Pin 2 In/Output In/Output Input Output In/Output 8 Port 3, Pin 5 ROM/ROMless control Ground Port 3, Pin 2 Port 5, Pins 0,1 Direction Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y ABSOLUTE MAXIMUM RATINGS Symbol Description Min Max Units VCC TSTG TA Supply Voltage* –0.3 Storage Temp –65 Oper Ambient Temp † +7.0 +150 † V C Notes: * Voltages on all pins with respect to GND. † See ordering information Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Test Load). From Output Under Test I 150 pF Test Load Diagram 9 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y DC ELECTRICAL CHARACTERISTICS Z86C63 Sym Parameter TA = 0°C to +70°C Min Max VCH VCL Max Input Voltage Clock Input High Voltage Clock Input Low Voltage 0.85 VCC VSS – 0.3 VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage 2 VSS – 0.3 2.4 VOH VOH VOL VOL VOL VOL VRH Output High Voltage VCC – 100 mV Output High Voltage (Low EMI) 2.4 Output Low Voltage 0.4 Output Low Voltage (Low EMI) 0.4 Output Low Voltage 0.6 Output Low Voltage (Low EMI) 0.6 Reset Input High Voltage 0.85 VCC VCC + 0.3 VRl IIL IOL Reset Input Low Voltage Input Leakage Output Leakage IIR ICC ICC ICC ICC1 ICC1 ICC2 IALL Reset Input Current Supply Current (Standard Mode) Supply Current (Standard Mode) Supply Current (Low EMI) Standby Current (Standard Mode) Standby Current (Low EMI) Standby Current Auto Latch Low Current –14 –0.3 –2 –2 7 VCC + 0.3 0.8 VCC + 0.3 0.2 VCC 0.2 VCC 2 2 –180 35 40 6.0 15 1.6 10 14 Notes: [1] All inputs driven to either 0V or VCC, outputs floating. [2] VCC = 3.0V to 3.6V [3] VCC = 4.5V to 5.5V [4] /Reset pin must be a maximum of VCC + 0.3V. 10 TA = –40°C to +105°C Min Max 0.85 VCC VSS – 0.3 2 VSS – 0.3 2.4 Typical at 25°C Units 7 VCC + 0.3 0.8 V V V [4] IIN < 250 µA Driven by External Clock Generator Driven by External Clock Generator VCC + 0.3 0.2 VCC V V V IOH = –2.0 mA VCC – 100 mV 0.85 VCC 0.4 0.4 0.6 0.6 VCC + 0.3 V V V V V V V –0.3 –2 –2 0.2 VCC 2 2 V µA µA 2.4 –180 35 40 15 –20 Conditions 20 20 24 30 4.0 4.5 0.8 5 5 µA mA mA mA mA mA µA µA IOH = –100 µA IOH = –0.5 mA IOL = +5.0 mA [3] IOL = +2.0 mA [3] IOL = +4.0 mA [2] IOL = +1.0 mA [2] VIN = 0 V, VCC VIN = 0 V, VCC VRL = 0 V [1] @ 16 MHz [1] @ 20 MHz @ 4 MHz [1] HALT Mode VIN = 0 V, VCC @ 16 MHz @ 4 MHz [1] STOP Mode VIN = 0 V, VCC Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y AC CHARACTERISTICS R//W 13 12 Port 0, /DM 16 3 18 Port 1 A7 - A0 1 D7 - D0 IN 9 2 /AS 8 11 4 5 /DS (Read) 6 17 10 Port 1 A7 - A0 D7 - D0 OUT 14 15 7 /DS (Write) 17 External I/O or Memory Read/Write 11 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y AC CHARACTERISTICS External I/O or Memory Read and Write Timing Z86C63/64 (16 MHz—Standard Mode Only[4]) TA = 0°C to +70°C 16 MHz Min Max TA = –40°C to +105°C 16 MHz Min Max 25 35 25 35 No Symbol Parameter 1 2 3 4 5 TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) Address Valid to /AS rise Delay /AS rise to Address Float Delay /AS rise to Read Data Req’d Valid /AS Low Width Address Float to /DS fall 40 0 6 7 8 9 10 TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) /DS (Read) Low Width /DS (Write) Low Width /DS fall to Read Data Req’d Valid Read Data to /DS rise Hold Time /DS rise to Address Active Delay 80 75 0 50 11 12 13 14 15 TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) /DS rise to /AS fall Delay R//W Valid to /AS rise Delay /DS rise to R//W Not Valid Write Data Valid to /DS fall (Write) Delay /DS rise to Write Data Not Valid Delay 35 25 35 25 35 16 17 18 TdA(DR) TdAS(DS) TdDM(AS) Address Valid to Read Data Req’d Valid /AS rise to /DS fall Delay /DM Valid to /AS rise Delay 45 25 Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. [4] Low EMI is not selected. Standard Test Load All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0. 12 Units Notes ns ns ns ns ns [2,3] [2,3] [1,2,3] [2,3] 80 75 0 50 ns ns ns ns ns [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] 35 25 35 25 35 ns ns ns ns ns [2,3] [2,3] [2,3] [2,3] [2,3] ns ns ns [1,2,3] [2,3] [2,3] 150 150 40 0 135 135 210 210 45 25 Clock Dependent Formulas Number Symbol Equation 1 2 3 4 TdA(AS) TdAS(A) TdAS(DR) TwAS 0.40 TpC + 0.32 0.59 TpC – 3.25 2.83 TpC + 6.14 0.66 TpC – 1.65 6 7 8 10 TwDSR TwDSW TdDSR(DR) TdDS(A) 2.33 TpC – 10.56 1.27 TpC + 1.67 1.97 TpC – 42.5 0.8 TpC 11 12 13 14 TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) 0.59 TpC – 3.14 0.4 TpC 0.8 TpC – 15 0.4 TpC 15 16 17 18 TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) 0.88 TpC – 19 4 TpC – 20 0.91 TpC – 10.7 0.9 TpC – 26.3 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y AC CHARACTERISTICS External I/O or Memory Read and Write Timing Z86C63/64 (20 MHz—Standard Mode Only[4]) TA = 0°C to +70°C 20 MHz Min Max TA = –40°C to +105°C 20 MHz Min Max 15 25 25 35 No Symbol Parameter 1 2 3 4 5 TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) Address Valid to /AS rise Delay /AS rise to Address Float Delay /AS rise to Read Data Req’d Valid /AS Low Width Address Float to /DS fall 30 0 6 7 8 9 10 TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) /DS (Read) Low Width /DS (Write) Low Width /DS fall to Read Data Req’d Valid Read Data to /DS rise Hold Time /DS rise to Address Active Delay 65 55 0 40 11 12 13 14 15 TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) /DS rise to /AS fall Delay R//W Valid to /AS rise Delay /DS rise to R//W Not Valid Write Data Valid to /DS fall (Write) Delay /DS rise to Write Data Not Valid Delay 25 20 25 20 25 16 17 18 TdA(DR) TdAS(DS) TdDM(AS) Address Valid to Read Data Req’d Valid /AS rise to /DS fall Delay /DM Valid to /AS rise Delay 35 15 Units Notes ns ns ns ns ns [2,3] [2,3] [1,2,3] [2,3] 65 55 0 40 ns ns ns ns ns [1,2,3] [1,2,3] [1,2,3] [2,3] [2,3] 25 20 25 20 25 ns ns ns ns ns [2,3] [2,3] [2,3] [2,3] [2,3] ns ns ns [1,2,3] [2,3] [2,3] 120 120 30 0 105 105 150 150 35 15 Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] See clock cycle dependent characteristics table. [4] Low EMI is not selected. Standard Test Load All timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0. 13 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y AC CHARACTERISTICS Additional Timing Diagram 3 1 Clock 2 2 3 7 7 TIN 4 5 6 IRQN 8 9 Additional Timing AC CHARACTERISTICS Additional Timing Table Z86C63 (Standard Mode Only) No Symbol Parameter TA = 0°C to +70°C 20/16 MHz Min Max 1 2 3 4 5 TpC TrC,TfC TwC TwTinL TwTinH Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width 50/62.5 1000 10 25/31 75 5 TpC 50/62.5 1000 10 25/31 75 5 TpC ns ns ns ns ns [1] [1] [1] [2] [2] 6 7 8a 8b 9 TpTin TrTin,TfTin TwIL TwIL TwIH Timer Input Period Timer Input Rise and Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times 8 TpC 100 70 5 TpC 5 TpC 8 TpC 100 50 5 TpC 5 TpC ns ns ns ns ns [2] [2] [2,4] [2,5] [2,3] Notes: [1] Clock timing references use 0.85VCC for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31). [5] Interrupt request through Port 30. 14 TA = –40°C to +105°C 20/16 MHz Min Max Units Notes Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y AC CHARACTERISTICS Additional Timing Table Z86C63 (Low EMI Mode Only) TA = 0°C to +70°C 4 MHz Min Max No Symbol Parameter 1 2 3 4 5 TpC TrC,TfC TwC TwTinL TwTinH Input Clock Period Clock Input Rise & Fall Times Input Clock Width Timer Input Low Width Timer Input High Width 125 75 3 TpC 6 7 8a 8b 9 TpTin TrTin,TfTin TwIL TwIL TwIH Timer Input Period Timer Input Rise and Fall Times Interrupt Request Input Low Times Interrupt Request Input Low Times Interrupt Request Input High Times 4 TpC 100 70 3 TpC 3 TpC 250 DC 10 TA = –40°C to +105°C 4 MHz Min Max 250 DC 10 Units Notes 125 75 3 TpC ns ns ns ns ns [1] [1] [1] [2] [2] 4 TpC 100 50 3 TpC 3 TpC ns ns ns ns ns [2] [2] [2,4] [2,5] [2,3] Notes: [1] Clock timing references use 0.85VCC for a logic 1 and 0.8V for a logic 0. [2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0. [3] Interrupt references request through Port 3. [4] Interrupt request through Port 3 (P33-P31). [5] Interrupt request through Port 30. 15 Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y AC CHARACTERISTICS Handshake Timing Diagrams Data In Data In Valid 1 Next Data In Valid 2 3 /DAV (Input) Delayed DAV 4 5 RDY (Output) 6 Delayed RDY Input Handshake Timing Data Out Valid Data Out Next Data Out Valid 7 /DAV (Output) Delayed DAV 8 9 11 10 RDY (Input) Delayed Output Handshake Timing 16 RDY Z86C63/64 CPS DC-5461-02 P R E L I M I N A R Y AC ELECTRICAL CHARACTERISTICS Handshake Timing Table Z86C63 TA = 0°C to +70°C 20/16 MHz Min Max TA = –40°C to +105°C 20/16 MHz Min Max Data Direction No Symbol Parameter 1 2 3 4 5 TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) Data In Setup Time Data In Hold Time Data Available Width DAV Fall to RDY Fall Delay DAV Rise to RDY Rise Delay 0 145 110 115 115 0 145 110 115 115 IN IN IN IN IN 6 7 8 9 10 11 TdRDY0(DAV) TdDO(DAV) TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) RDY Rise to DAV Fall Delay Data Out to DAV Fall Delay DAV Fall to RDY Fall Delay RDY Fall to DAV Rise Delay RDY Width RDY Rise to DAV Fall Delay 0 TpC 0 115 110 115 0 TpC 0 115 110 115 IN OUT OUT OUT OUT OUT © 1993, 1994, 1995, 1996, 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com 17