PCI7410 www.ti.com SLLA247 – JULY 2006 PC Card, UltraMedia™ and Integrated 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller FEATURES • • • • • • • • • • • • • • • • • • • • • • PC Card Standard 8.0 compliant PCI Bus Power Management Interface Specification 1.1 compliant Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant PCI Local Bus Specification Revision 2.3 compliant PC 98/99 and PC2001 compliant Compliant with the PCI Bus Interface Specification for PCI-to-CardBus Bridges Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus and IEEE Std 1394a-2000 Fully compliant with 1394 Open Host Controller Interface Specification 1.1 1.8-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.8-V core VCC Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments Supports PC Card or CardBus with hot insertion and removal Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus Supports serialized IRQ with PCI interrupts Programmable multifunction terminals Many interrupt modes supported Serial ROM interface for loading subsystem ID and subsystem vendor ID ExCA-compatible registers are mapped in memory or I/O space Intel 82365SL–DF register compatible Supports ring indicate, SUSPEND, and PCI CCLKRUN protocol and PCI bus Lock (LOCK) Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals • • • • • • • • • • • • • • Fully interoperable with FireWire™ and i.LINK™ implementations of IEEE Std 1394 Compliant with Intel Mobile Power Guideline 2000 Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down, ultralow-power sleep mode Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s Cable ports monitor line conditions for active connection to remote node Cable power presence monitoring Separate cable bias (TPBIAS) for each port Physical write posting of up to three outstanding transactions PCI burst transfers and deep FIFOs to tolerate large host latency External cycle timer control for customized synchronization Extended resume signaling for compatibility with legacy DV components PHY-Link logic performs system initialization and arbitration functions PHY-Link encode and decode functions included for data-strobe bit level encoding PHY-Link incoming data resynchronized to local clock Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UltraMedia is a trademark of Texas Instruments. FireWire is a trademark of Apple Computer, Inc.. i.LINK is a trademark of Sony Corporation of America. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated PCI7410 www.ti.com SLLA247 – JULY 2006 • • • • • Node power class information signaling for system power management Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features Isochronous receive dual-buffer mode Out-of-order pipelining for asynchronous transmit requests Register access fail interrupt when the PHY SCLK is not active • • • • PCI power-management D0, D1, D2, and D3 power states Initial bandwidth available and initial channels available registers PME support per 1394 Open Host Controller Interface Specification Advanced submicron, low-power CMOS technology DESCRIPTION The Texas Instruments PCI7410 device is an integrated single-socket UltraMedia™ PC Card controller with an IEEE 1394 open host controller link-layer controller (LLC) and two-port 1394 PHY. The PCI7410 controller also includes a dedicated interface that can be used as a Secure Digital (SD)/MultiMediaCard (MMC), or Memory Stick socket. This high performance integrated solution provides the latest in PC Card, IEEE 1394, and UltraMedia™ technology. The PCI7410 CardBus controller is a four-function, 33-MHz PCI device compliant with the PCI Local Bus Specification. Function 0 provides a PC Card socket controller compliant with the latest PC Card Standards. Function 1 provides a dedicated socket for either SD/MMC or Memory Stick. Function 2 of the PCI7410 controller is an integrated IEEE 1394 OHCI host controller and two-port PHY. Function 3 is the interface to load the PCI7410 program RAM with firmware. The PCI7410 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports any combination of 16-bit and CardBus cards powered at 5 V or 3.3 V as required. There is no PCMCIA card and socket service software changes required to move systems from the existing CardBus socket controller to the PCI7410 controller. The PCI7410 controller is register compatible with the Intel 82365SL–DF ExCA controller and implements the host interface defined in the PC Card Standard. The PCI7410 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and the pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI7410 controller can be programmed to accept posted writes to improve bus utilization. All card signals are internally buffered to allow hot insertion and removal without external buffering. Function 1 of the PCI7410 controller provides a dedicated interface for either a Secure Digital (and MMC) or Memory Stick socket. Secure Digital cards are based upon the MultiMediaCard (MMC). SD is essentially a superset of MMC. The additional security features of the SD cards also allow their use in more-secure applications or in devices where content protection is essential. Memory Stick cards are about the size of a stick of gum and are 2,8 mm thick. Developed by Sony, there are two types of Memory Stick cards, the standard Memory Stick and MagicGate Memory Stick. MagicGate technology provides security to Memory Stick cards so that they can be used to store and protect copyrighted data. Function 2 of the PCI7410 controller is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The PCI7410 controller provides two 1394 ports that have separate cable bias (TPBIAS). The PCI7410 controller also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements. As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and non-prefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the PCI7410 controller is compliant with the PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide requirements. The PCI7410 controller supports the D0, D1, D2, and D3 power states. Function 3 of the PCI7410 controller is the interface to load the PCI7410 program RAM with firmware. This function provides an I/O window that a software driver uses to load the PCI7410 firmware into the internal RAM. 2 Submit Documentation Feedback PCI7410 www.ti.com SLLA247 – JULY 2006 The PCI7410 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the 1394 data. The PCI7410 controller provides physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The PCI7410 controller also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus-holding buffers. The PCI7410 PHY-layer provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PCI7410 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals that control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization of the received data. Data bits to be transmitted through the cable ports are received from the integrated LLC and are latched internally in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair A (TPA) cable pair(s). Various implementation specific functions and general-purpose inputs and outputs are provided through several multifunction terminals. These terminals present a system with options, such as PCI LOCK and parallel IRQs. ACPI-complaint general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs. The PCI7410 controller is compliant with the latest PCI Bus Power Management Specification, and provides several low-power modes, which enable the host power system to further reduce power consumption. The PCI7410 controller also has a four-pin interface compatible with both the TI TPS2211 and TPS2221 power switches. An advanced CMOS process achieves low power consumption and allows the PCI7410 controller to operate at PCI clock rates up to 33 MHz. NOTE: This product is for high-volume PC applications only. For a complete datasheet or more information contact [email protected]. Submit Documentation Feedback 3 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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