CM3196 2A Sink/Source DDR-I, -II Bus Termination Regulator Features Product Description • • • • • • • • The CM3196 is a sinking and sourcing regulator specifically designed for DDR-I, -II VTT bus termination. The output voltage accurately tracks VDDQ/2. For DDR-I it can source and sink current up to 2A with a load regulation of 0.5%. This current adequately serves both single and dual channel DDR-I memory systems. For power conscious notebook applications, the CM3196 also operates from a VDDQ of 1.5V or 1.8V with less current drive. For DDR-II applications, the CM3196 provides up to 0.6A at 0.9V to drive the memory controller VTT. • • Ideal for DDR-I, -II VTT applications Sinks and sources 2A for DDR-I, 0.6A for DDR-II Shutdown input to support ACPI states Operates down to 1.5V input voltage Integrated power MOSFETs Overcurrent protection Over temperature protection Excellent accuracy VTT = VREF ± 30mV VTT = VDDQ/2 ± 2% 8-pin SOIC or PSOP package Lead-free versions available Applications • • • DDR-I, -II memory termination Active termination buses Graphics card memory termination For boards which support Suspend to RAM (STR) functionality, the CM3196 provides a Shutdown (SD) pin. When SD is set low, VTT will be in tri-state mode, causing the output to go high impedance. In this mode, CM3196 power is saved by significantly reducing the quiescent current. VREF voltage remains VDDQ/2. The CM3196 provides overcurrent and over temperature protection. These features protect the chip from excessive heating due to high current and high temperature. The CM3196 is housed in an 8-pin SOIC or PSOP package and is available with optional lead-free finishing. Simplified Electrical Schematic VDDQ PVIN 50K AVIN SD Over Temp Over Current Reference Driver OUT Buffer VTT IN 50K VREF VSENSE GND © 2004 California Micro Devices Corp. All rights reserved. 04/22/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 1 CM3196 PACKAGE / PINOUT DIAGRAM TOP VIEW GND SD 1 8 2 7 VSENSE V REF 3 6 4 5 TOP VIEW VTT PVIN AVIN VDDQ GND SD 1 VSENSE VREF 3 8-lead SOIC VTT PV IN AV IN VDDQ 8 2 7 GND 4 6 5 8-lead PSOP Note: This drawing is not to scale. PIN DESCRIPTIONS LEAD(S) NAME 1 GND DESCRIPTION 2 SD 3 VSENSE Feedback from VTT input 4 VREF Reference output, VDDQ/2 5 VDDQ VDDQ input 6 AVIN Analog circuit power input 7 PVIN Power transistor input 8 VTT Output Ground Shutdown input, active low Ordering Information PART NUMBERING INFORMATION Standard Finish Lead-free Finish Ordering Part Ordering Part Package Number1 Part Marking Number1 Part Marking 8 SOIC-8 CM3196-12SN CM3196-12SN CM3196-12SM CM3196-12SM 8 PSOP-8 CM3196-12SB CM3196-12SB CM3196-12SH CM3196-12SH Pins Note 1: Parts are shipped in Tape & Reel form unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 2 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 04/22/04 CM3196 Specifications ABSOLUTE MAXIMUM RATINGS PARAMETER RATING UNITS AVIN Operating Supply Voltage 7 V VDDQ Input Voltage 7 V Pin Voltages VTT Output Any other pins 7 7 V V Storage Temperature Range -40 to +150 °C Operating Temperature Range Ambient Junction -40 to +85 -40 to +150 °C °C Power Dissipation (See note 1) Internally Limited W Note 1: These devices must be derated based on thermal resistance at elevated temperatures. The device packaged in an 8-pin SOIC package must be derated at θ JA = 151°C/W and the 8-pin PSOP must be derated at θ JA = 43°C/W. © 2004 California Micro Devices Corp. All rights reserved. 04/22/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 3 CM3196 Specifications (cont’d) DDR-I Features STANDARD OPERATING CONDITIONS VALUE UNITS VDDQ PARAMETER 2.5 V AVIN 2.5 V PVIN 2.5 V Ambient Operating Temperature -40 to +85 °C CVOUT 220 +20% µF ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL VIN PARAMETER CONDITIONS Input Voltage Range PVIN pin AVIN pin MIN TYP MAX UNITS 2.2 2.2 2.5 2.5 AVIN 5.5 V V ICC AVIN Quiescent Current ITT = 0A 450 µA ICCSD AVIN Quiescent Current in Shut Down VSD = logic "0" 115 µA VTT VREF VTT Output Voltage PVIN = 2.5V PVIN = 1.8V PVIN = 1.5V ILOAD = 0 to 2A or ILOAD = -2A to 0A ILOAD = 0 to 0.75A or ILOAD = -0.75A to 0A ILOAD = 0 to 0.3A or ILOAD = -0.3A to 0A 1.225 1.225 1.225 1.250 1.250 1.250 1.275 1.275 1.275 V V V Output Reference Voltage VDDQ = 2.5V, IREF = 0A 1.225 1.250 1.275 V 30 mV VOSVTT Output Offset from V REF ZREF VREF Output Impedance ZVDDQ -30 5 kΩ VDDQ Input Impedance 100 kΩ ILIM VTT Current Limit 2.5 A VSD Shutdown Logic Logic "1" Level Logic "0" Level TDISABLE THYST IREF = -5µA to 5µA 1.5 0.4 Shutdown Temperature Thermal Hysteresis 150 30 V V °C °C Note 1: Operating characteristics are over Standard Operating Conditions unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 4 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 04/22/04 CM3196 Specifications (cont’d) DDR-II Features STANDARD OPERATING CONDITIONS VALUE UNITS VDDQ PARAMETER 1.8 V AVIN 3.3 V PVIN 1.8 V Ambient Operating Temperature -40 to +85 °C CVOUT 220 +20% µF ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) SYMBOL VIN PARAMETER CONDITIONS Input Voltage Range PVIN pin AVIN pin MIN TYP MAX UNITS 1.5 2.2 1.8 3.3 AVIN 5.5 V V ICC AVIN Quiescent Current ITT = 0A 450 µA ICCSD AVIN Quiescent Current in Shut Down VSD = logic "0" 115 µA VTT VREF VTT Output Voltage PVIN = 1.8V PVIN = 1.5V AVIN > 2.2V, PVIN > 2.2V Output Reference Voltage VOSVTT Output Offset from V REF ZREF VREF Output Impedance ZVDDQ ILOAD = 0 to 0.6A or ILOAD = -0.6A to 0A ILOAD = 0 to 1.2A or ILOAD = -1.2A to 0A 0.882 0.882 0.882 0.9 0.9 0.9 0.918 0.918 0.918 V V V VDDQ = 1.8V, IREF = 0A 0.882 0.9 0.918 V 30 mV ILOAD = 0 to 0.3A or ILOAD = -0.3A to 0A -30 5 kΩ VDDQ Input Impedance 100 kΩ ILIM VTT Current Limit 2.5 A VSD Shutdown Logic Logic "1" Level Logic "0" Level TDISABLE THYST IREF = -5µA to 5µA 1.5 V V 0.4 Shutdown Temperature Thermal Hysteresis 150 30 °C °C Note 1: Operating characteristics are over Standard Operating Conditions unless otherwise specified. © 2004 California Micro Devices Corp. All rights reserved. 04/22/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 5 CM3196 Performance Information Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 1. Output Voltage with Supply (VDDQ = 2.5V) Figure 3. Load Regulation (Sink) Figure 2. Reference Voltage with Supply (VDDQ = 2.5V) Figure 4. Load Regulation (Source) © 2004 California Micro Devices Corp. All rights reserved. 6 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 04/22/04 CM3196 Performance Information (cont’d) Typical DC Characteristics (nominal conditions unless otherwise specified) Figure 5. Over Current Limit (Sink) Figure 7. Over Current Limit (Source) Figure 6. Supply Current with Supply Voltage © 2004 California Micro Devices Corp. All rights reserved. 04/22/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 7 CM3196 Performance Information (cont’d) Typical Transient Characteristics (nominal conditions unless otherwise specified) Figure 8. Load Transient (0A to 2.0A Sink) Figure 9. Line Transient (0A to 2.0A Source) © 2004 California Micro Devices Corp. All rights reserved. 8 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 04/22/04 CM3196 Performance Information (cont’d) Typical Thermal Characteristics The overall junction to ambient thermal resistance (θJA) for device power dissipation (PD) consists primarily of two paths in series. The first path is junction to case (θ JC) which is defined by the package style, and instantaneous current of 2A should not be exceeded 29% of the time. For CM3196-12SB, the maximum RMS current increases from 1.3A to 2.2A. Thus, the maximum continuous current can be 2A all the time. the second path is case to ambient (θCA) thermal resistance which is dependent on board layout. The final operating junction temperature for any set of conditions can be estimated by the following thermal equation: TJUNC = TA + PD (θ JC) + PD (θCA) = TA + PD (θJA) When a CM3196-12SN (SOIC) is mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading," the resulting θJA is 151°C/W. Based on the over temperature limit of 150°C with an ambient of 85°C, the available power of this package will be: PD = (150°C -85°C) / 151°C/W = 0.43W For the CM3196-12SB (PSOP), θJA is 40°C/W and the available power for this package will be: PD = (150°C -85°C) / 40°C/W = 1.625W Figure 10. Duty Cycle vs. Ambient Temperature (ILOAD = 2A) DDR Memory Application Since the output voltage is 1.25V, and the device can either source current from VDD or sink current to Ground, the power dissipated in the device at any time is 1.25V times the current load. This means the maximum average RMS current (in either direction) is 0.344A for CM3196-12SN and 1.3A for CM3196-12SB. The maximum instantaneous current is specified at 2A, so this condition should not be exceeded 17% and 65% of the time for CM3196-12SN and CM3196-12SB, respectively. It is highly unlikely in the use of DDR memory that this would occur, because it means the DDR memory outputs are either all high or all low for 17% (SOIC) and 65% (PSOP) of the time. If the ambient temperature is 40°C instead of 85°C, which is typically the maximum in most DDR memory applications, the power dissipated (PD) can be 0.73W for CM3196-12SN and 2.75W for CM3196-12SB. So the maximum average RMS current increases from 0.42A to 0.58A for CM3196-12SN and maximum Figure 11. Duty Cycle vs. Output Current (Temp=70°C) © 2004 California Micro Devices Corp. All rights reserved. 04/22/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 9 CM3196 Performance Information (cont’d) Typical Thermal Characteristics (cont’d) The theoretical calculations of these relationships show the safe operating area of the CM3196 in the SOIC package. Thermal characteristics were measured using a double-sided board with two square inches of copper area connected to the GND pins for "heat spreading." Measurements showing performance up to a junction temperature of 150°C were performed under light load conditions (5mA). This allows the ambient temperature to be representative of the internal junction temperature. Note: The use of multi-layer board construction with separate ground and power planes will further enhance the overall thermal performance. Figure 13. Output Voltage vs. Ambient Temperature (ILOAD=5mA) Figure 12. Reference Voltage vs. Temperature Figure 14. Quiescent Current vs. Temperature © 2004 California Micro Devices Corp. All rights reserved. 10 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 04/22/04 CM3196 Application Information PCB Layout Considerations The CM3196-12SB has a heat spreader attached to the underneath of the PSOP-8 package in order for heat to be transferred easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during manufacturing, the heat will be transferred between the two pads. The drawing below shows the recommended PCB layout. Note that there are six vias on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can cause blockage of the solder. The ground and power planes should be at least 2 sq. in. of copper adjacent to the vias. It also helps if the chip is positioned away from the edge of the PCB, and not near other heat dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will properly couple the CM3196 package to maintain an ambient junction temperature (θJA) of around 40°C/W. Figure 15. Recommended Heat Sink PCB Layout SD VDDQ VDDQ AVIN AVIN PVIN PVIN CAVIN 47µF VREF VREF SD CVREF 0.1µF VSENSE GND VTT VTT CVout 220µF CPVIN 47µF Figure 16. Typical Application Circuit © 2004 California Micro Devices Corp. All rights reserved. 04/22/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 11 CM3196 Mechanical Details The CM3196 is available in an 8-lead SOIC and PSOP package. Mechanical Package Diagrams SOIC-8 Mechanical Specifications TOP VIEW Dimensions for CM3196 devices packaged in 8-pin SOIC packages are presented below. D 8 7 6 5 For complete information on the SOIC-8 package, see the California Micro Devices SOIC Package Information document. H Pin 1 Marking E PACKAGE DIMENSIONS Package SOIC Leads Dimensions 1 3 4 8 Millimeters Inches Min Max Min Max A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.19 0.150 0.165 e 2 1.27 BSC SIDE VIEW A A1 SEATING PLANE B END VIEW 0.050 BSC H 5.80 6.20 0.228 0.244 L 0.40 1.27 0.016 0.050 # per tube 100 pieces* # per tape and reel 2500 pieces e C L Controlling dimension: inches Package Dimensions for SOIC-8 * This is an approximate number which may vary. © 2004 California Micro Devices Corp. All rights reserved. 12 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 04/22/04 CM3196 Mechanical Details PSOP-8 Mechanical Specifications Dimensions for CM3196 devices packaged in 8-pin PSOP packages with an intagrated heatslug are presented below. Mechanical Package Diagrams TOP VIEW For complete information on the PSOP-8 package, see the California Micro Devices PSOP-8 Package Information document. D 8 PACKAGE DIMENSIONS Package H 6 5 E Pin 1 Marking PSOP-8 Leads Dimensions 7 8 Millimeters Inches Min Max Min Max A 1.30 1.62 0.051 0.064 A1 0.03 0.10 0.001 0.004 B 0.33 0.51 0.013 0.020 C 0.18 0.25 0.007 0.010 D 4.83 5.00 0.190 0.197 E 3.81 3.99 0.150 0.157 e 1.02 1.52 0.040 0.050 H 5.79 6.20 0.228 0.244 L 0.41 1.27 0.016 0.050 x** 3.56 4.06 0.130 0.150 y** 2.29 2.79 0.090 0.110 # per tube 100 pieces* # per tape and reel 2500 pieces 1 2 3 4 BOTTOM VIEW D 1 2 3 4 Heat Slug x H y E x/2 8 7 y/2 6 5 SIDE VIEW Controlling dimension: inches A A1 SEATING PLANE * This is an approximate number which may vary. e B ** Centered on package centerline. END VIEW C L Package Dimensions for PSOP-8 © 2004 California Micro Devices Corp. All rights reserved. 04/22/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com 13