AKM AK4340_10

[AK4340]
AK4340
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4340 offers the ideal features for consumer systems that require a 2Vrms audio output. Using
AKM's multi bit architecture for its modulator the AK4340 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4340 integrates the Switched Capacitor Filter (SCF)
increasing performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz
sampling rate make this part ideal for a wide range of applications including Set-top-box, DVD-Audio. The
AK4340 is offered in a space saving 16pin TSSOP package.
FEATURES
† Sampling Rate Ranging from 8kHz to 192kHz
† 128 times Oversampling (Normal Speed Mode)
† 64 times Oversampling (Double Speed Mode)
† 32 times Oversampling (Quad Speed Mode)
† 24-Bit 8 times FIR Digital Filter
† Switched Capacitor Filter with High Tolerance to Clock Jitter
† On chip Buffer with 2Vrms Single-ended output
† Digital De-emphasis Filter: 32kHz, 44.1kHz or 48kHz
† Soft Mute Function
† Digital Attenuator (Linear 256 Step)
† Audio interface format: 24Bit MSB justified, 24/20/16 LSB justified or
I2S compatible
† Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 512fs (Double Speed Mode)
128fs or 192fs (Quad Speed Mode)
† THD+N: -90dB
† Dynamic Range: 106dB
† Power supply: +4.5V to +5.5V (DAC), - 4.5V to - 13.2V (Output Buffer)
† Ta = - 20 to 85 °C
† Package: 16pin TSSOP (6.4mm x 5.0mm)
MCLK
P/S
GAIN
VDD
SMUTE/CSN
ACKS/CCLK
De-emphasis
Control
µP
Interface
VSS
Clock
Divider
HVEE
DIF0/CDTI
LRCK
BICK
SDTI
Audio
Data
Interface
ATT
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTL
ATT
8X
Interpolator
ΔΣ
Modulator
SCF
LPF
AOUTR
PDN
MS0501-E-01
2010/09
-1-
[AK4340]
■ Ordering Guide
-20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation board for AK4340
AK4340ET
AKD4340
■ Pin Layout
MCLK
1
16
GAIN
BICK
2
15
NC
SDTI
3
14
P/S
LRCK
4
13
VDD
PDN
5
12
VSS
SMUTE/CSN
6
11
HVEE
ACKS/CCLK
7
10
AOUTL
DIF0/CDTI
8
9
AOUTR
Top
View
MS0501-E-01
2010/09
-2-
[AK4340]
PIN / FUNCTION
No.
Pin Name
I/O
Function
Master Clock Input Pin
1
MCLK
I
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock Pin
3
SDTI
I
Audio Serial Data Input Pin
4
LRCK
I
L/R Clock Pin
Power-Down Mode Pin
5
PDN
I
When at “L”, the AK4340 is in the power-down mode and is held in reset. The
AK4340 must be reset once upon power-up.
Soft Mute Pin in parallel control mode
SMUTE
I
6
“H”: Enable, “L”: Disable
CSN
I
Chip Select Pin in serial control mode
Auto Setting Mode Pin in parallel control mode
ACKS
I
7
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CCLK
I
Control Data Clock Pin in serial control mode
Audio Data Interface Format Pin in parallel control mode
DIF0
I
8
CDTI
I
Control Data Input Pin in serial control mode
9
AOUTR
O
Rch Analog Output Pin
10
AOUTL
O
Lch Analog Output Pin
Output Buffer Negative Power Supply Pin
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
11
HVEE
10μF electrolytic cap.
12
VSS
Ground Pin
13
VDD
DAC Power Supply Pin
Parallel/Serial Select Pin (Internal pull-up pin)
14
P/S
I
“L”: Serial control mode, “H”: Parallel control mode
No connect
15
NC
No internal banding
(Note)
Output Gain Select Pin
16
GAIN
I
“L”: 0dB, “H”: +1.94dB
Note: Do not allow digital input pins except pull-up pin to float.
Note: Pin No.15 (NC) has no internal bonding and can be left Open, connected GND or VDD.
MS0501-E-01
2010/09
-3-
[AK4340]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
DAC
Output Buffer
Input Current (any pins except for supplies)
Input Voltage
Ambient Operating Temperature
Storage Temperature
Note 1. All voltages with respect to ground.
Symbol
VDD
HVEE
IIN
VIND
Ta
Tstg
min
-0.3
-14.0
-0.3
-20
-65
max
+6.0
0.3
±10
VDD+0.3
85
150
Units
V
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
DAC
Output Buffer
Note 1. All voltages with respect to ground.
Symbol
VDD
HVEE
min
+4.5
-13.2
typ
+5.0
-5.0
max
+5.5
-4.5
Units
V
V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0501-E-01
2010/09
-4-
[AK4340]
ANALOG CHARACTERISTICS
(Ta=25°C; VDD=+5.0VV; HVEE=-5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
(Note 2)
THD+N
fs=44.1kHz
0dBFS
-90
-84
dB
BW=20kHz
-60dBFS
-42
dB
fs=96kHz
0dBFS
-90
dB
BW=40kHz
-60dBFS
-39
dB
fs=192kHz
0dBFS
-90
dB
BW=40kHz
-60dBFS
-39
dB
Dynamic Range (-60dBFS with A-weighted)
(Note 3)
100
106
dB
S/N
(A-weighted)
(Note 4)
100
106
dB
Interchannel Isolation (1kHz)
90
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
DC Accuracy
Gain Drift
100
ppm/°C
Output Voltage
(Note 5) GAIN pin = “L”
1.85
2
2.15
Vrms
GAIN pin = “H”
2.35
2.5
2.65
Vrms
Load Capacitance
(Note 6)
25
pF
Load Resistance
5
kΩ
Power Supplies
Power Supply Current: (Note 7)
Normal Operation (PDN pin = “H”, fs≤96kHz)
22
30
mA
VDD
6
9
mA
HVEE
Normal Operation (PDN pin = “H”, fs=192kHz)
25
33
mA
VDD
6
9
mA
HVEE
Power-Down Mode (PDN pin = “L”) (Note 8)
10
100
VDD
μA
10
100
HVEE
μA
Note 2. Measured by Audio Precision (System Two). GAIN pin = “L”. Refer to the evaluation board manual regarding
the measurement results.
Note 3. 98dB at 16bit data
Note 4. S/N ration does not depend on the input data length
Note 5. Full-scale voltage (0dB). Output voltage is proportional to VDD voltage.
AOUT ([email protected] 0dB, GAIN = 0dB) = 2Vrms × VDD/5.
Note 6. When the output pin drives a capacitive load, a resistor should be added in series between output pin and
capacitive load.
Note 7. These values are supplied to VDD pin or HVEE pin.
Note 8. P/S pin is tied to VDD and the other all digital inputs including clock pins (MCLK, BICK and LRCK) are tied to
VDD or VSS.
MS0501-E-01
2010/09
-5-
[AK4340]
FILTER CHARACTERISTICS
(Ta = 25°C; VDD = +4.5 ∼ +5.5V, HVEE = -13.2 ∼ -4.5V; fs = 44.1kHz, DEM = OFF)
Parameter
Symbol
min
typ
max
Units
Digital filter
PB
0
20.0
kHz
Passband
±0.05dB (Note 9)
22.05
kHz
-6.0dB
Stopband
(Note 9)
SB
24.1
kHz
Passband Ripple
PR
dB
± 0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 10)
GD
19.3
1/fs
Digital Filter + LPF
Frequency Response 20.0kHz fs=44.1kHz
FR
dB
± 0.05
40.0kHz fs=96kHz
FR
dB
± 0.05
80.0kHz fs=192kHz
FR
dB
± 0.05
Note 9. The passband and stopband frequencies scale with fs (system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 10. Delay time caused by digital filtering. This time is from setting the 16/24bit data of both channels to input
register to the output of analog signal.
DC CHARACTERISTICS
(Ta=25°C; VDD = +4.5 ∼ +5.5V, HVEE = -13.2 ∼ -4.5V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
Input Leakage Current
(Note 11)
Iin
Note 11. P/S pin is pulled-up internally. (typ. 100kΩ)
MS0501-E-01
typ
-
max
0.8
± 10
Units
V
V
µA
2010/09
-6-
[AK4340]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD = +4.5 ∼ +5.5V, HVEE = -13.2 ∼ -4.5V)
Parameter
Symbol
min
typ
fCLK
2.048
11.2896
Master Clock Frequency
dCLK
40
Duty Cycle
LRCK Frequency
8
fsn
Normal Speed Mode
60
fsd
Double Speed Mode
120
fsq
Quad Speed Mode
45
Duty
Duty Cycle
Audio Interface Timing
BICK Period
tBCK
1/128fsn
Normal Speed Mode
tBCK
1/64fsd
Double Speed Mode
tBCK
1/64fsq
Quad Speed Mode
tBCKL
30
BICK Pulse Width Low
tBCKH
30
Pulse Width High
tBLR
20
BICK rising to LRCK Edge
(Note 12)
tLRB
20
LRCK Edge to BICK rising
(Note 12)
tSDH
SDTI Hold Time
20
tSDS
SDTI Setup Time
20
Control Interface Timing
tCCK
200
CCLK Period
tCCKL
80
CCLK Pulse Width Low
tCCKH
80
Pulse Width High
tCDS
40
CDTI Setup Time
tCDH
40
CDTI Hold Time
tCSW
150
CSN High Time
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
Reset Timing
tPD
150
PDN Pulse Width
(Note 13)
Note 12. BICK rising edge must not occur at the same time as LRCK edge.
Note 13. The AK4340 can be reset by bringing PDN pin = “L”.
MS0501-E-01
max
36.864
60
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2010/09
-7-
[AK4340]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Figure 2. Serial Interface Timing
MS0501-E-01
2010/09
-8-
[AK4340]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
Figure 3. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 4. WRITE Data Input Timing
tPD
PDN
VIL
Figure 5. Power-down Timing
MS0501-E-01
2010/09
-9-
[AK4340]
OPERATION OVERVIEW
■ System Clock
The AK4340 requires MCLK, BICK and LRCK external clocks. The master clock (MCLK) should be synchronized with
LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma
modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”: Register 00H), the
sampling speed is set by DFS0/1 (Table 1). The frequency of MCLK at each sampling speed is set automatically. (Table
2) After exiting reset (PDN pin = “↑”), the AK4340 is in Auto Setting Mode. In Auto Setting Mode (ACKS = “1”:
Default), as MCLK frequency is detected automatically (Table 3), and the internal master clock becomes the appropriate
frequency (Table 4), it is not necessary to set DFS0/1.
In parallel control mode, the sampling speed can be set by only ACKS pin. The internal DFS0 and DFS1 bits are fixed to
“0”. Therefore, when ACKS pin is “L”, the AK4340 operates in Normal Speed Mode. The AK4340 operates in Auto
Setting Mode at ACKS pin = “H”. In parallel control mode, the AK4340 does not support 128fs and 192fs of Double
Speed Mode.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4340 is in the normal operation
mode (PDN pin = “H”). If these clocks are not provided, the AK4340 may draw excess current and may fall into
unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4340 should be
reset by PDN pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4340 should be in
the power-down mode (PDN pin = “L”). After exiting reset at power-up etc., the AK4340 is in the power-down mode
until MCLK and LRCK are input.
DFS1
DFS0
0
0
1
0
1
0
Sampling Rate (fs)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Default
Table 1. Sampling Speed (Manual Setting Mode)
DFS1
DFS0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
Sampling
Speed
Normal
Double
Quad
LRCK
(kHz)
fs
32.0
44.1
48.0
88.2
96.0
176.4
192.0
MCLK(MHz)
128fs
11.2896
12.2880
22.5792
24.5760
192fs
16.9344
18.4320
33.8688
36.8640
256fs
8.1920
11.2896
12.2880
22.5792
24.5760
-
384fs
12.2880
16.9344
18.4320
33.8688
36.8640
-
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
1152fs
36.8640
-
BICK
(MHz)
64fs
2.0480
2.8224
3.0720
5.6448
6.1440
11.2896
12.2880
Table 2. System Clock Example (Manual Setting Mode)
MS0501-E-01
2010/09
- 10 -
[AK4340]
MCLK
1152fs
512fs
768fs
256fs
384fs
128fs
192fs
Sampling Speed
Normal (fs=32kHz Only)
Normal
Double
Quad
Table 3. Sampling Speed (Auto Setting Mode: Default at Serial control mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
256fs
22.5792
24.5760
-
MCLK (MHz)
384fs
512fs
16.3840
22.5792
24.5760
33.8688
36.8640
-
768fs
24.5760
33.8688
36.8640
-
1152fs
36.8640
-
Sampling
Speed
Normal
Double
Quad
Table 4. System Clock Example (Auto Setting Mode)
■ Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. In serial control mode, five serial data mode can be
selected by DIF2-0 bits. (See Table 5). In parallel control mode, two serial data mode can be selected by DIF0 pin. (See
Table 6) In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK. Mode
2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
DIF0
0
1
0
1
0
SDTI Format
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I2S Compatible
24bit LSB Justified
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 6
Figure 7
Figure 8
Figure 9
Figure 7
Default
Table 5. Audio Data Format in Serial control mode
Mode
2
3
DIF0
0
1
SDTI Format
24bit MSB Justified
24bit I2S Compatible
BICK
≥48fs
≥48fs
Figure
Figure 8
Figure 9
Table 6. Audio Data Format in Parallel control mode
MS0501-E-01
2010/09
- 11 -
[AK4340]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
1
0
5
14
4
15
3
2
16
1
17
0
31
15
0
14
6
5
14
1
4
15
3
16
2
1
17
0
31
15
14
0
1
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. Mode 1,4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 8. Mode 2 Timing
MS0501-E-01
2010/09
- 12 -
[AK4340]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 9. Mode 3 Timing
■ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always OFF.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Default
Table 7. De-emphasis Filter Control (Normal Speed Mode)
■ Output Volume
The AK4340 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 8.
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
8LRCK
2040LRCK
16LRCK
4080LRCK
Table 8. ATT Transition Time
MS0501-E-01
2010/09
- 13 -
[AK4340]
■ Output Gain Setting
Outputs level of AOUTL/AOUTR pin can be selected by GAIN pin.
GAIN pin
L
H
GAIN
0dB
+1.94dB
Output Level (VDD=5V)
2Vrms (typ)
2.5Vrms (typ)
Table 9. Output Level Setting
■ Soft Mute Operation
Soft mute operation is performed in digital domain. When the SMUTE bit (SMUTE pin) goes to “1”(“H”), the output
signal is attenuated by -∞ during ATT_DATA×ATT transition time (Table 8) from the current ATT level. When the
SMUTE bit (SMUTE pin) is returned to “0” (“L”), the mute is cancelled and the output attenuation gradually changes to
the ATT level during ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after
starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is
effective for changing the signal source without stopping the signal transmission.
SMUTE bit or
SMUTE pin
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
Notes:
(1) ATT_DATA×ATT transition time (Table 8). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
Figure 10. Soft Mute function
■ System Reset
The AK4340 should be reset once by bringing PDN pin = “L” upon power-up. The AK4340 is powered up and the
internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4340 is in the
power-down mode until MCLK and LRCK are input.
MS0501-E-01
2010/09
- 14 -
[AK4340]
■ Power-down
The AK4340 is placed in the power-down mode by bringing PDN pin “L” and the analog outputs are GND. Figure 11
shows an example of the system timing at the power-down and power-up.
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(2)
(3)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
DZFL/DZFR
External
MUTE
(6)
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
Figure 11. Power-down/up Sequence Example
MS0501-E-01
2010/09
- 15 -
[AK4340]
■ Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage and DZF pin goes to “H”. Figure 12 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
D/A In
(Digital)
“0” data
(1)
D/A Out
(Analog)
Normal Operation
Digital Block Power-down
GD
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK,LRCK,BICK
External
MUTE
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Figure 12. Reset Sequence Example
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[AK4340]
■ Mode Control Interface
Some function of the AK4340 can be controlled by pins (parallel control mode) shown in Table 10. The serial control
interface is enabled by the P/S pin = “L”. Internal registers may be written to 3-wire µP interface pins, CSN, CCLK and
CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”,
Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). The AK4340 latches the data on the
rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “↑”. The
clock speed of CCLK is 5MHz (max).
Function
Parallel control mode
Serial control mode
Double sampling mode at 128/192fs
X
De-emphasis
X
SMUTE
O
16/20/24bit LSB justified format
X
Table 10. Function list (O: available, X: not available)
O
O
O
O
PDN pin = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4340 should be
reset by PDN pin = “L”. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “01”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 13. Control I/F Timing
*The AK4340 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4340 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
■ Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
Notes:
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
ACKS
0
0
ATT7
ATT7
0
0
0
ATT6
ATT6
0
0
0
ATT5
ATT5
DIF2
DFS1
INVL
ATT4
ATT4
DIF1
DFS0
INVR
ATT3
ATT3
DIF0
DEM1
0
ATT2
ATT2
PW
DEM0
0
ATT1
ATT1
RSTN
SMUTE
0
ATT0
ATT0
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
MS0501-E-01
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[AK4340]
■ Register Definitions
Addr
00H
D7
D6
D5
D4
D3
D2
D1
D0
Control 1
Register Name
ACKS
0
0
DIF2
DIF1
DIF0
PW
RSTN
default
1
0
0
0
1
0
1
1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 5)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the settings of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr
01H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
Control 2
0
0
0
DFS1
DFS0
DEM1
DEM0
SMUTE
default
0
0
0
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 7)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal Speed Mode
01: Double Speed Mode
10: Quad Speed Mode
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise
occurs.
MS0501-E-01
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[AK4340]
Addr
02H
D7
D6
D5
D4
D3
D2
D1
D0
Control 3
Register Name
0
0
0
INVL
INVR
0
0
0
default
0
0
0
0
0
0
0
0
D6
ATT6
ATT6
1
D5
ATT5
ATT5
1
D4
ATT4
ATT4
1
D3
ATT3
ATT3
1
D2
ATT2
ATT2
1
D1
ATT1
ATT1
1
D0
ATT0
ATT0
1
INVR: Inverting Lch Output Polarity
0: Normal Output
1: Inverted Output
INVL: Inverting Rch Output Polarity
0: Normal Output
1: Inverted Output
Addr
03H
04H
Register Name
Lch ATT
Rch ATT
default
D7
ATT7
ATT7
1
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
MS0501-E-01
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[AK4340]
SYSTEM DESIGN
Figure 14and Figure 15 show the system connection diagram. An evaluation board (AKD4340) is available in order to
allow an easy study on the layout of a surround circuit.
Master Clock
1
MCLK
64fs
2
24bit Audio Data
3
fs
Reset & Power down
μP
Digital Ground
GAIN
16
BICK
NC
15
SDTI
P/S
14
4
LRCK
VDD
13
5
PDN
VSS
12
6
CSN
HVEE
11
7
CCLK
AOUTL
10
Lch Out
8
CDTI
AOUTR
9
Rch Out
AK4340
0.1u
10u
0.1u
+
+5V Analog Supply
+ 10u
Negative Analog Supply
Analog Ground
Figure 14. Typical Connection Diagram (Serial Control Mode, GAIN=0dB)
Master Clock
1
MCLK
64fs
2
24bit Audio Data
3
4
fs
Reset & Power down
Mode
Setting
Digital Ground
GAIN
16
BICK
NC
15
SDTI
P/S
14
LRCK
VDD
13
AK4340
0.1u
10u
+
+5V Analog Supply
VSS
12
HVEE
11
ACKS
AOUTL
10
Lch Out
DIF0
AOUTR
9
Rch Out
5
PDN
6
SMUTE
7
8
0.1u
+ 10u
Negative Analog Supply
Analog Ground
Figure 15. Typical Connection Diagram (Parallel Control Mode, GAIN=0dB)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except for pull-up pin must not be left floating.
MS0501-E-01
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[AK4340]
1. Grounding and Power Supply Decoupling
VDD, HVEE and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitor, especially 0.1μF ceramic capacitor for high frequency should be placed as near to VDD and HVEE as possible.
The differential Voltage between VDD and VSS pins set the analog output range.
Power-up sequence between VDD and HVEE is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the ground (VSS). The output signal range is typically 2Vrms
(@VDD=5V & GAIN pin = “L”). The phase of the analog outputs can be inverted channel independently by INVL/INVR
bits. The internal switched capacitor filter (SCF) and continuous time filter (CTF) attenuate the noise generated by the
delta-sigma modulator beyond the audio passband. If the noise generated by the delta-sigma modulator beyond the audio
band would be the problem, the 1st order filter is required. (See Figure 16)
The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The
ideal output is 0V(VSS) for 000000H (@24bit).
470
Analog
Out
AOUT
2.2n
Figure 16. External 1st order LPF Circuit Example
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
MS0501-E-01
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[AK4340]
PACKAGE
16pin TSSOP (Unit: mm)
1.1 (max)
*5.0±0.1
16
9
8
1
0.13
M
6.4±0.2
*4.4±0.1
A
0.65
0.22±0.1
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0501-E-01
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[AK4340]
MARKING
AKM
4340ET
XXYYY
1)
2)
3)
4)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 4340ET
Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD)
06/04/24
10/09/28
Revision
00
01
Reason
First Edition
Specification
Change
Page
Contents
22
PACKAGE
The package dimension was changed.
MS0501-E-01
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[AK4340]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS0501-E-01
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