AKM AKD4357

ASAHI KASEI
[AK4357]
AK4357
192kHz 24-Bit 6ch DAC with DSD Input
GENERAL DESCRIPTION
The AK4357 is six channels 24bit DAC corresponding to digital audio system. Using AKM's advanced
multi bit architecture for its modulator the AK4357 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4357 has full differential SCF outputs, removing the
need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The
AK4357 accepts 192kHz PCM data and 1-Bit DSD data, ideal for a wide range of applications including
DVD-Audio and SACD.
FEATURES
o Sampling Rate Ranging from 8kHz to 192kHz
o 24Bit 8 times Digital Filter with Slow roll-off option
o THD+N:
-90dB
o DR, S/N: 106dB
o High Tolerance to Clock Jitter
o Low Distortion Differential Output
o DSD Data input available
o Channel Independent Digital De-emphasis for 32, 44.1 & 48kHz sampling
o Zero Detect function
o Channel Independent Digital Attenuator with soft-transition (3 Speed
mode)
o Soft Mute
o 3-wire Serial Interface for Volume Control
o Master clock: 256fs, 384fs, 512fs or 768fs (PCM Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (PCM Double Speed Mode)
128fs or 192fs (PCM Quad Speed Mode)
512fs or 768fs (DSD Mode)
o Power Supply: 4.75 to 5.25V
o 48pin LQFP Package
DZF
LOUT1+
LOUT1-
SCF
DAC
ROUT1+
ROUT1-
SCF
DAC
LOUT2+
LOUT2-
SCF
DATT
Audio
I/F
MCLK
LRCK
BICK
SDTI1
DATT
PCM
DAC
SDTI2
SDTI3
DATT
ROUT2+
ROUT2-
SCF
DAC
DATT
LOUT3+
LOUT3-
SCF
DAC
DATT
ROUT3+
ROUT3-
SCF
DAC
DATT
Control
Register
MS0088-E-02
CDTI
DCLK
DSDL1
DSDR1
DSDL2
DSD
AK4357
CSN
CCLK
DSDR2
DSDL3
DSDR3
2002/07
- 1-
ASAHI KASEI
[AK4357]
n Ordering Guide
-40 ∼ +85°C
48LQFP
Evaluation Board for AK4357
AK4357VQ
AKD4357
LOUT3+
LOUT3-
ROUT3+
42
41
40
AVSS
ROUT243
37
ROUT2+
44
AVSS
LOUT245
ROUT3-
LOUT2+
46
38
ROUT147
39
ROUT1+
48
n Pin Layout
LOUT1-
1
36
AVSS
LOUT1+
2
35
AVDD
DZFL1
3
34
VREFH
DAFR1
4
33
DIF2
DZF23
5
32
DIF1
AK4357VQ
CAD0
6
31
DIF0
CAD1
7
30
DSDR3
Top View
19
20
21
22
23
24
CCLK
CDTI
CSN
DSDM
DCLK
NC
DSDL1
SMUTE
DSDR1
25
18
26
12
17
11
NC
LRCK
DVDD
SDTI3
DSDL2
16
27
15
10
SDTI2
DSDR2
MCLK
SDTI1
DSDL3
28
14
29
9
13
8
DVSS
PDN
BICK
PIN/FUNCTION
No.
1
2
3
4
5
6
7
Pin Name
LOUT1LOUT1+
DZFL1
DZFR1
DZF23
CAD0
CAD1
I/O
O
O
O
O
O
I
I
8
PDN
I
9
10
BICK
MCLK
I
I
Function
DAC1 Lch Negative Analog Output Pin
DAC1 Lch Positive Analog Output Pin
DAC1 Lch Zero Input Detect Pin
DAC1 Rch Zero Input Detect Pin
DAC2,3 Zero Input Detect Pin
Chip Address 0 Pin
Chip Address 1 Pin
Power-Down Mode Pin
When at “L”, the AK4357 is in the power-down mode and is held in reset.
The AK4357 should always be reset upon power-up.
Audio Serial Data Clock Pin
Master Clock Input Pin
An external TTL clock should be input on this pin.
MS0088-E-02
2002/07
- 2-
ASAHI KASEI
No.
11
12
Pin Name
DVDD
NC
[AK4357]
I/O
-
Function
Digital Power Supply Pin, +4.75∼ +5.25V
NC pin
No internal bonding
13
DVSS
Digital Ground Pin
14
SDTI1
I
DAC1 Audio Serial Data Input Pin
15
SDTI2
I
DAC2 Audio Serial Data Input Pin
16
SDTI3
I
DAC3 Audio Serial Data Input Pin
17
LRCK
I
L/R Clock Pin
18
SMUTE
I
Soft Mute Pin
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
19
CCLK
I
Control Data Clock Pin
20
CDTI
I
Control Data Input Pin
21
CSN
I
Chip Select Pin
22
DSDM
I
DSD Mode Enable Pin (Pull-down Pin)
“0”: PCM mode “1”: DSD mode
23
DCLK
I
DSD Clock Pin
24
NC
NC pin
No internal bonding
25
DSDL1
I
DAC1 DSD Lch Data Input Pin
26
DSDR1
I
DAC1 DSD Rch Data Input Pin
27
DSDL2
I
DAC2 DSD Lch Data Input Pin
28
DSDR2
I
DAC2 DSD Rch Data Input Pin
29
DSDL3
I
DAC3 DSD Lch Data Input Pin
30
DSDR3
I
DAC3 DSD Rch Data Input Pin
31
DIF0
I
Audio Data Interface Format 0 Pin
32
DIF1
I
Audio Data Interface Format 1 Pin
33
DIF2
I
Audio Data Interface Format 2 Pin
34
VREFH
I
Positive Voltage Reference Input Pin
35
AVDD
Analog Power Supply Pin, +4.75∼+5.25V
36
AVSS
Analog Ground Pin
37
AVSS
Analog Ground Pin
38
AVSS
Analog Ground Pin
39
ROUT3O
DAC3 Rch Negative Analog Output Pin
40
ROUT3+
O
DAC3 Rch Positive Analog Output Pin
41
LOUT3O
DAC3 Lch Negative Analog Output Pin
42
LOUT3+
O
DAC3 Lch Positive Analog Output Pin
43
ROUT2O
DAC2 Rch Negative Analog Output Pin
44
ROUT2+
O
DAC2 Rch Positive Analog Output Pin
45
LOUT2O
DAC2 Lch Negative Analog Output Pin
46
LOUT2+
O
DAC2 Lch Positive Analog Output Pin
47
ROUT1O
DAC1 Rch Negative Analog Output Pin
48
ROUT1+
O
DAC1 Rch Positive Analog Output Pin
Note: All input pins except pull-down pin should not be left floating.
MS0088-E-02
2002/07
- 3-
ASAHI KASEI
[AK4357]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1)
Parameter
Power Supplies
Analog
Digital
|AVSS-DVSS|
(Note 2)
Input Current (any pins except for supplies)
Analog Input Voltage
Digital Input Voltage
Ambient Operating Temperature
Storage Temperature
Note:
Symbol
A VDD
DVDD
∆ GND
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-0.3
-40
-65
max
6.0
6.0
0.3
±10
AVDD+0.3
DVDD+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
1. All voltages with respect to ground.
2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter
Power Supplies
Analog
(Note 3)
Digital
Voltage Reference
Note:
Symbol
A VDD
DVDD
VREF
min
4.75
4.75
AVDD-0.5
typ
5.0
5.0
-
max
5.25
5.25
AVDD
Units
V
V
V
1. All voltages with respect to ground.
3. The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0088-E-02
2002/07
- 4-
ASAHI KASEI
[AK4357]
ANALOG CHARACTERISTICS
(Ta=25 °C; AVDD, DVDD=5V; VREF=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; R L ≥ 4kΩ ; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
(Note 4)
THD+N
fs=44.1kHz
0dBFS
-90
-86
dB
BW=20kHz
fs=96kHz
0dBFS
-88
-84
dB
BW=40kHz
dB
fs=192kHz
0dBFS
-86
dB
BW=40kHz
dB
Dynamic Range (-60dBFS with A-weighted)
(Note 5)
100
106
dB
S/N
(A-weighted)
(Note 6)
100
106
dB
Interchannel Isolation (1kHz)
90
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
DC Accuracy
Gain Drift
100
ppm/°C
± 2.35
±2.5
± 2.65
Output Voltage
(Note 7)
Vpp
Load Resistance
(Note 8)
4
kΩ
Power Supplies
Power Supply Current (AVDD+DVDD)
Normal Operation (PDN = “H”, fs ≤96kHz)
50
75
mA
Normal Operation (PDN = “H”, fs=192kHz)
60
85
mA
Power-Down Mode (PDN = “L”)
(Note 9)
10
100
µA
Note:
4. Measured by Audio Precision System Two. Refer to the evaluation board manual.
5. 100dB at 16bit data.
6. S/N is independent of input bit length.
7. Fu ll scale voltage (0dB). Output voltage scales with the voltage of VREFH pin.
AOUT([email protected])=(AOUT+)-(AOUT-)=± 2.5Vpp*VREFH/5.0
8. For AC-load. 8kΩ for DC-load
9. All digital inputs including clock pins (MCLK, BICK and LRCK) are held DVDD or DVSS.
MS0088-E-02
2002/07
- 5-
ASAHI KASEI
[AK4357]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75 ∼ 5.25V; fs = 44.1kHz; DEM = OFF; SLOW=”0”; PCM Mode)
Parameter
Symbol
min
typ
max
Units
Digital filter
± 0.05dB (Note 9)
Passband
PB
0
20.0
kHz
-6.0dB
22.05
kHz
Stopband
(Note 10)
SB
24.1
kHz
± 0.02
Passband Ripple
PR
dB
Stopband Attenuation
SA
54
dB
Group Delay
(Note 11)
GD
19.1
1/fs
Digital Filter + SCF
± 0.2
Frequency Response 20.0kHz Fs=44.1kHz
FR
dB
± 0.3
40.0kHz Fs=96kHz
FR
dB
80.0kHz
Fs=192kHz
FR
+0/ -0.6
dB
Notes : 10. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@ ±0.05dB), SB=0.546×fs.
11. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = “1”; PCM Mode)
Parameter
Symbol
min
PB
0
39.2
Typ
max
Units
18.2
8.1
-
kHz
kHz
kHz
± 0.005
dB
Digital Filter
± 0.04dB
Passband
(Note 12)
-3.0dB
Stopband
(Note 12)
SB
Passband Ripple
PR
Stopband Attenuation
SA
72
GD
-
19.1
-
1/fs
-
+0/ -5
+0/ -4
+0/ -5
-
dB
dB
dB
Group Delay
(Note 11)
dB
Digital Filter + SCF
Frequency Response
FR
FR
FR
Note: 12. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
20.0kHz
40.0kHz
80.0kHz
fs=44.kHz
fs=96kHz
fs=192kHz
DC CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75 ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout = -80µA)
VOH
DVDD-0.4
Low-Level Output Voltage (Iout = 80µA)
VOL
Input Leakage Current
(Note 13)
Iin
Note: 13. DSDM pin has internal pull-down devices, nominally 100k Ω .
MS0088-E-02
Typ
-
max
0.8
0.4
± 10
Units
V
V
V
V
µA
2002/07
- 6-
ASAHI KASEI
[AK4357]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.75 ∼ 5.25V; CL = 20pF)
Parameter
Symbol
Master Clock Frequency
fCLK
Duty Cycle
dCLK
min
2.048
40
LRCK Frequency
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
60
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
tBCK
1/128fs
Double/Quad Speed Mode
tBCK
1/64fs
BICK Pulse Width Low
tBCKL
30
Pulse Width High
tBCKH
30
BICK “↑ ” to LRCK Edge
(Note 13)
tBLR
20
LRCK Edge to BICK “↑ ”
(Note 13)
tLRB
20
SDTI Hold Time
tSDH
20
SDTI Setup Time
tSDS
20
DSD Audio Interface Timing
DCLK Period
tDCK
1/64fs
DCLK Pulse Width Low
tDCKL
160
Pulse Width High
tDCKH
160
DCLK Edge to DSDL/R
(Note 14)
tDDD
-20
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN High Time
tCSW
150
CSN “ ↓” to CCLK “↑ ”
tCSS
50
CCLK “↑ ” to CSN “↑ ”
tCSH
50
Reset Timing
PDN Pulse Width
(Note 15)
tPD
150
Notes : 13. BICK rising edge must not occur at the same time as LRCK edge.
14. DSD data transmitting device must meet this time.
15. The AK4357 can be reset by bringing PDN= “L”.
MS0088-E-02
Typ
11.2896
max
36.864
60
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2002/07
- 7-
ASAHI KASEI
[AK4357]
n Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDS
tSDH
VIH
SDTI
VIL
Audio Serial Interface Timing (PCM Mode)
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Normal Mode, DCKB = “0”)
MS0088-E-02
2002/07
- 8-
ASAHI KASEI
[AK4357]
tDCK
tDCKL
tDCKH
VIH
DCLK
VIL
tDDD
tDDD
VIH
DSDL
DSDR
VIL
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB = “0”)
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
CDTI
C1
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
CDTI
D3
D2
D1
D0
VIH
VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing
MS0088-E-02
2002/07
- 9-
ASAHI KASEI
[AK4357]
OPERATION OVERVIEW
n D/A Conversion Mode
The AK4357 can perform D/A conversion for both PCM data and DSD data. When DSD mode, DSD data can be input from
DCLK, DSDL1-3 and DSDR1-3 pins. When PCM mode, PCM data can be input from BICK, SDTI1-3 and LRCK pins.
PCM/DSD mode changes by DSDM pin or D/P bit, DSDM pin setting and D/P bit setting are ORed internal. When
PCM/DSD mode changes by DSDM pin or D/P bit, the AK4357 should be reset by RSTN bit, PW bit (PW1=PW2=PD3=”0”)
or PDN pin. It takes about 2/fs to 3/fs to change the mode.
DSDM pin
L
H
D/P bit
0
1
0
1
DAC Output
PCM
DSD
DSD
DSD
Table 1. DSD/PCM Mode Control
n System Clock
1) PCM Mode
The external clocks, which are required to operate the AK4357, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter
and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = “0”:
Register 00H), the sampling speed is set by DFS0/1(Table 2). The frequency of MCLK at each sampling speed is set
automatically. (Table 3~5). In Auto Setting Mode (ACKS = “1”: Default), as MCLK frequency is detected automatically
(Table 6), and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to set DFS0/1.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4357 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4357 may draw excess current and may fall into unpredictable
operation. This is because the dev ice utilizes dynamic refreshed logic internally. The AK4357 should be reset by PDN= ”L”
after threse clocks are provided. If the external clocks are not present, the AK4357 should be in the power-down mode
(PDN= ”L”). After exiting reset(PDN = “ ↑”) at power-up etc., the AK4357 is in the power-down mode until MCLK is input.
DSD interface signals (DCLK, DSDL1-3, DSDR1-3) are fixed to “H” or “L”.
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
8kHz~48kHz
0
1
Double Speed Mode
60kHz~96kHz
1
0
Quad Speed Mode
Default
120kHz~192kHz
Table 2. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
512fs
12.2880MHz 16.3840MHz
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
MS0088-E-02
2002/07
- 10 -
ASAHI KASEI
[AK4357]
LRCK
fs
88.2kHz
96.0kHz
128fs
11.2896MHz
12.2880MHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
BICK
64fs
5.6448MHz
6.1440MHz
384fs
33.8688MHz
36.8640MHz
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
176.4kHz
192.0kHz
MCLK
128fs
22.5792MHz
24.5760MHz
BICK
64fs
11.2896MHz
12.2880MHz
192fs
33.8688MHz
36.8640MHz
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
512fs
256fs
128fs
768fs
384fs
192fs
Sampling Speed
Normal
Double
Quad
Table 6. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
MCLK (MHz)
256fs
384fs
22.5792
33.8688
24.5760
36.8640
-
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
Sampling Speed
Normal
Double
Quad
Table 7. System Clock Example (Auto Setting Mode)
2) DSD Mode
The external clocks, which are required to operate the AK4357, are MCLK and DCLK. The master clock (MCLK) should be
synchronized with DSD clock (DCLK) but the phase is not critic al. The frequency of MCLK is set by DCKS bit.
All external clocks (MCLK, DCLK) should always be present whenever the AK4357 is in the normal operation mode
(PDN= ”H”). If these clocks are not provided, the AK4357 may draw excess current because the device utilizes dynamic
refreshed logic internally. The AK4357 should be reset by PDN= ”L” after threse clocks are provided. If the external clocks
are not present, the AK4357 should be in the power-down mode (PDN= ”L”). After exiting reset(PDN = “↑ ”) at power-up
etc., the AK4357 is in the power-down mode until MCLK is input. PCM interface signals (BICK, LRCK, SDTI1-3) are fixed to
“H” or “L”.
DCKS
MCLK
DCLK
0
512fs
64fs
1
768fs
64fs
Table 8. System Clock (fs=44.1kHz)
MS0088-E-02
2002/07
- 11 -
ASAHI KASEI
[AK4357]
n Audio Serial Interface Format
1) PCM Mode
When PCM mode, data is shifted in via the SDTI1-3 pins using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can
select five serial data modes . Initial value of DIF0-2 bits is“000”, each DIF0-2 bits is ORed with DIF0-2 pins. In all modes the
serial data is MSB-first, 2 ’s compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB
justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
DIF2
0
0
0
0
DIF1
0
0
1
1
4
1
0
DIF0
0
1
0
1
SDTI Format
16bit LSB Justified
20bit LSB Justified
24bit MSB Justified
24bit I2S Compatible
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
0
24bit LSB Justified
Table 9. Audio Data Formats
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15 14
6
1
0
5
14
4
15
3
16
2
17
1
0
31
15 14
0
6
5
14
1
4
15
3
16
2
17
1
0
31
15 14
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15 14
0
Don’t care
15 14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
23 22 21 20 19
0
Don’t care
19
0
22 21 20 19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
MS0088-E-02
2002/07
- 12 -
ASAHI KASEI
[AK4357]
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
0
1
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23 22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
1
23 22
0
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
2) DSD Mode
In case of DSD mode, DIF0-2 are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can invert the polarity of DCLK.
DCLK (64fs)
DCKB=1
DCLK (64fs)
DCKB=0
DSDL,DSDR
Normal
D0
DSDL,DSDR
Phase Modulation
D0
D1
D1
D2
D1
D2
D3
D2
D3
Figure 5. DSD Mode Timing
MS0088-E-02
2002/07
- 13 -
ASAHI KASEI
[AK4357]
n De -emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled with
DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off. When DSD
mode, DEM0-1 is invalid.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Default
Table 8. De-emphasis Filter Control (Normal Speed Mode)
n Output Volume
The AK4357 includes channel independent digital output volumes (ATT) with 128 levels at 0.5dB steps including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –63dB and mute. Transition time is set
by AST1-0 bits(Table12) When changing levels, transitions are executed via soft changes; thus no switching noise occurs
during these transitions.
ATT7-0
FFH
FEH
FDH
:
82H
81H
80H
:
02H
01H
00H
Attenuation Level
0dB
-0.5dB
-1.0dB
:
-62.5dB
-63.0dB
MUTE (-∞)
:
MUTE (-∞ )
MUTE (-∞ )
MUTE (-∞ )
Default
Table 11. Attenuation Level of Output Volume
Mode
0
1
2
3
ATS1
0
0
1
1
ATS0
0
1
0
1
ATT speed
1792/fs
896/fs
256/fs
256/fs
Default
Table 12. Transition time of output volume
In case Mode0, it takes 1792/ fs to transit from FFH(0dB) to 80H(MUTE). In case Mode1, it takes 896/fs to transit from
FFH(0dB) to 80H(MUTE). In case Mode2 and 3,it takes 256/fs to transit from FFH(0dB) to 80H (MUTE). If PDN pin goes to
“L”, ATT7-0 registers are initialized to FFH.ATTN7-0 registers go to FFH when RSTN bit is set to “0”. When RSTN bit
returns to “1”, ATT7-0 registers go to the set value. Digital output volume function is independent of soft mute function.
The setting value of the register is held when switching between PCM mode and DSD mode.
MS0088-E-02
2002/07
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ASAHI KASEI
[AK4357]
n Zero Detection
When the input data atall channels are continuously zero s for 8192 LRCK cycles,The AK4357 has Zero Detection like Table
13. DZF pin immediately goes to “ L” if input data of each channel is not zero after going DZF “ H”. If RSTN bit is “0”, DZF
pin goes to “ H”. DZF pin goes to “ L” at 4~5LRCK if input data of each channel is not zero afterRSTN bit returns to “ 1”. Zero
detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always “ L”. DZFB bit can invert the
polarity of DZF pin. When one of PW1-3 bit is set to “0”, the input data of DAC which the PW bit is set to ”0” should be zero
in order to enable zero detectionof the other channels . When all PW1-3 bits are set to “0”, DZF pin fixes “L”. When DZFM
bit set to “1”, only the input data at all channels are continuously zero s for 8192 LRCK cycles, all DZF pins go to “H”.
DZF Pin
Operations
DZFL1
When Lch Data of DAC1 is “0”, DZFL1 pin goes “H”.
DZFR1
When Rch Data of DAC1 is “0”, DZFR1 pin goes “H”.
DZF23
When all Lch and Rch Data of DAC2,3 are “0”, DZF23 goes “H”.
Table 13. DZF pin Operations
n Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by -∞
during ATT_DATA× ATT transition time (Table 12) from the current ATT level. When the SMUTE bit is returned to“0”, the
mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA × ATT transition time.
If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the
signal transmission.
SMUTE bit
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA × ATT transition time (Table 12). For example, in Normal Speed Mode, this time is 1792LRCK cycles
(1792/fs) at ATT_DATA=128.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 6. Soft Mute and Zero Detection
MS0088-E-02
2002/07
- 15 -
ASAHI KASEI
[AK4357]
n System Reset
The AK4357 should be reset once by bringing PDN= ”L” upon power-up. The analog section exits power-down mode by
MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs.
n Power-down
The AK4357 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure
6 shows an example of the system timing at the power-down and power-up.
Each DAC can be powered down by each power-down bit (PW1-3) “0”. In this case, the internal register values are not
initialized and the analog output is Hi-Z. Because some click noise occurs, the analog output should be muted externally if
the click noise influences system application.
PDN
Internal
State
Normal Operation
Power-down
D/A In
(Digital)
Normal Operation
“0” data
GD
D/A Out
(Analog)
(1)
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK, LRCK, BICK
DZF
External
MUTE
(6)
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influence system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 7. Power-down/up Sequence Example
MS0088-E-02
2002/07
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ASAHI KASEI
[AK4357]
n Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM
voltage and DZFL/DZFR pins go to “H”. Figure 8 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
D/A In
(Digital)
“0” data
(1)
D/A Out
(Analog)
Normal Operation
Digital Block Power-down
GD
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK,LRCK,BICK
2/fs(5)
DZF
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Click noise occurs at the edges(“ ↑ ↓ ”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the internal
RSTN “1”.
Figure 8. Reset Sequence Example
MS0088-E-02
2002/07
- 17 -
ASAHI KASEI
[AK4357]
n D/A conversion mode switching timing
RSTN bit
≥ 4/fs
D/A Mode
PCM Mode
DSD Mode
≥0
D/A Data
PCM Data
DSD Data
Figure 9. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode
PCM Mode
≥4/fs
D/A Data
DSD Data
PCM Data
Figure 10. D/A Mode Switching Mode Timing (DSD to PCM)
Caution: In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not
recommended by SACD format book (Scarlet Book).
MS0088-E-02
2002/07
- 18 -
ASAHI KASEI
[AK4357]
n Mode Control Interface
Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and CDTI. The data on this interface consists of
Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”, Write only), Register Address (M SB first, 5bits) and
Control Data (MSB first, 8bits). The AK4357 latches the data on the rising edge of CCLK, so data should clocked in on the
falling edge. The writing of data becomes valid by CSN “↑”. The clock speed of CCLK is 5MHz (max).
PDN = “L” resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are
not initialized.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
Chip Address (C1=CAD1, C0=CAD0)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 11. Control I/F Timing
*The AK4357 does not support the read command and chip address.
*When the AK4357 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control register
is inhibited.
n Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
Register Name
Control 1
Control 2
Speed & Power Down Control
De-emphasis Control
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
Control 3
D7
ACKS
0
0
0
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
0
D6
SLOW
0
0
0
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
0
D5
DZFM
0
DFS1
D4
DZFE
0
DFS0
D3
DIF2
0
PW3
D2
DIF1
0
PW2
D1
DIF0
PW1
D0
RSTN
RSTN
RSTN
0
0
0
0
DEM1
DEM0
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
DCKS
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
D/P
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
DCKB
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
DZFB
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATS1
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATS0
SMUTE
Note: For addresses from 0BH to 1FH, data must not be written.
When PDN goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the only internal timing is reset, and the registers are not initialized totheir default values.
All data can be written to the registers even if PW1-3 or RSTN bit is “0”.
MS0088-E-02
2002/07
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ASAHI KASEI
[AK4357]
n Register Definitions
Addr Register Name
00H Control 1
Default
D7
ACKS
1
D6
SLOW
0
D5
DZFM
0
D4
DZFE
1
D3
DIF2
0
D2
DIF1
0
D1
DIF0
0
D0
RSTN
1
RSTN: In ternal timing reset
0: Reset. All DZF pins go to “H” and any registers are not initialized.
1: Normal operation
When MCLK frequency or DFS change s , the AK4357 should be reset by PDN pin or RSTN bit.
DIF2-0: Audio data interface modes (See Table 9, PCM Only)
Initial: “000”, Mode 0
Register bits of DIF2-0 are ORed with the DIF2-0 pins.
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins are always “L”.
DZFM: Data Zero Detect Mode
0: Channel Separated Mode (See table 13.)
1: Channel ANDed Mode
If the DZFM bit is set to “1”, all DZF pins go to “H” only when the input data
at all channels are continuously zeros for 8192 LRCK cycles.
SLOW: Slow Roll-off Filter Enable (PCM Only)
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 are
ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr Register Name
01H Control 2
Default
D7
0
0
D6
0
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
SMUTE
0
D0
RSTN
1
RSTN: Internal timing reset
0: Reset. All DZF pins of go to “H” and any registers are not initialized.
1: Normal operation
When MCLK frequency or DFS change s , the AK4357 should be reset by PDN pin or RSTN bit.
SMUTE: Soft Mute Enable
0: Normal operation
1: All DAC outputs soft -muted
MS0088-E-02
2002/07
- 20 -
ASAHI KASEI
Addr Register Name
02H Speed & Power Down Control
Default
[AK4357]
D7
0
0
D6
0
0
D5
DFS1
0
D4
DFS0
0
D3
PW3
1
D2
PW2
1
D1
PW1
1
D0
RSTN
1
RSTN: Internal timing reset
0: Reset. All DZF pins go to “H” and any registers are not initialized.
1: Normal operation
When MCLK frequency or DFS change s , the AK4357 should be reset by PDN pin or RSTN bit.
PW3-1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
PW2: Power down control of DAC2
PW3: Power down control of DAC3
All sections are powered-down by PW1=PW2=PW3=0.
DFS1-0:Sampling speed control (See Table 2, PCM Only)
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs.
Addr Register Name
03H De-emphasis Control
Default
D7
0
0
D6
0
0
D5
D4
D3
D2
D1
D0
0
0
0
0
DEM1
DEM0
0
0
0
0
0
1
DEM1-0: De-emphasis response control for DAC1/2/3 data on SDTI1/2/3/ (See Table 10, PCM only)
Initial: “01”, OFF
MS0088-E-02
2002/07
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ASAHI KASEI
Addr
04H
05H
06H
07H
08H
09H
Register Name
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
Default
[AK4357]
D7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
1
D6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
1
D5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
1
D4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
1
D3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
1
D2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
1
D1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
1
D0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
1
D5
DCKS
0
D4
D/P
0
D3
DCKB
0
D2
DZFB
0
D1
ATS1
0
D0
ATS0
0
ATT7-0: Attenuation Level
128 levels, 0.5dB step (See Table 11)
Addr Register Name
0AH Control 3
Default
D7
0
0
D6
0
0
ATS1-0: DATT Speed Setting (See Table 12)
Initial: “00”, mode 0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge
1: DSD data is output from DCLK rising edge
D/P: DSD/PCM Mode Select
0: PCM Mode. SCLK, SDTI1-3, LRCK
1: DSD Mode. DCLK, DSDL1-3, DSDR1-3
D/P bit is ORed with the DSDM pin.When D/P changes , the AK4357 should be reset by PDN pin, PW bit
or RSTN bit.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs
1: 768fs
MS0088-E-02
2002/07
- 22 -
ASAHI KASEI
[AK4357]
SYSTEM DESIGN
Figure 12 shows the system connection diagram. An evaluation board (AKD4357) is available in order to allow an easy
study on the layout of a surrounding circuit.
+
10u
Digital 5V
0.1u
Reset
DSP
2
1
3
LOUT1-
4
DZFL1
LOUT1+
5
DZFR1
CAD0 6
13 DVSS
DZF23
8
PDN
CAD1 7
BICK 9
MCLK 10
NC 12
Gen
D V D D 11
Clock
ROUT1- 47
15 SDTI2
LOUT2+
46
16 SDTI3
LOUT2-
45
AK4357
ROUT2- 43
19 CCLK
Top View
LOUT3+
42
LOUT3-
41
21 CSN
ROUT3+ 40
22 D S D M
ROUT3- 39
36 AVSS
35 AVDD
34 VREFH
33 DIF2
32 DIF1
31 DIF0
30 DSDR3
29 DSDL3
28 DSDR2
27 DSDL2
Data
LPF
MUTE
R1ch
OUT
LPF
MUTE
L2ch
OUT
LPF
MUTE
R2ch
OUT
LPF
MUTE
L3ch
OUT
LPF
MUTE
R3ch
OUT
AVSS 38
26 DSDR1
DSD
25 DSDL1
23 DCLK
24 NC
L1ch
OUT
ROUT2+ 44
18 SMUTE
20 CDTI
MUTE
48
14 SDTI1
17 L R C K
uP
ROUT1+
LPF
AVSS 37
Controller
Analog 5V
+
0.1u
10u
Mode
Control
System Ground
Analog Ground
Figure 12. Typical Connection Diagram
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive
load.
- All input pins except pull-down pins should not be left floating.
MS0088-E-02
2002/07
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ASAHI KASEI
[AK4357]
8
7
6
5
4
3
2
PDN
CAD1
CAD0
DZF23
DZFR1
DZFL1
LOUT1+
ROUT1+ 4 8
1 4 SDTI1
ROUT1-
47
1 5 SDTI2
LOUT2+
46
1 6 SDTI3
LOUT2-
45
1 7 LRCK
ROUT2+ 4 4
AK4357
AVSS
37
3 6 AVSS
38
24 NC
3 5 AVDD
39
AVSS
3 4 VREFH
ROUT3-
2 3 DCLK
3 3 DIF2
2 2 DSDM
3 2 DIF1
ROUT3+ 4 0
3 1 DIF0
41
2 1 CSN
3 0 DSDR3
LOUT3-
2 8 DSDR2
42
2 0 CDTI
2 7 DSDL2
43
LOUT3+
2 6 DSDR1
ROUT2-
1 9 CCLK
2 5 DSDL1
1 8 SMUTE
2 9 DSDL3
Controller
1
9
BICK
1 3 DVSS
System
LOUT1-
10
MCLK
NC 12
Analog Ground
DVDD 1 1
Digital Ground
Figure 13. Ground Layout
1. Grounding and Power Supply Decoupling
AVDD and DVDD are usually supplied from analog supply in system and should be separated from system digital supply.
Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the
AK4357 must be connected to analog ground plane. System analog ground and digital ground should be connected
together near to where the supplies are brought onto the printed circuit board. Decoupling capacitor, especially 0.1µF
ceramic capacitor for high frequency should be placed as near to AVDD and DVDD as possible.
2. Voltage Reference
VREFH sets the analog output range. VREFH pin is normally connected to AVDD with a 0.1µF ceramic capacitor. All signals,
especially clocks, should be kept away from the VREFH pin in order to avoid unwanted coupling into the AK4357.
3. Analog Outputs
The analog outputs are full-differential outputs and 0.5 x VREFH Vpp (typ) centered around the internal common voltage
(about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and AOUT-.
If the summing gain is 1, the output range is 5.0Vpp (typ @VREFH=5V). The bias voltage of the external summing circuit is
supplied externally. The input data format is 2’s complement. The output voltage(VAOUT) is a positive full scale for 7FFFFF
(@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H (@24bit).
The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator
beyond the audio passband. DC offset on AOUT+/ - is eliminated without AC coupling since the analog outputs are
differential.
MS0088-E-02
2002/07
- 24 -
ASAHI KASEI
[AK4357]
4. External Analog Filter
It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass filter
with a cut -off frequency of maximum 50kHz and a slop of minimum 30dB/Oct. The AK4357 can achieve this filter response
by combination of the internal filter (Table 14) and an external filter (Figure 14).
Frequency
20kHz
50kHz
100kHz
Gain
-0.4dB
-2.8dB
-15.5dB
Table 14. Internal Filter Response at DSD mode
47u
AOUT-
2.0k
1.8k
4.3k
1.0k
2.5Vpp
2200p
47u
2.0k
270p
+Vop
3300p
1.8k
1.0k
+
AOUT+
2.5Vpp
4.3k
270p
Analog
Out
5.65Vpp
-Vop
Figure 14. External 3rd order LPF Circuit Example
Frequency
Gain
20kHz
-0.05dBr
50kHz
-0.51dBr
100kHz
-16.8dBr
DC gain = 1.07dB
Table 15. 3rd order LPF (Figure 14) Response
MS0088-E-02
2002/07
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ASAHI KASEI
[AK4357]
PACKAGE
48pin LQFP(Unit:mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
9.0 ± 0.2
25
12
0.145 ± 0.05
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.5 ± 0.2
n Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0088-E-02
2002/07
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ASAHI KASEI
[AK4357]
MARKING
AKM
AK4357VQ
XXXXXXX
JAPAN
1
1) Asahi Kasei Logo
2) Marking Code: AK4357VQ
3) Date Code: XXXXXXX(7 digits)
4) Country of Origin
5) Pin #1 indication
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an
export license o r other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one d esigned or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant in jury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing i t, and which must therefore meet very
high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that pa rty in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS0088-E-02
2002/07
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