AKM AK4359AEF

[AK4359A]
AK4359A
106dB 192kHz 24-Bit 8ch DAC
GENERAL DESCRIPTION
The AK4359A is an eight channels 24bit DAC corresponding to digital audio system. Using AKM's
advanced multi bit architecture for its modulator the AK4359A delivers a wide dynamic range while
preserving linearity for improved THD+N performance. The AK4359A has single end SCF outputs,
increasing performance for systems with excessive clock jitter. The AK4359A accepts 192kHz PCM data,
ideal for a wide range of applications including DVD-Audio.
FEATURES
† Sampling Rate Ranging from 8kHz to 192kHz
† 24Bit 8 times Digital Filter with Slow roll-off option
† THD+N: -94dB
† DR, S/N: 106dB
† High Tolerance to Clock Jitter
† Single Ended Output Buffer with 2nd order Analog LPF
† Digital De-emphasis for 32, 44.1 & 48kHz sampling
† Zero Detect function
† Channel Independent Digital Attenuator (Linear 256 steps)
† 3-wire Serial and I2C Bus μP I/F for mode setting
† I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I2S, TDM
† Master clock: 256fs, 384fs, 512fs or 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs or 192fs (Quad Speed Mode)
† Power Supply: 4.5 to 5.5V
† 30pin VSOP Package
† AK4384 Semi-compatible
† AK4359 Compatible
DZF
Audio
I/F
LOUT1
LPF
SCF
DAC
DATT
ROUT1
LPF
SCF
DAC
DATT
LOUT2
LPF
SCF
DAC
DATT
ROUT2
LPF
SCF
DAC
DATT
LOUT3
LPF
SCF
DAC
DATT
ROUT3
LPF
SCF
DAC
DATT
LOUT4
LPF
SCF
DAC
DATT
ROUT4
LPF
SCF
DAC
DATT
MS1010-E-01
MCLK
LRCK
BICK
SDTI1
SDTI2
SDTI3
SDTI4
PCM
Control
Register
3-wire
or I2C
AK4359A
2008/10
-1-
[AK4359A]
■ Ordering Guide
AK4359AEF
AK4359AVF
AKD4359A
-20 ∼ +85°C
30pin VSOP
-40 ∼ +105°C
30pin VSOP
Evaluation Board for AK4359A
■ Pin Layout
MCLK
1
30
DZF1
BICK
2
29
DZF2
SD TI1
3
28
AVDD
LRCK
4
27
VSS2
RST B
5
26
VCOM
SMUTE/C SN/CAD0
6
25
LOUT 1
ACKS/CC LK/SCL
7
24
ROUT1
DIF0/CDTI/SDA
8
23
P/S
SD TI2
9
22
LOUT 2
SDTI3
10
21
ROUT2
SDTI4
11
20
LOUT 3
TDM0B
12
19
ROUT3
DEM0
13
18
LOUT 4
DVDD
14
17
ROUT4
VSS1
15
16
DEM1/I2C
AK4359A
Top
View
MS1010-E-01
2008/10
-2-
[AK4359A]
■ Compatibility with AK4384/AK4359
1. Function
Functions
# of channels
I2C
DEM control
16/20bit LSB justified format
control
TDM256 mode
AK4384
2
Not available
Register
AK4359
8
Available
Pin/Register
AK4359A
8
Available
Pin/Register
Register
Pin/Register
Register
Not available
Register
Pin/Register
2. Pin Configuration
AK4359/A
MCLK
BICK
SDTI1
LRCK
RSTB
SMUTE/CSN/CAD0
ACKS/CCLK/SCL
DIF0/CDTI/SDA
SDTI2
SDTI3
SDTI4
DIF1(AK4359)/
TDM0B(AK4359A)
DEM0
DVDD
VSS1
AK4384
MCLK
BICK
SDTI
LRCK
PDN
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
Pin#
30
29
28
27
26
25
24
23
22
21
20
19
13
14
15
18
17
16
AK4384
DZFL
DZFR
VDD
VSS
VCOM
AOUTL
AOUTR
P/S
AK4359/A
DZF1
DZF2
AVDD
VSS2
VCOM
LOUT1
ROUT1
P/S
LOUT2
ROUT2
LOUT3
ROUT3
LOUT4
ROUT4
I2C/DEM1
3. Register map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
Register Name
Control 1
Control 2
Control 3
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
LOUT4 ATT Control
ROUT4 ATT Control
Invert Output Signal
DZF1 Control
DZF2 Control
DEM Control
D7
ACKS
0
PW4
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
INVL1
L1
L1
0
D6
D5
D4
D3
TDM1
TDM0
DIF2
DIF1
0
SLOW
DFS1
DFS0
PW3
PW2
0
0
ATT6
ATT5
ATT4
ATT3
ATT6
ATT5
ATT4
ATT3
ATT6
ATT5
ATT4
ATT3
ATT6
ATT5
ATT4
ATT3
ATT6
ATT5
ATT4
ATT3
ATT6
ATT5
ATT4
ATT3
ATT6
ATT5
ATT4
ATT3
ATT6
ATT5
ATT4
ATT3
INVR1 INVL2 INVR2 INVL3
R1
L2
R2
L3
R1
L2
R2
L3
0
0
0
DEMA
: Compatible with AK4384’s register.
MS1010-E-01
D2
DIF0
DEM1
DZFB
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
INVR3
R3
R3
DEMB
D1
PW1
DEM0
0
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
INVL4
L4
L4
DEMC
D0
RSTN
SMUTE
0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
INVR4
R4
R4
DEMD
2008/10
-3-
[AK4359A]
PIN/FUNCTION
No.
1
Pin Name
MCLK
I/O
I
Function
Master Clock Input
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock
3
SDTI1
I
DAC1 Audio Serial Data Input
4
LRCK
I
L/R Clock
5
RSTB
I
Reset Mode
When at “L”, the AK4359A is in the reset mode.
The AK4359A must be reset once upon power-up.
6
SMUTE
I
Soft Mute in parallel control mode
“H”: Enable, “L”: Disable
CSN
I
Chip Select in serial 3-wire mode
CAD0
I
Chip Address in serial I2C mode
7
ACKS
I
Auto Setting Mode in parallel control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CCLK
I
Control Data Clock in serial 3-wire mode
SCL
Control Data Clock in serial I2C mode
8
DIF0
I
Audio Data Interface Format in parallel control mode
CDTI
I
Control Data Input in serial 3-wire mode
SDA
I/O
Control Data in serial I2C mode
9
SDTI2
I
DAC2 Audio Serial Data Input
10
SDTI3
I
DAC3 Audio Serial Data Input
11
SDTI4
I
DAC4 Audio Serial Data Input
12
TDM0B
I
TDM I/F Format Mode in parallel control mode
“L”: TDM256 mode, “H”: Normal mode
13
DEM0
I
De-emphasis Filter Enable
14
DVDD
Digital Power Supply, +4.5∼+5.5V
15
VSS1
Ground
16
I2C
I
Control Mode Select in serial control mode
“L”: 3-wire Serial, “H”: I2C Bus
DEM1
I
De-emphasis Filter Enable in parallel control mode
17
ROUT4
O
DAC4 Rch Analog Output
18
LOUT4
O
DAC4 Rch Analog Output
19
ROUT3
O
DAC3 Rch Analog Output
20
LOUT3
O
DAC3 Rch Analog Output
21
ROUT2
O
DAC2 Rch Analog Output
22
LOUT2
O
DAC2 Rch Analog Output
23
P/S
I
Parallel/Serial Select
(Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
24
ROUT1
O
DAC1 Rch Analog Output
25
LOUT1
O
DAC1 Lch Analog Output
26
VCOM
O
Common Voltage, AVDD/2
Normally connected to AVSS with a 0.1μF ceramic capacitor in parallel with
a 10μF electrolytic cap.
27
VSS2
Ground
28
AVDD
Analog Power Supply, +4.5∼+5.5V
29
DZF2
O
Data Zero Input Detect
30
DZF1
O
Data Zero Input Detect
Note: All input pins except pull-up pin should not be left floating.
MS1010-E-01
2008/10
-4-
[AK4359A]
■ Handling of Unused Pin
The following tables illustrate recommended states for open pins:
Classification Pin Name
Analog
LOUT4-1, ROUT4-1
DZF2-1
SDTI4-1
Digital
SMUTE (Parallel control mode)
DEM0, TDM0B (Serial control mode)
Setting
Leave open.
Leave open.
Connect to VSS1.
Connect to DVDD or VSS1.
ABSOLUTE MAXIMUM RATINGS
(AVSS=DVSS=0V; Note 1)
Parameter
Symbol
min
Power Supplies
AVDD
-0.3
Analog
DVDD
-0.3
Digital
|AVSS-DVSS|
(Note 2)
ΔGND
Input Current (any pins except for supplies)
IIN
Analog Input Voltage
VINA
-0.3
Digital Input Voltage
VIND
-0.3
Ambient Operating Temperature AK4359AEF
Ta
-20
AK4359AVF
Ta
-40
Storage Temperature
Tstg
-65
Note 1. All voltages with respect to ground.
Note 2. AVSS and DVSS must be connected to the same analog ground plane.
max
6.0
6.0
0.3
±10
AVDD+0.3
DVDD+0.3
85
105
150
Units
V
V
V
mA
V
V
°C
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS=DVSS=0V; Note 1)
Parameter
Symbol
min
typ
Analog
AVDD
4.5
5.0
Power Supplies
Digital
DVDD
4.5
5.0
(Note 3)
Note 3. The power up sequence between AVDD and DVDD is not critical.
max
5.5
5.5
Units
V
V
*AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1010-E-01
2008/10
-5-
[AK4359A]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD=5V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified)
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
(Note 4)
THD+N
Fs=44.1kHz
0dBFS
-94
-84
dB
BW=20kHz
-60dBFS
-42
dB
fs=96kHz
0dBFS
-92
dB
BW=40kHz
-60dBFS
-39
dB
fs=192kHz
0dBFS
-92
dB
BW=40kHz
-60dBFS
-39
dB
Dynamic Range (-60dBFS with A-weighted)
(Note 5)
98
106
dB
S/N
(A-weighted)
(Note 6)
98
106
dB
Interchannel Isolation (1kHz)
90
100
dB
Interchannel Gain Mismatch
0.2
0.5
dB
DC Accuracy
Gain Drift
100
ppm/°C
Output Voltage
(Note 7)
3.15
3.4
3.65
Vpp
Load Resistance
(Note 8)
5
kΩ
Power Supplies
Power Supply Current (AVDD+DVDD)
55
85
mA
Normal Operation (RSTB pin = “H”, fs≤96kHz)
63
90
mA
Normal Operation (RSTB pin = “H”, fs=192kHz)
60
150
Reset Mode (RSTB pin = “L”)
(Note 9)
μA
Note 4. Measured by Audio Precision System Two. Refer to the evaluation board manual.
Note 5. 100dB at 16bit data.
Note 6. S/N does not depend on input word length.
Note 7. Full scale voltage (0dB). Output voltage scales with the voltage of the AVDD pin. AOUT (typ. @0dB) =
3.4Vpp×AVDD/5.0
Note 8. For AC-load.
Note 9. The P/S pin is tied to DVDD and the other all digital input pins including clock pins (MCLK, BICK, LRCK) are
tied to DVSS.
MS1010-E-01
2008/10
-6-
[AK4359A]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD=DVDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)
Parameter
Symbol
min
typ
max
Units
Digital filter
PB
0
20.0
kHz
Passband
±0.05dB (Note 10)
22.05
kHz
-6.0dB
Stopband
(Note 10)
SB
24.1
kHz
Passband Ripple
PR
dB
± 0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 11)
GD
19.3
1/fs
Digital Filter + SCF
Frequency Response 20.0kHz Fs=44.1kHz
FR
+ 0.06/-0.10
dB
40.0kHz Fs=96kHz
FR
+ 0.06/-0.13
dB
80.0kHz Fs=192kHz
FR
+ 0.06/-0.51
dB
Note 10. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs
(@±0.05dB), SB=0.546×fs.
Note 11. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both
channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD=DVDD = 4.5~5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter
Symbol
min
typ
max
Units
PB
0
39.2
18.2
8.1
-
kHz
kHz
kHz
dB
dB
1/fs
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 12)
(Note 12)
SB
PR
SA
GD
(Note 11)
± 0.005
72
-
19.3
-
Digital Filter + SCF
FR
+0.1/-4.3
dB
FR
+0.1/-3.3
dB
FR
+0.1/-3.7
dB
Note 12. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.kHz
fs=96kHz
fs=192kHz
DC CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 4.5 ∼ 5.5V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
2.2
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout = -80µA)
VOH
DVDD-0.4
Low-Level Output Voltage
(Iout = 80µA)
VOL
Input Leakage Current
(Note 13)
Iin
Note 13. The P/S pin has an internal pull-up resistor. (typ. 100kΩ)
MS1010-E-01
typ
-
max
0.8
0.4
± 10
Units
V
V
V
V
μA
2008/10
-7-
[AK4359A]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD=DVDD = 4.5 ∼ 5.5V; CL = 20pF)
Parameter
Symbol
min
fCLK
2.048
Master Clock Frequency
dCLK
40
Duty Cycle
LRCK Frequency
Normal Mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM256 mode (TDM0= “1”, TDM1= “0”)
Normal Speed Mode
High time
Low time
TDM128 mode (TDM0= “1”, TDM1= “1”)
Normal Speed Mode
Double Speed Mode
High time
Low time
Audio Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
(Note 14)
LRCK Edge to BICK “↑”
(Note 14)
SDTI Hold Time
SDTI Setup Time
Control Interface Timing (3-wire Serial control mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN High Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 15)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
MS1010-E-01
typ
11.2896
max
36.864
60
Units
MHz
%
fsn
fsd
fsq
Duty
8
60
120
45
48
96
192
55
kHz
kHz
kHz
%
fsn
tLRH
tLRL
8
3/256fs
3/256fs
48
kHz
ns
ns
fsn
fsd
tLRH
tLRL
8
60
3/128fs
3/128fs
48
96
kHz
kHz
ns
ns
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
81
30
30
20
20
10
10
ns
ns
ns
ns
ns
ns
ns
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
400
0.3
0.3
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
2008/10
-8-
[AK4359A]
Parameter
Symbol
min
Reset Timing
tRST
150
RSTB Pulse Width
(Note 16)
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 16. The AK4359A can be reset by bringing the RSTB pin = “L”.
Note 17. I2C is a registered trademark of Philips Semiconductors.
MS1010-E-01
typ
max
Units
ns
2008/10
-9-
[AK4359A]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Audio Serial Interface Timing
MS1010-E-01
2008/10
- 10 -
[AK4359A]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
CDTI
D3
D2
D1
VIH
D0
VIL
WRITE Data Input Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
I2C Bus mode Timing
tRST
RSTB
VIL
Reset Timing
MS1010-E-01
2008/10
- 11 -
[AK4359A]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4359A, are MCLK, LRCK and BICK. The master clock
(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital
interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting
Mode (ACKS bit = “0”: Register 00H), the sampling speed is set by DFS1-0 bits (Table 1). The frequency of MCLK for
each sampling speed is set automatically. (Table 2~Table 4) In auto setting mode (ACKS bit = “1”: Default), as MCLK
frequency is detected automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6),
it is not necessary to set DFS1-0 bits.
In parallel control mode, the sampling speed can be set by only the ACKS pin. When ACKS pin = “L”, the AK4359A
operates by Normal Speed Mode. When ACKS pin = “H”, auto setting mode is enabled. The parallel control mode does
not support 128fs and 192fs of double speed mode.
The AK4359A is automatically placed in reset state when the external clocks (MCLK, BICK, LRCK) are stopped during
a normal operation (RSTB pin =“H”). When the external clocks are input again, the AK4359A exit reset state and starts
the operation.
DFS1
DFS0
0
0
Normal Speed Mode
8kHz~48kHz
0
1
Double Speed Mode
60kHz~96kHz
1
Sampling Rate (fs)
(default)
0
Quad Speed Mode
120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
MCLK
BICK
fs
256fs
384fs
512fs
768fs
1152fs
64fs
32.0kHz
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz
N/A
2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz
N/A
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) (N/A: Not available)
MS1010-E-01
2008/10
- 12 -
[AK4359A]
LRCK
MCLK
BICK
fs
128fs
192fs
256fs
384fs
64fs
88.2kHz 106896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
MCLK
BICK
fs
128fs
192fs
64fs
176.4kHz 22.5792MHz 33.8688MHz 106896MHz
192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK
Sampling Speed
512fs
768fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
Table 5. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLK (MHz)
192fs
256fs
384fs
512fs
768fs
16.3840
24.5760
22.5792
33.8688
24.5760
36.8640
22.5792
33.8688
24.5760
36.8640
33.8688
36.8640
Table 6. System Clock Example (Auto Setting Mode)
MS1010-E-01
1152fs
36.8640
-
Sampling
Speed
Normal
Double
Quad
2008/10
- 13 -
[AK4359A]
■ Audio Serial Interface Format
In parallel control mode, the DIF0 and TDM0 pins as shown in Table 7 can select four serial data modes. The register
value of DIF1-0 and TDM1-0 bits are ignored. In serial control mode, the DIF2-0 and TDM1-0 bits shown in Table 8 can
select 11 serial data modes. Initial value of DIF2-0 bits is “010”. The setting of the DIF1 pin is ignored. In all modes the
serial data is MSB-first, 2’s complement format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20
MSB justified formats by zeroing the unused LSBs.
In parallel control mode, when the TDM0 pin = “L”, the audio interface format is TDM256 mode (Table 7). The audio
data of all DACs (eight channels) is input to the SDTI1 pin. The input data to SDTI2-4 pins is ignored. BICK should be
fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is MSB-first, 2’s complement
format. The input data to the SDTI1 pin is latched on the rising edge of BICK.
In serial control mode, when the TDM0 bit = “1” and the TDM1 bit = “0”, the audio interface format is TDM256 mode
(Table 8), and the audio data of all DACs (eight channels) is input to the SDTI1 pin. The input data to the SDTI2-4 pins is
ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is
MSB-first, 2’s complement format. The input data to the SDTI1 pin is latched on the rising edge of BICK. In TDM128
mode (TDM0 bit = “1” and TDM1 bit = “1”, Table 8), the audio data of DACs (four channels; L1, R1, L2, R2) is input to
the SDTI1 pin. The other four data (L3, R3, L4, R4) are input to the SDTI2 pin. The input data to SDTI3-4 pins is ignored.
BICK should be fixed to 128fs. The audio data is MSB-first, 2’s complement format. The input data to SDTI1-2 pins is
latched on the rising edge of BICK.
Mode
Normal
TDM256
Mode
Normal
0
1
2
3
4
TDM256
5
6
7
TDM128
8
9
10
2
3
5
6
TDM0B DIF0 SDTI Format
LRCK
H
L
24-bit MSB Justified
H/L
2
L/H
H
H
24-bit I S Compatible
L
L
24-bit MSB Justified
↑
L
H
24-bit I2S Compatible
↓
Table 7. Audio Data Formats (Parallel control mode)
BICK
≥48fs
≥48fs
256fs
256fs
Figure
Figure 3
Figure 4
Figure 5
Figure 6
TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format
LRCK
0
0
0
0
0
16-bit LSB Justified
H/L
0
0
0
0
1
20-bit LSB Justified
H/L
0
0
0
1
0
24-bit MSB Justified
H/L
0
0
0
1
1
24-bit I2S Compatible
L/H
0
0
1
0
0
24-bit LSB Justified
H/L
0
1
0
0
0
N/A
0
1
0
0
1
N/A
0
1
0
1
0
24-bit MSB Justified
↑
2
0
1
0
1
1
24-bit I S Compatible
↓
0
1
1
0
0
24-bit LSB Justified
↑
1
1
0
0
0
N/A
1
1
0
0
1
N/A
1
1
0
1
0
24-bit MSB Justified
↑
1
1
0
1
1
24-bit I2S Compatible
↓
1
1
1
0
0
24-bit LSB Justified
↑
Table 8. Audio Data Formats (Serial control mode) (N/A: Not available)
MS1010-E-01
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
256fs
256fs
256fs
Figure 5
Figure 6
Figure 7
128fs
128fs
128fs
Figure 8
Figure 9
Figure 10
2008/10
- 14 -
[AK4359A]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
1
0
5
14
4
15
3
2
16
1
17
0
31
15
0
14
6
5
14
1
4
15
3
16
2
1
17
0
31
15
14
0
1
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
Don’t care
0
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
20
21
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1/4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
MS1010-E-01
2008/10
- 15 -
[AK4359A]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
Don’t care
23 22
0
1
23
Don’t care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
3/256fs (min)
3/256fs (min)
256 BICK
LRCK
BICK(256fs)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 5. Mode 5 Timing
3/256fs (min)
256 BICK
3/256fs (min)
LRCK
BICK(256fs)
SDTI1(i)
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 6. Mode 6 Timing
3/256fs (min)
256 BICK
3/256fs (min)
LRCK
BICK(256fs)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
23
Figure 7. Mode 7 Timing
MS1010-E-01
2008/10
- 16 -
[AK4359A]
3/128fs (min)
128 BICK
3/128fs (min)
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
23 22
0
0
23 22
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
23 22
0
0
23 22
23 22
0
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
23 22
0
23 22
0
23
0
23
Figure 8. Mode 8 Timing
3/128fs (min)
128 BICK
3/128fs (min)
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
0
23 22
0
0
23 22
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
0
23 22
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
Figure 9. Mode 9 Timing
3/128fs (min)
128 BICK
3/128fs (min)
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
23 22
0
23 22
L3
R3
L4
R4
32 BICK
32 BICK
32 BICK
32 BICK
0
19
0
19
Figure 10. Mode 10 Timing
MS1010-E-01
2008/10
- 17 -
[AK4359A]
■ De-emphasis Filter
A digital de-emphasis filter is available for 32kHz, 44.1kHz or 48kHz sampling rates (tc = 50/15μs). For double speed
and quad speed modes, the digital de-emphasis filter is always off. In serial control mode, the DEM1-0 bits are enabled
for each DAC by the DEMA-D bits setting. In parallel control mode, DEM1-0 pins are valid.
DEM1
DEM0
Mode
0
0
44.1kHz
(default)
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 9. De-emphasis Filter Control (Normal Speed Mode)
■ Output Volume Control
The AK4359A includes channel independent digital output volume control (ATT) with 256 levels at linear step including
MUTE. The volume control is in front of the DAC, and it can attenuate the input data from 0dB to –48dB and mute. When
changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The
transition time of 1 level and all 256 levels is shown in Table 10. The attenuation level is calculated by ATT = 20 log10
(ATT_DATA / 255) [dB] and MUTE at ATT_DATA = “0”.
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
8LRCK
2040LRCK
16LRCK
4080LRCK
Table 10. ATT Transition time
■ Zero Detection
When the input data at all channels are continuously zeros for 8192 LRCK cycle, the zero detection is executed (Table
11). The DZF pin is immediately set to “L” if input data of each channel is not zero after going DZF “H”. If RSTN bit is
“0”, the DZF pin is set to “H”. The DZF pin goes “L” after 4~5LRCK after RSTN bit returns to “1”. Zero detect function
can be disabled by setting the DZFE bit. In this case, all DZF pins are always “L”. When one of PW1-4 bit is set to “0”, the
input data of DAC, that the PW bit is set to “0”, should be zero in order to enable zero detection of the other channels.
When all PW1-4 bits are set to “0”, the DZF pin fixes “L”. DZFB bit can invert the polarity of the DZF pin. In parallel
control mode, the zero detect function is disabled and the DZF pin is fixed to “L”.
DZF Pin
DZF1
DZF2
Operations
ANDed output of zero detection flag of each channel set to “1” in 0CH register
ANDed output of zero detection flag of each channel set to “1” in 0DH register
Table 11. DZF pins Operation
MS1010-E-01
2008/10
- 18 -
[AK4359A]
■ Soft Mute Operation
The Soft mute operation is performed in the digital domain. When the SMUTE bit is set to “1”, the output signal is
attenuated by -∞ during ATT_DATA×ATT transition time (Table 10) from the current ATT level. When the SMUTE bit
is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during
ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the
attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
SMUTE
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA×ATT transition time (Table 10). For this example, in Normal Speed Mode, the time is 1020LRCK
cycles (1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data for each channel is continuously zero for 8192 LRCK cycles, the DZF pin for each channel
changes to “H”. The DZF pin immediately goes “L” if input data are not zero after going DZF “H”. In parallel control
mode, the DZF pin is fixed to “L” regardless of the state of the SMUTE pin.
Figure 11. Soft Mute and Zero Detection (DZFB bit = “0”)
MS1010-E-01
2008/10
- 19 -
[AK4359A]
■ System Reset
The AK4359A should be reset once by bringing the RSTB pin = “L” upon power-up. The AK4359A is powered up and
the internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4359A is in
the power-down mode until MCLK and LRCK are input.
■ Power ON/OFF timing
All DACs are placed in the power-down mode by bringing the RSTB pin “L” and the registers are initialized. the analog
outputs go to VCOM. As some click noise occurs at the edge of RSTB signal, the analog output should be muted
externally if the click noise influences system application.
Each DAC can be powered down by setting each power-down bit (PW4-1) to “0”. In this case, the registers are not
initialized and the corresponding analog outputs go to VCOM. As some click noise occurs at the edge of RSTB signal, the
analog output should be muted externally if click noise aversely affect system perfoemance.
Power
RSTB pin
(1)
Internal
State
Normal Operation
DAC In
(Digital)
“0”data
“0”data
GD
DAC Out
(Analog)
(3)
(2)
GD
(4)
(4)
(3)
(6)
DZFL/DZFR
External
Mute
Reset
(5)
Mute ON
Mute ON
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) Analog outputs are VCOM in power-down mode.
(4) Click noise occurs at the edge of RSTN signal. This noise is output even if “0” data is input.
(5) Mute the analog output externally if click noise (3) adversely affect system performance
The timing example is shown in this figure.
(6) DZFL/R pins are “L” in the reset state (RSTB pin = “L”). (DZFB bit = “0”)
Figure 12. Power-down/up Sequence Example
MS1010-E-01
2008/10
- 20 -
[AK4359A]
■ Reset Function (RSTN bit)
When the RSTN bit = “0”, internal circuit of DAC is powered down but the registers are not initialized. The analog
outputs settle to VCOM voltage and the DZF pins go “H” at DZFB bit = “0”.
Figure 13 shows the example of reset by RSTN bit. When RSTN bit = “0”, pop noise is reduced at no clock state.
RSTN bit
3~4/fs (5)
2~3/fs (5)
Internal
RSTN bit
Internal
State
Normal Operation
P
D/A In
(Digital)
d
“0 ” data
(1)
D/A Out
(Analog)
Normal O peration
D igital Block
GD
GD
(3)
(2)
(3)
(1)
2/ fs(4)
DZF
(6)
Notes:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs settle to VCOM voltage.
(3) Small pop noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”
data is input.
(4) The DZF pins change to “H” when the RSTN bit becomes “0”, and return to “L” at 2/fs after RSTN bit becomes
“1”.
(5) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
(6) Mute the analog output externally if click noise (3) and Hi-Z (2) adversely affect system performance
Figure 13. Reset Sequence Example (DZFB bit = “0”)
MS1010-E-01
2008/10
- 21 -
[AK4359A]
■ Reset Function (MCLK, BICK and LRCK stop)
When the MCLK, LRCK or BICK stops, the digital circuit of the AK4359A is placed in power-down mode. When the
MCLK, LRCK and BICK are restarted, power-down mode is released and the AK4359A returns to normal operation
mode.
AVDD pin
DVDD pin
RSTB pin
(1)
Internal
State
Power-down
D/A In
(Digital)
Power-down
Normal O peration
Normal Operation
(3)
GD
D/A Out
(Analog)
Digital Circuit P ower-down
(2)
GD
(4)
Hi-Z
(5)
(2)
(4)
(4)
(5)
Clock In
MCLK, BICK, LRCK Stop
MCLK, BICK, LRCK
External
MUTE
(6)
(6)
(6)
Notes:
(1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns.
(2) The analog output corresponding to digital input has group delay (GD).
(3) The digital data can be stopped. Click noise after MCLK, BICK and LRCK are input again can be reduced by
inputting “0” data during this period.
(4) Click noise occurs within 20usec or 20usec +3 ~ 4LRCK from the riding edge (“↑”) of the RSTN pin or MCLK
inputs. Click noise also occurs within 20usec when MCLK, LRCK or BICK is stopped.
(5) Mute the analog output externally if click noise (4) influences system applications. The timing example is shown
in this figure.
Figure 14. Clock Stop Sequence
MS1010-E-01
2008/10
- 22 -
[AK4359A]
■ Register Control Interface
The functions of the AK4359A can be controlled by registers. Two types of control mode write internal registers. In the
I2C-bus mode, the chip address is determined by the state of the CAD0 pin. In 3-wire mode, the chip address is fixed to
“11”. The RSTB pin = “L” initializes the registers to their default values. Writing “0” to the RSTN bit resets the internal
timing circuit, but the registers are not initialized.
* The AK4359A does not support read command.
* When the AK4359A is in power down mode (RSTB pin = “L”) or the MCLK is not provided, writing to control
register is prohibited.
* When the state of the P/S pin is changed, the AK4359A should be reset by the RSTB pin = “L”.
* In serial control mode, the setting of parallel pins is invalid.
Function
Parallel Control Mode
Serial Control Mode
Double sampling mode at 128/192fs
De-emphasis
O
SMUTE
O
Zero Detection
16/20/24bit LSB justified format
TDM256 mode
O
TDM128 mode
Table 12. Function Table (O: Supported, -: Not supported)
O
O
O
O
O
O
O
(1) 3-wire Serial Control Mode (I2C pin = “L”)
The 3-wire μP interface pins, CSN, CCLK and CDTI, write internal registers. The data on this interface consists of Chip
Address (2bits, C1/0; fixed to “11”), Read/Write (1bit; fixed to “1”, Write only), Register Address (MSB first, 5bits) and
Control Data (MSB first, 8bits). The AK4359A latches the data on the rising edge of CCLK, so data should clocked in on
the falling edge. The writing of data becomes valid by the rising edge of CSN. The clock speed of CCLK is 5MHz (max).
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
Chip Address (Fixed to “11”)
R/W:
READ/WRITE (Fixed to “1”, Write only)
A4-A0:
Register Address
D7-D0:
Control Data
Figure 15. Control I/F Timing
MS1010-E-01
2008/10
- 23 -
[AK4359A]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4359A supports the fast-mode I2C-bus system (max: 400kHz).
Figure 16 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 20). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit which is a data direction
bit (R/W) (Figure 17). The most significant six bits of the slave address are fixed as “001001”. The next one bit are CAD0
(device address bit). The bit identify the specific device on the bus. The hard-wired input pin (CAD0 pin) set them. If the
slave address match that of the AK4359A and R/W bit is “0”, the AK4359A generates the acknowledge and the write
operation is executed. If R/W bit is “1”, the AK4359A generates the not acknowledge since the AK4359A can be only a
slave-receiver. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during
the acknowledge clock pulse (Figure 21).
The second byte consists of the address for control registers of the AK4359A. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 18). Those data after the second byte contain control data. The format is MSB
first, 8bits (Figure 19). The AK4359A generates an acknowledge after each byte is received. A data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 20).
The AK4359A is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4359A generates an acknowledge, and awaits the next data. The master can transmit more than one byte instead of
terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits address
counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed 1FH
prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 22) except for the START and the STOP
condition.
S
T
A
R
T
SDA
S
S
T
O
P
R/W
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 16. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
1
CAD0
R/W
A2
A1
A0
D2
D1
D0
(This CAD0 should match with CAD0 pin)
Figure 17. The first byte
0
0
0
A4
A3
Figure 18. The second byte
D7
D6
D5
D4
D3
Figure 19. Byte structure after the second byte
MS1010-E-01
2008/10
- 24 -
[AK4359A]
SDA
SCL
S
P
start condition
stop condition
Figure 20. START and STOP conditions
DATA
OUTPUT BY
MASTER
not acknowledge
DATA
OUTPUT BY
SLAVE(AK4359)
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 21. Acknowledge on the I2C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 22. Bit transfer on the I2C-bus
MS1010-E-01
2008/10
- 25 -
[AK4359A]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
Register Name
Control 1
Control 2
Control 3
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
LOUT4 ATT Control
ROUT4 ATT Control
Invert Output Signal
DZF1 Control
DZF2 Control
DEM Control
D7
ACKS
0
PW4
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
INVL1
L1
L1
0
D6
TDM1
0
PW3
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
INVR1
R1
R1
0
D5
TDM0
SLOW
PW2
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
INVL2
L2
L2
0
D4
DIF2
DFS1
0
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
INVR2
R2
R2
0
D3
DIF1
DFS0
0
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
INVL3
L3
L3
DEMA
D2
DIF0
DEM1
DZFB
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
INVR3
R3
R3
DEMB
D1
PW1
DEM0
PW1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
INVL4
L4
L4
DEMC
D0
RSTN
SMUTE
0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
INVR4
R4
R4
DEMD
Note: For addresses from 0FH to 1FH, data must not be written.
When the RSTB pin goes “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default
values. All data can be written to the registers even if PW4-1 bits or RSTN bit is “0”.
■ Register Definitions
Addr
00H
Register Name
Control 1
Default
D7
ACKS
D6
TDM1
D5
TDM0
D4
DIF2
D3
DIF1
D2
DIF0
D1
PW1
D0
RSTN
1
0
0
0
1
0
1
1
RSTN: Internal timing reset
0: Reset. All DZF pins change to “H” and any registers are not initialized.
1: Normal operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
This bit is duplicated into D1 of 02H.
DIF2-0: Audio data interface modes (Table 8)
Initial: “010”,
MS1010-E-01
2008/10
- 26 -
[AK4359A]
TDM0-1: TDM Mode Select
Mode
Normal
TDM256
TDM128
TDM1
0
0
1
TDM0
0
1
1
BICK
32fs∼
256fs fixed
128fs fixed
SDTI
1-4
1
1-2
Sampling Speed
Normal, Double, Quad Speed
Normal Speed
Normal, Double Speed
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
bits is ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode.
Addr
01H
Register Name
Control 2
Default
D7
0
0
D6
0
0
D5
SLOW
D4
DFS1
D3
DFS0
D2
DEM1
D1
DEM0
D0
SMUTE
0
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (Table 9)
Initial: “01”, OFF
DFS1-0: Sampling speed control (Table 1)
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs.
SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
Adr
02H
Register Name
Speed & Power Down Control
Default
D7
PW4
1
D6
PW3
1
D5
PW2
1
D4
0
0
D3
0
0
D2
DZFB
0
D1
PW1
1
D0
0
0
PW1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
This bit is duplicated into D1 of 00H.
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
PW4-2: Power-down control (0: Power-down, 1: Power-up)
PW2: Power down control of DAC2
PW3: Power down control of DAC3
PW4: Power down control of DAC4
All sections are powered-down by PW1=PW2=PW3=PW4= “0”.
MS1010-E-01
2008/10
- 27 -
[AK4359A]
Addr
03H
04H
05H
06H
07H
08H
09H
0AH
Register Name
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
LOUT4 ATT Control
ROUT4 ATT Control
Default
D7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
1
D6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
1
D5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
1
D4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
1
D3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
1
D2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
1
D1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
1
D0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
1
D6
INVR1
0
D5
INVL2
0
D4
INVR2
0
D3
INVL3
0
D2
INVR3
0
D1
INVL4
0
D0
INVR4
0
D5
L2
L2
0
D4
R2
R2
0
D3
L3
L3
0
D2
R3
R3
0
D1
L4
L4
0
D0
R4
R4
0
D4
0
0
D3
DEMA
0
D2
DEMB
0
D1
DEMC
0
D0
DEMD
0
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
Addr
0BH
Register Name
Invert Output Signal
Default
D7
INVL1
0
INVL4-1, INVR4-1: Inverting Output Polarity
0: Normal Output
1: Inverted Output
Addr
0CH
0DH
Register Name
DZF1 Control
DZF2 Control
Default
D7
L1
L1
0
D6
R1
R1
0
L1-4, R1-4: Zero Detect Flag Enable Bit for the DZF1/2 pins
0: Disable
1: Enable
Addr
0EH
Register Name
DEM Control
Default
D7
0
0
D6
0
0
D5
0
0
DEMA-D: De-emphasis Enable bit of DAC1/2/3/4
0: Disable
1: Enable
MS1010-E-01
2008/10
- 28 -
[AK4359A]
SYSTEM DESIGN
Figure 23 and Figure 24 show the system connection diagram. The evaluation board (AKD4359A) demonstrates
application circuits, the optimum layout, power supply arrangements and measurement results.
Master Clock
1
MCLK
DZF1
30
Mute Signal
64fs
2
BICK
DZF2
29
24bit Audio Data
3
SDTI1
AVDD
28
fs
4
LRCK
AVSS
27
Reset
5
RSTB
VCOM
26
+
0.1u 10u
6
SMUTE
LOUT1
25
10u
7
ACKS
ROUT1
24
8
DIF0
P/S
23
LOUT2
22
MUTE
L2ch Out
ROUT2
21
MUTE
R2ch Out
Microcontroller
24bit Audio Data
9
SDTI2
24bit Audio Data
10
SDTI3
24bit Audio Data
AK4359A
0.1u 10u
Analog 5V
+
MUTE
L1ch Out
MUTE
R1ch Out
11
SDTI4
LOUT3
20
MUTE
L3ch Out
Micro-
12
TDM0
ROUT3
19
MUTE
R3ch Out
controller
13
DEM0
LOUT4
18
MUTE
L4ch Out
14
DVDD
ROUT4
17
MUTE
R4ch Out
15
DVSS
DEM1
16
Micro-controller
10u
+
0.1u
Digital 5V
Digital Ground
Analog Ground
Figure 23. Typical Connection Diagram (Parallel Control Mode)
MS1010-E-01
2008/10
- 29 -
[AK4359A]
Master Clock
1
MCLK
DZF1
30
64fs
2
BICK
DZF2
29
24bit Audio Data
3
SDTI1
AVDD
28
fs
4
LRCK
AVSS
27
Reset
5
RSTB
VCOM
26
6
CSN
LOUT1
25
7
CCLK
ROUT1
24
Microcontroller
AK4359A
0.1u 10u
Analog 5V
+
10u
+
0.1u 10u
10u
MUTE
L1ch Out
MUTE
R1ch Out
8
CDTI
P/S
23
24bit Audio Data
9
SDTI2
LOUT2
22
MUTE
L2ch Out
24bit Audio Data
10
SDTI3
ROUT2
21
MUTE
R2ch Out
24bit Audio Data
11
SDTI4
LOUT3
20
MUTE
L3ch Out
Micro-
12
TDM0
ROUT3
19
MUTE
R3ch Out
controller
13
DEM0
LOUT4
18
MUTE
L4ch Out
14
DVDD
ROUT4
17
MUTE
R4ch Out
15
DVSS
I2C
16
10u
+
0.1u
Digital 5V
Digital Ground
Analog Ground
Figure 24. Typical Connection Diagram (3-wire Serial Control Mode)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-up pin should not be left floating.
MS1010-E-01
2008/10
- 30 -
[AK4359A]
Analog Ground
Digital Ground
System
Controller
1
MCLK
DZF1
30
2
BICK
DZF2
29
3
SDTI1
AVDD
28
4
LRCK
AVSS
27
5
RSTB
VCOM
26
6
SMUTE/CSN/CAD0
LOUT1
25
7
ACKS/CCLK/CSL
ROUT1
24
8
DFS0/CDT/SDA
P/S
23
9
SDTI2
LOUT2
22
10
SDTI3
ROUT2
21
11
SDTI4
LOUT3
20
12
TDM0
ROUT3
19
13
DEM0
LOUT4
18
14
DVDD
ROUT4
17
15
DVSS
DEM1/I2
16
AK4359A
Figure 25. Ground Layout
AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
AVDD and DVDD are usually supplied from analog supply in system and should be separated from system digital
supply. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and
DVSS of the AK4359A must be connected to analog ground plane. System analog ground and digital ground should
be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitor,
especially 0.1μF ceramic capacitor for high frequency should be placed as near to AVDD and DVDD as possible.
2. Analog Outputs
The analog outputs are single-ended and centered around the VCOM voltage. The output signal range is typically
3.40Vpp ([email protected]=5V). The phase of the analog outputs can be inverted channel independently by INVL/INVR bits.
The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. The input data format is two’s complement. The output voltage is positive full
scale for 7FFFFFH (@24bit) and negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for
000000H (@24bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV.
MS1010-E-01
2008/10
- 31 -
[AK4359A]
PACKAGE
30pin VSOP (Unit: mm)
1.5MAX
*9.7±0.1
0.3
30
16
7.6±0.2
5.6±0.1
A
15
1
0.22±0.1
0.15 +0.10
-0.05
0.65
0.12 M
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
■ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS1010-E-01
2008/10
- 32 -
[AK4359A]
MARKING (AK4359AEF)
AKM
AK4359AEF
XXXXXXXXX
XXXXXXXXX
Date code identifier
MARKING (AK4359AVF)
AKM
AK4359AVF
XXXXXXXXX
XXXXXXXXX
Date code identifier
MS1010-E-01
2008/10
- 33 -
[AK4359A]
REVISION HISTORY
Date (YY/MM/DD)
08/09/19
08/10/02
Revision
00
01
Reason
First Edition
Spec Addition
Page
Contents
AK4359AVF was added.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
MS1010-E-01
2008/10
- 34 -