TI DRV8839

DRV8839
www.ti.com
SLVSBN4 – JANUARY 2013
LOW VOLTAGE DUAL ½-H-BRIDGE DRIVER IC
Check for Samples: DRV8839
FEATURES
1
•
2
•
•
•
•
•
•
Dual ½-H-Bridge Motor Driver
– Drives a DC Motor or One Winding of a
Stepper Motor, or Other Loads
– Low MOSFET On-Resistance:
HS + LS 280 mΩ
1.8-A Maximum Drive Current
1.8-V to 11-V Motor Operating Supply Voltage
Range
Separate Motor and Logic Supply Pins
Individual ½-H-Bridge Control Input Interface
Low-Power Sleep Mode With 120-nA Maximum
Combined Supply Current
2-mm x 3-mm 12-Pin WSON Package
APPLICATIONS
•
Battery-Powered:
– DSLR Lenses
– Consumer Products
– Toys
– Robotics
– Cameras
– Medical Devices
DESCRIPTION
The DRV8839 provides a versatile power driver solution for cameras, consumer products, toys, and other
low-voltage or battery-powered applications. The device has two independent ½-H-bridge drivers and can drive
one DC motor or one winding of a stepper motor, as well as other devices like solenoids. The output stages use
N-channel power MOSFET’s configured as ½-H-bridges. An internal charge pump generates needed gate drive
voltages.
The DRV8839 can supply up to 1.8-A of output current. It operates on a motor power supply voltage from 1.8 V
to 11 V and a device power supply voltage of 1.8 V to 7 V.
The DRV8839 has independent input and enable pins for each ½-H-bridge which allow independent control of
each output.
Internal shutdown functions are provided for over current protection, short circuit protection, under voltage
lockout and overtemperature.
The DRV8839 is packaged in a 12-pin, 2-mm x 3-mm WSON package with PowerPAD™ (Eco-friendly: RoHS &
no Sb/Br).
ORDERING INFORMATION (1)
PACKAGE (2)
PowerPAD™ (WSON) - DSS
(1)
(2)
Reel of 3000
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
DRV8839DSSR
8839
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
DRV8839
SLVSBN4 – JANUARY 2013
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
1.8 to 11V
VM
VM
VM
Drives DC motor or
1/2 Stepper
1.8 to 7V
VCC
Gate
Drive
Charge
Pump
OCP
OUT1
Step
Motor
VCC
DCM
VM
Logic
IN1
OUT2
Gate
Drive
OCP
EN1
IN2
OverTemp
EN2
Osc
nSLEEP
GND
2
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Table 1. TERMINAL FUNCTIONS
NAME
PIN
I/O (1)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
POWER AND GROUND
GND
5, 6
-
Device ground
VM
1, 2
-
Motor supply
Bypass to GND with a 0.1-μF, 16-V ceramic
capacitor.
VCC
12
-
Device supply
Bypass to GND with a 0.1-μF, 6.3-V ceramic
capacitor.
nSLEEP
11
I
Sleep mode input
Logic low puts device in low-power sleep mode
Logic high for normal operation
Internal pulldown resistor
IN1
10
I
Input 1
Logic input controls OUT1
Internal pulldown resistor
EN1
9
I
Enable 1
Logic high enables OUT1
Internal pulldown resistor
IN2
8
I
Input 2
Logic input controls OUT2
Internal pulldown resistor
EN2
7
I
Enable 2
Logic high enables OUT2
Internal pulldown resistor
OUT1
3
O
Output 1
OUT2
4
O
Output 2
2, 5
-
No connection
CONTROL
OUTPUT
Connect to motor winding
NO CONNECT
NC
(1)
No connection to these pins
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
DSS PACKAGE
(TOP VIEW)
VM
VM
OUT1
OUT2
GND
GND
1
12
2
11
3
4
GND
(PPAD )
10
9
5
8
6
7
VCC
nSLEEP
IN1
EN1
IN2
EN2
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ABSOLUTE MAXIMUM RATINGS (1) (2)
VALUE
UNIT
VM
Power supply voltage range
-0.3 to 12
V
VCC
Power supply voltage range
-0.3 to 7
V
Digital input pin voltage range
-0.5 to 7
V
Internally limited
A
TJ
Peak motor drive output current
Operating junction temperature range
-40 to 150
°C
Tstg
Storage temperature range
-60 to 150
°C
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
DRV8839
THERMAL METRIC
(1)
DSS
UNITS
12 PINS
Junction-to-ambient thermal resistance (2)
θJA
50.4
(3)
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
19.9
ψJT
Junction-to-top characterization parameter (5)
0.9
ψJB
Junction-to-board characterization parameter (6)
20
(7)
6.9
θJCbot
Junction-to-case (bottom) thermal resistance
58
°C/W
xxx
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
RECOMMENDED OPERATING CONDITIONS
TA = 25°C (unless otherwise noted)
MIN
VCC
Device power supply voltage range
1.8
VM
Motor power supply voltage range
IOUT
H-bridge output current (1)
fPWM
VIN
(1)
4
NOM
MAX
UNIT
7
V
1.8
11
V
0
1.8
A
Externally applied PWM frequency
0
250
kHz
Logic level input voltage
0
5.5
V
Power dissipation and thermal limits must be observed.
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SLVSBN4 – JANUARY 2013
ELECTRICAL CHARACTERISTICS
TA = 25°C, VM = 5 V, VCC = 3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
No PWM
40
100
µA
50 kHz PWM
0.8
1.5
mA
nSLEEP = 0 V
30
95
nA
No PWM
300
500
µA
50 kHz PWM
0.7
1.5
mA
5
25
nA
POWER SUPPLY
IVM
VM operating supply current
IVMQ
VM sleep mode supply current
IVCC
VCC operating supply current
ICCQ
VCC sleep mode supply current
nSLEEP = 0 V
VUVLO
VCC undervoltage lockout
voltage
VCC rising
1.8
VCC falling
1.7
V
LOGIC-LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
0.31 x VCC 0.34 x VCC
0.39 x VCC 0.43 x VCC
VHYS
Input hysteresis
0.08 x VCC
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Pulldown resistance
-5
V
V
V
5
50
100
μA
μA
kΩ
H-BRIDGE FETS
RDS(ON)
HS + LS FET on resistance
IOFF
Off-state leakage current
I O = 800 mA, TJ = 25°C
280
330
mΩ
±200
nA
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tTSD
Thermal shutdown temperature
1.9
Die temperature
150
160
3.5
A
180
°C
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TIMING REQUIREMENTS (1)
TA = 25°C, VM = 5 V, VCC = 3 V, RL = 20 Ω
NO.
(1)
PARAMETER
CONDITIONS
MIN
MAX
UNIT
1
t1
Output enable time
120
ns
2
t2
Output disable time
120
ns
3
t3
Delay time, INx high to OUTx high
120
ns
4
t4
Delay time, INx low to OUTx low
120
ns
5
t5
Output rise time
50
150
ns
6
t6
Output fall time
50
150
ns
Not production tested – ensured by design
INx
ENx
3
1
2
4
OUTx
OUTx
z
z
80%
80%
20%
20%
5
6
6
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SLVSBN4 – JANUARY 2013
FUNCTIONAL DESCRIPTION
Bridge Control
The DRV8839 is controlled using separate enable and input pins for each ½-H-bridge.
The following table shows the logic for the DRV8839:
ENx
INx
OUTx
0
X
Z
1
0
L
1
1
H
Sleep Mode
If the nSLEEP pin is brought to a logic-low state, the DRV8839 will enter a low-power sleep mode. In this state
all unnecessary internal circuitry is powered down.
Power Supplies and Input Pins
The input pins may be driven within their recommended operating conditions with or without the VCC and VM
power supplies present. No leakage current path will exist to the supply. There is a weak pulldown resistor
(approximately 100 kΩ) to ground on each input pin.
VCC and VM may be applied and removed in any order. When VCC is removed, the device will enter a low
power state and draw very little current from VM. If the supply voltage is between 1.8 V and 7 V, VCC and VM
may be connected together.
Protection Circuits
The DRV8839 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled. After
approximately 1 ms, the bridge will be re-enabled automatically.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled. Once the die temperature
has fallen to a safe level operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VCC pin falls below the undervoltage lockout threshold voltage, all circuitry in
the device is disabled and internal logic is reset. Operation resumes when VCC rises above the UVLO threshold.
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APPLICATIONS INFORMATION
Motor Connections
If a single DC motor is connected to the DRV8839, it is connected between the OUT1 and OUT2 pins as shown
below:
OUT1
DCM
OUT2
Figure 1. Single DC Motor Connection
Motor operation is controlled as follows:
EN1
(1)
(2)
8
EN2
IN1
IN2
OUT1
OUT2
See
(1)
MOTOR OPERATION
0
X
X
X
Z
X
0
X
X
See
1
1
0
0
L
L
Brake
1
1
0
1
L
H
Reverse
1
1
1
0
H
L
Forward
1
1
1
1
H
H
Brake
(2)
Z
Off (coast)
Off (coast)
State depends on EN2 and IN2, but does not affect motor operation because OUT1 is tri-stated.
State depends on EN1 and IN1, but does not affect motor operation because OUT2 is tri-stated.
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Two DC motors may be connected to the DRV8839. In this mode, it is not possible to reverse the direction of the
motors; they will turn only in one direction. The connections are shown below:
OUT1
DCM
OUT2
DCM
Figure 2. Dual DC Motor Connection
Motor operation is controlled as follows:
ENx
INx
OUTx
MOTOR OPERATION
0
X
Z
Off (coast)
1
0
L
Brake
1
1
H
Forward
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THERMAL INFORMATION
Thermal Protection
The DRV8839 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation,
insufficient heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8839 is dominated by the power dissipated in the output FET resistance, or RDS(ON).
Average power dissipation when running a stepper motor can be roughly estimated by:
PTOT = RDS(ON) x (IOUT(RMS))2
(1)
Where PTOT is the total power dissipation, RDS(ON) is the resistance of the HS plus LS FETs, and IOUT(RMS) is the
RMS output current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale
output current setting.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases.
10
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Feb-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
DRV8839DSSR
ACTIVE
Package Type Package Pins Package Qty
Drawing
WSON
DSS
12
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-2-260C-1 YEAR
(4)
-40 to 85
8839A0
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8839DSSR
Package Package Pins
Type Drawing
WSON
DSS
12
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
2.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
0.85
4.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Mar-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8839DSSR
WSON
DSS
12
3000
367.0
367.0
35.0
Pack Materials-Page 2
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