TI DRV8812PWP

DRV8812
www.ti.com
SLVS997F – OCTOBER 2009 – REVISED AUGUST 2013
DUAL-BRIDGE MOTOR CONTROLLER IC
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FEATURES
APPLICATIONS
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1
2
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Dual-H-Bridge Current-Control Motor Driver
– Capable of Driving a Bipolar Stepper or
Two DC Motors
– Two-Bit Winding Current Control Allows Up
to Four Current Levels
– Low MOSFET On-Resistance
1.6-A Maximum Drive Current at 24 V, 25°C
Built-In 3.3-V Reference Output
Industry-Standard Parallel Digital Control
Interface
8-V to 45-V Operating Supply Voltage Range
Thermally Enhanced HTSSOP and QFN
Surface Mount Packages
Automatic Teller Machines
Money Handling Machines
Video Security Cameras
Printers
Scanners
Office Automation Machines
Gaming Machines
Factory Automation
Robotics
DESCRIPTION
The DRV8812 provides an integrated motor driver solution for printers, scanners, and other automated
equipment applications. The device has two H-bridge drivers, and can drive a bipolar stepper motor or two DC
motors. The output driver block for each consists of N-channel power MOSFET’s configured as full H-bridges to
drive the motor windings. The DRV8812 is capable of driving up to 1.6-A of output current (with proper
heatsinking, at 24 V and 25°C).
A simple parallel digital control interface is compatible with industry-standard devices. Decay mode is
programmable.
Internal shutdown functions are provided for over current protection, short circuit protection, under voltage
lockout and overtemperature.
The DRV8812 is available in a 28-pin HTSSOP package with PowerPAD™ and in a 28-pin QFN package
PowerPAD™ (Eco-friendly: RoHS & no Sb/Br).
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
(2)
ORDERABLE PART
NUMBER
PACKAGE (2)
PowerPAD™ (HTSSOP) - PWP
Reel of 2000
DRV8812PWPR
PowerPAD™ (QFN) - RHD
Reel of 3000
DRV8812RHDR
TOP-SIDE
MARKING
DRV8812
For the most current packaging and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
DRV8812
SLVS997F – OCTOBER 2009 – REVISED AUGUST 2013
www.ti.com
DEVICE INFORMATION
Functional Block Diagram
VM
VM
CP1
Int. VCC
Internal
0.01mF
LS Gate
Reference &
Drive
Regs
V3P3OUT
CP2
VM
Charge
Pump
3.3V
VCP
3.3V
0.1mF
Thermal
HS Gate
Drive
Shut down
1MW
VM
VMA
AVREF
BVREF
AOUT1
+
APHASE
Step
Motor
DCM
Driver A
AENBL
Motor
-
AOUT2
AI0
+
ISENA
AI1
-
BPHASE
BENBL
BI0
Control
VM
Logic
VMB
BI1
DECAY
BOUT1
Motor
nRESET
Driver B
nSLEEP
BOUT2
nFAULT
ISENB
GND
2
DCM
GND
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Table 1. TERMINAL FUNCTIONS
NAME
PIN
PWP
RHD
I/O (1)
EXTERNAL COMPONENTS
OR CONNECTIONS
DESCRIPTION
POWER AND GROUND
GND
14, 28
3, 17
-
Device ground
VMA
4
7
-
Bridge A power supply
VMB
11
14
-
Bridge B power supply
V3P3OUT
15
18
O
3.3-V regulator output
CP1
1
4
IO
Charge pump flying capacitor
CP2
2
5
IO
Charge pump flying capacitor
VCP
3
6
IO
High-side gate drive voltage
Connect a 0.1-μF 16-V ceramic capacitor and
a 1-MΩ resistor to VM.
AENBL
21
24
I
Bridge A enable
Logic high to enable bridge A
APHASE
20
23
I
Bridge A phase (direction)
Logic high sets AOUT1 high, AOUT2 low
AI0
24
27
I
AI1
25
28
I
Bridge A current set
Sets bridge A current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
BENBL
22
25
I
Bridge B enable
Logic high to enable bridge B
BPHASE
23
26
I
Bridge B phase (direction)
Logic high sets BOUT1 high, BOUT2 low
BI0
26
1
I
BI1
27
2
I
Bridge B current set
Sets bridge B current: 00 = 100%,
01 = 71%, 10 = 38%, 11 = 0
DECAY
19
22
I
Decay mode
Low = slow decay, open = mixed decay,
high = fast decay
nRESET
16
19
I
Reset input
Active-low reset input initializes internal logic
and disables the H-bridge outputs
nSLEEP
17
20
I
Sleep mode input
Logic high to enable device, logic low to enter
low-power sleep mode
AVREF
12
15
I
Bridge A current set reference input
BVREF
13
16
I
Bridge B current set reference input
18
21
OD
Fault
Logic low when in fault condition (overtemp,
overcurrent)
ISENA
6
9
IO
Bridge A ground / Isense
Connect to current sense resistor for bridge A
ISENB
9
12
IO
Bridge B ground / Isense
Connect to current sense resistor for bridge B
AOUT1
5
8
O
Bridge A output 1
AOUT2
7
10
O
Bridge A output 2
BOUT1
10
13
O
Bridge B output 1
BOUT2
8
11
O
Bridge B output 2
Connect to motor supply (8 - 45 V). Both pins
must be connected to same supply.
Bypass to GND with a 0.47-μF 6.3-V ceramic
capacitor. Can be used to supply VREF.
Connect a 0.01-μF 50-V capacitor between
CP1 and CP2.
CONTROL
Reference voltage for winding current set.
Can be driven individually with an external
DAC for microstepping, or tied to a reference
(e.g., V3P3OUT). A 0.01-µF bypass capacitor
to GND is recommended.
STATUS
nFAULT
OUTPUT
(1)
Connect to motor winding A
Connect to motor winding B
Directions: I = input, O = output, OZ = tri-state output, OD = open-drain output, IO = input/output
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PWP PACKAGE
(TOP VIEW)
RHD PACKAGE
(TOP VIEW)
22
23
24
25
26
27
28
1
21
2
20
3
19
GND
(PPAD)
4
18
5
17
6
16
7
15
nFAULT
nSLEEP
nRESET
V3P3OUT
GND
BVREF
AVREF
14
13
12
11
10
9
8
VMB
BOUT1
ISENB
BOUT2
AOUT2
ISENA
AOUT1
4
DECAY
APHASE
AENBL
BENBL
BPHASE
AI0
AI1
BI0
BI1
GND
CP1
CP2
VCP
VMA
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SLVS997F – OCTOBER 2009 – REVISED AUGUST 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VMx
VREF
(1) (2)
VALUE
UNIT
Power supply voltage range
–0.3 to 47
V
Digital pin voltage range
–0.5 to 7
V
Input voltage
–0.3 to 4
V
–0.3 to 0.8
V
Peak motor drive output current, t < 1 μS
Internally limited
A
Continuous motor drive output current (3)
1.6
A
ISENSEx pin voltage
Continuous total power dissipation
See Dissipation Ratings table
TJ
Operating virtual junction temperature range
–40 to 150
°C
TA
Operating ambient temperature range
–40 to 85
°C
Tstg
Storage temperature range
–60 to 150
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
THERMAL INFORMATION
DRV8812
THERMAL METRIC
(1)
Junction-to-ambient thermal resistance (2)
θJA
(3)
PWP
RHD
28 PINS
28 PINS
38.9
35.8
θJCtop
Junction-to-case (top) thermal resistance
23.3
25.1
θJB
Junction-to-board thermal resistance (4)
21.2
8.2
ψJT
Junction-to-top characterization parameter (5)
0.8
0.3
ψJB
Junction-to-board characterization parameter (6)
20.9
8.2
θJCbot
Junction-to-case (bottom) thermal resistance (7)
2.6
1.1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
xxx
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Motor power supply voltage range (1)
VM
(2)
VREF
VREF input voltage
IV3P3
V3P3OUT load current
(1)
(2)
NOM
MAX
8.2
45
1
3.5
1
UNIT
V
V
mA
All VM pins must be connected to the same supply voltage.
Operational at VREF between 0 V and 1 V, but accuracy is degraded.
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ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V, fPWM < 50 kHz
5
8
mA
IVMQ
VM sleep mode supply current
VM = 24 V
10
20
μA
VUVLO
VM undervoltage lockout voltage
VM rising
7.8
8.2
V
V3P3OUT REGULATOR
V3P3
V3P3OUT voltage
IOUT = 0 to 1 mA, VM = 24 V, TJ = 25°C
3.18
3.30
3.42
IOUT = 0 to 1 mA
3.10
3.30
3.50
V
LOGIC-LEVEL INPUTS
VIL
Input low voltage
VIH
Input high voltage
0.6
0.7
V
5.25
V
VHYS
Input hysteresis
IIL
Input low current
VIN = 0
20
μA
IIH
Input high current
VIN = 3.3 V
100
μA
0.5
V
1
μA
0.8
V
±40
µA
2
0.45
–20
V
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
DECAY INPUT
VIL
Input low threshold voltage
For slow decay mode
0
VIH
Input high threshold voltage
For fast decay mode
2
IIN
Input current
V
H-BRIDGE FETS
RDS(ON)
HS FET on resistance
RDS(ON)
LS FET on resistance
IOFF
Off-state leakage current
VM = 24 V, I O = 1 A, TJ = 25°C
0.63
VM = 24 V, IO = 1 A, TJ = 85°C
0.76
VM = 24 V, IO = 1 A, TJ = 25°C
0.65
VM = 24 V, IO = 1 A, TJ = 85°C
0.78
–20
0.90
0.90
20
Ω
Ω
μA
MOTOR DRIVER
fPWM
Internal PWM frequency
tBLANK
Current sense blanking time
50
tR
Rise time
VM = 24 V
100
tF
Fall time
VM = 24 V
80
tDEAD
Dead time
tDEG
Input deglitch time
kHz
μs
3.75
360
ns
250
ns
2.9
µs
400
1.3
ns
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
tTSD
Thermal shutdown temperature
1.8
Die temperature
150
5
A
160
180
°C
3
μA
CURRENT CONTROL
IREF
xVREF input current
VTRIP
xISENSE trip voltage
AISENSE
Current sense amplifier gain
6
xVREF = 3.3 V
–3
xVREF = 3.3 V, 100% current setting
635
660
685
xVREF = 3.3 V, 71% current setting
445
469
492
xVREF = 3.3 V, 38% current setting
225
251
276
Reference only
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5
mV
V/V
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SLVS997F – OCTOBER 2009 – REVISED AUGUST 2013
FUNCTIONAL DESCRIPTION
PWM Motor Drivers
The DRV8812 contains two H-bridge motor drivers with current-control PWM circuitry. A block diagram of the
motor control circuitry is shown in Figure 1. A bipolar stepper motor is shown, but the drivers can also drive two
separate DC motors.
Figure 1. Motor Control Circuitry
Note that there are multiple VM motor power supply pins. All VM pins must be connected together to the motor
supply voltage.
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Bridge Control
The xPHASE input pins control the direction of current flow through each H-bridge. The xENBL input pins enable
the H-bridge outputs when active high. Table 2 shows the logic.
Table 2. H-Bridge Logic
xENBL
xPHASE
xOUT1
xOUT2
0
X
Z
Z
1
1
H
L
1
0
L
H
Current Regulation
The current through the motor windings is regulated by a fixed-frequency PWM current regulation, or current
chopping. When an H-bridge is enabled, current rises through the winding at a rate dependent on the DC voltage
and inductance of the winding. Once the current hits the current chopping threshold, the bridge disables the
current until the beginning of the next PWM cycle.
For stepping motors, current regulation is normally used at all times, and can changing the current can be used
to microstep the motor. For DC motors, current regulation is used to limit the start-up and stall current of the
motor.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the xISEN pins, multiplied by a factor of 5, with a reference voltage. The reference voltage is input
from the xVREF pins, and is scaled by a 2-bit DAC that allows current settings of 100%, 71%, 38% of full-scale,
plus zero.
The full-scale (100%) chopping current is calculated in Equation 1.
VREFX
ICHOP = 5¾
· RISENSE
(1)
Example:
If a 0.5-Ω sense resistor is used and the VREFx pin is 3.3 V, the full-scale (100%) chopping current will be
3.3 V / (5 x 0.5 Ω) = 1.32 A.
Two input pins per H-bridge (xI1 and xI0) are used to scale the current in each bridge as a percentage of the fullscale current set by the VREF input pin and sense resistance. The function of the pins is shown in Table 3.
Table 3. H-Bridge Pin Functions
xI1
xI0
RELATIVE CURRENT
(% FULL-SCALE CHOPPING CURRENT)
1
1
0% (Bridge disabled)
1
0
38%
0
1
71%
0
0
100%
Note that when both xI bits are 1, the H-bridge is disabled and no current flows.
Example:
If a 0.5-Ω sense resistor is used and the VREF pin is 3.3 V, the chopping current will be 1.32 A at the 100%
setting (xI1, xI0 = 00). At the 71% setting (xI1, xI0 = 01) the current will be 1.32 A x 0.71 = 0.937 A, and at
the 38% setting (xI1, xI0 = 10) the current will be 1.32 A x 0.38 = 0.502 A. If (xI1, xI0 = 11) the bridge will be
disabled and no current will flow.
8
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Decay Mode
During PWM current chopping, the H-bridge is enabled to drive current through the motor winding until the PWM
current chopping threshold is reached. This is shown in Figure 2 as case 1. The current flow direction shown
indicates the state when the xENBL pin is high.
Once the chopping current threshold is reached, the H-bridge can operate in two different states, fast decay or
slow decay.
In fast decay mode, once the PWM chopping current level has been reached, the H-bridge reverses state to
allow winding current to flow in a reverse direction. As the winding current approaches zero, the bridge is
disabled to prevent any reverse current flow. Fast decay mode is shown in Figure 2 as case 2.
In slow decay mode, winding current is re-circulated by enabling both of the low-side FETs in the bridge. This is
shown in Figure 2 as case 3.
Figure 2. Decay Mode
The DRV8812 supports fast decay, slow decay and a mixed decay mode. Slow, fast, or mixed decay mode is
selected by the state of the DECAY pin - logic low selects slow decay, open selects mixed decay operation, and
logic high sets fast decay mode. Note that the DECAY pin sets the decay mode for both H-bridges.
Mixed decay mode begins as fast decay, but at a fixed period of time (75% of the PWM cycle) switches to slow
decay mode for the remainder of the fixed PWM period.
Blanking Time
After the current is enabled in an H-bridge, the voltage on the xISEN pin is ignored for a fixed period of time
before enabling the current sense circuitry. This blanking time is fixed at 3.75 μs. Note that the blanking time also
sets the minimum on time of the PWM.
nRESET and nSLEEP Operation
The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs
are ignored while nRESET is active.
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Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped, the V3P3OUT regulator is disabled, and all internal clocks are stopped. In
this state all inputs are ignored until nSLEEP returns inactive high. When returning from sleep mode, some time
(approximately 1 ms) needs to pass before the motor driver becomes fully operational.
Protection Circuits
The DRV8812 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP time, all FETs in the H-bridge will be disabled and the
nFAULT pin will be driven low. The device will remain disabled until either nRESET pin is applied, or VM is
removed and re-applied.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown. Note that overcurrent protection does not use the current sense
circuitry used for PWM current control, and is independent of the ISENSE resistor value or VREF voltage.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
10
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THERMAL INFORMATION
Thermal Protection
The DRV8812 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
Power Dissipation
Power dissipation in the DRV8812 is dominated by the power dissipated in the output FET resistance, or RDS(ON).
Average power dissipation when running a stepper motor can be roughly estimated by Equation 2.
PTOT = 4 · RDS(ON) · (IOUT(RMS))
2
(2)
where PTOT is the total power dissipation, RDS(ON) is the resistance of each FET, and IOUT(RMS) is the RMS output
current being applied to each winding. IOUT(RMS) is equal to the approximately 0.7x the full-scale output current
setting. The factor of 4 comes from the fact that there are two motor windings, and at any instant two FETs are
conducting winding current for each winding (one high-side and one low-side).
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report SLMA002, " PowerPAD™ Thermally
Enhanced Package" and TI application brief SLMA004, " PowerPAD™ Made Easy", available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
DRV8812PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
DRV8812
DRV8812PWPR
ACTIVE
HTSSOP
PWP
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
DRV8812
DRV8812RHDR
ACTIVE
VQFN
RHD
28
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DRV8812
DRV8812RHDT
ACTIVE
VQFN
RHD
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DRV8812
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Sep-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DRV8812PWPR
HTSSOP
PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
DRV8812RHDR
VQFN
RHD
28
3000
330.0
DRV8812RHDT
VQFN
RHD
28
250
180.0
12.4
5.3
5.3
1.5
8.0
12.0
Q2
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
31-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8812PWPR
HTSSOP
PWP
28
2000
367.0
367.0
38.0
DRV8812RHDR
VQFN
RHD
28
3000
367.0
367.0
35.0
DRV8812RHDT
VQFN
RHD
28
250
210.0
185.0
35.0
Pack Materials-Page 2
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