ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS8523I is a low skew, high performance 1-to-4 Differential-to-HSTL fanout buffer HiPerClockS™ and a member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The ICS8523I has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. • 4 differential HSTL compatible outputs ICS • Selectable diffferential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency: 650MHz • Translates any single-ended input signal to HSTL levels with resistor bias on nCLK input Guaranteed output and part-to-part skew characteristics make the ICS8523I ideal for those applications demanding well defined performance and repeatability. • Output skew: 50ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 1.6ns (maximum) • 3.3V core, 1.8V output operating supply • Lead-Free package available • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT D CLK_EN GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VDD Q LE CLK nCLK PCLK nPCLK CLK_SEL 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 ICS8523I Q3 nQ3 8523BGI 1 2 3 4 5 6 7 8 9 10 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm body package G Package Top View www.icst.com/products/hiperclocks.html 1 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 GND Power 2 CLK_EN Input 3 CLK_SEL Input 4 CLK Input 5 nCLK Input 6 PCLK Input 7 nPCLK Input 8, 9 nc Unused Description Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, nQ outputs are forced Pullup high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK Pulldown inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Pulldown Non-inver ting differential LVPECL clock input. Pullup Inver ting differential LVPECL clock input. No connect. 10 VDD Power Core supply pin. 11, 12 nQ3, Q3 Output Differential output pair. HSTL interface levels. 13, 18 VDDO Power Output supply pins. 14, 15 nQ2, Q2 Output Differential output pair. HSTL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. HSTL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. HSTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ 8523BGI www.icst.com/products/hiperclocks.html 2 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 3A. CONTROL INPUT FUNCTION TABLE Inputs CLK_EN CLK_SEL Outputs Selected Source Q0:Q3 nQ0:nQ3 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ0:nQ3 Q0:Q3 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK or PCLK nCLK or nPCLK 0 1 0 1 Input to Output Mode Polarity HIGH Differential to Differential Non Inver ting LOW Differential to Differential Non Inver ting LOW HIGH Single Ended to Differential Non Inver ting HIGH LOW Single Ended to Differential Non Inver ting HIGH LOW Single Ended to Differential Inver ting LOW HIGH Single Ended to Differential Inver ting Q0:Q3 nQ0:nQ3 0 LOW 1 HIGH Biased; NOTE 1 Biased; NOTE 1 Biased; NOTE 1 0 Biased; NOTE 1 1 NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 8523BGI www.icst.com/products/hiperclocks.html 3 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter VDD Core Power Supply Voltage Test Conditions VDDO Output Power Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 1.6 1.8 2.0 V 55 mA Maximum Units TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical VIH Input High Voltage CLK_EN, CLK_SEL 2 VDD + 0.3 V VIL Input Low Voltage CLK_EN, CLK_SEL -0.3 0.8 V IIH Input High Current 5 µA IIL Input Low Current CLK_EN VDD = VIN = 3.465V CLK_SEL VDD = VIN = 3.465V CLK_EN VDD = 3.465V, VIN = 0V -150 150 µA µA CLK_SEL VDD = 3.465V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter IIH Input High Current IIL Input Low Current Maximum Units nCLK VDD = VIN = 3.465V Test Conditions 5 µA CLK VDD = VIN = 3.465V 150 µA nCLK VDD = 3.465V, VIN = 0V -150 µA CLK VDD = 3.465V, VIN = 0V -5 µA VPP Minimum Typical Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8523BGI www.icst.com/products/hiperclocks.html 4 1.3 V VDD - 0.85 V REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Maximum Units PCLK VDD = VIN = 3.465V Test Conditions 150 µA nPCLK VDD = VIN = 3.465V 5 µA IIH Input High Current IIL Input Low Current V PP Peak-to-Peak Input Voltage Minimum Typical PCLK VDD = 3.465V, VIN = 0V -5 µA nPCLK VDD = 3.465V, VIN = 0V -150 µA 0.3 Common Mode Input Voltage; NOTE 1, 2 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. 1 V VDD V TABLE 4D. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX Test Conditions Output Crossover Voltage Minimum Maximum Units 0.9 1.4 V 0 0.4 V 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V 0.6 1.3 V Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50Ω to ground. VSWING Typical TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum ƒ≤ 650MHz 1.0 Typical Maximum Units 650 MHz 1.6 ns 50 ps fMAX Output Frequency tPD Propagation Delay; NOTE 1 t sk(o) Output Skew; NOTE 2, 4 t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 250 ps tR Output Rise Time 20% to 80% @ 50MHz 300 700 ps tF Output Fall Time 20% to 80% @ 50MHz 300 700 ps 55 % odc Output Duty Cycle 45 All parameters measured at 500MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8523BGI www.icst.com/products/hiperclocks.html 5 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V±5% 1.8V±0.2V V DD V DD Qx SCOPE VDDO nCLK, nPCLK V HSTL Cross Points PP V CMR CLK, PCLK nQx GND GND = 0V 3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx Qx PART 1 nQx Qx Qy PART 2 nQy nQy Qy t sk(pp) t sk(o) OUTPUT SKEW PART-TO-PART SKEW nCLK, nPCLK CLK, PCLK 80% 80% VSW I N G Clock Outputs nQ0:nQ3 20% 20% tF tR Q0:Q3 tPD OUTPUT RISE/FALL TIME PROPAGATION DELAY nQ0:nQ3 Q0:Q3 Pulse Width t odc = odc & tPERIOD 8523BGI PERIOD t PW t PERIOD www.icst.com/products/hiperclocks.html 6 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8523BGI www.icst.com/products/hiperclocks.html 7 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an HSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS HSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8523BGI BY www.icst.com/products/hiperclocks.html 8 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK PCLK R1 100 Zo = 50 Ohm nPCLK nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK HiPerClockS Input R5 100 - 200 R2 84 FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 3.3V 2.5V 3.3V 3.3V 3.3V 2.5V R3 120 SSTL Zo = 50 Ohm R4 120 C1 LVDS Zo = 60 Ohm R4 1K R3 1K PCLK PCLK R5 100 Zo = 60 Ohm nPCLK R1 120 C2 nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK R1 1K R2 120 FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER 8523BGI HiPerClockS PCLK/nPCLK R2 125 HiPerClockS PCL K/n PC LK R2 1K FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 9 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER SCHEMATIC EXAMPLE Figure 5 shows a schematic example of the ICS8523I. In this example, the input is driven by an ICS HiPerClockS HSTL driver. The decoupling capacitors should be physically located near the power pin. For ICS8523I, the unused clock outputs can be left floating. Zo = 50 + Zo = 50 3.3V R2 50 R1 50 R12 1K U3 1.8V Zo = 50 Zo = 50 Ohm Zo = 50 Ohm R11 1K LVHSTL Driver R9 50 3.3V 1 2 3 4 5 6 7 8 9 10 R10 50 GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK NC NC VDD Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 20 19 18 17 16 15 14 13 12 11 + 1.8V Zo = 50 1.8V R4 50 R3 50 C1 0.1u 8523 Zo = 50 + 1.8V Zo = 50 C2 0.1u - C3 0.1u R6 50 R5 50 Zo = 50 + Zo = 50 R8 50 R7 50 FIGURE 5. ICS8523I HSTL BUFFER SCHEMATIC EXAMPLE 8523BGI www.icst.com/products/hiperclocks.html 10 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8523I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8523I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 190.6mW Power (outputs)MAX = 32.6mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32.6mW = 130.4mW Total Power_MAX (3.465V, with all outputs switching) = 190.6mW + 130.4mW = 321mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.321W * 66.6°C/W = 106.4°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θJA FOR 20-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8523BGI www.icst.com/products/hiperclocks.html 11 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 6. VDDO Q1 VOUT RL 50Ω FIGURE 6. HSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V OH_MIN Pd_L = (V /R ) * (V L -V DDO_MAX /R ) * (V OL_MAX L DDO_MAX ) OH_MIN -V ) OL_MAX Pd_H = (0.9V/50Ω) * (2V -0.9V) = 19.8mW Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW 8523BGI www.icst.com/products/hiperclocks.html 12 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8523I is: 472 8523BGI www.icst.com/products/hiperclocks.html 13 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER 20 LEADP TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 20 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 α 0° 8° aaa -- 0.10 0.75 Reference Document: JEDEC Publication 95, MS-153 8523BGI www.icst.com/products/hiperclocks.html 14 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8523BGI ICS8523BGI 20 lead TSSOP 72 per tube -40°C to 85°C ICS8523BGIT ICS8523BGI 20 lead TSSOP on Tape and Reel 2500 -40°C to 85°C ICS8523BGILF ICS8523BGILF 72 per tube -40°C to 85°C ICS8523BGILFT ICS8523BGILF 20 lead "Lead-Free" TSSOP 20 lead "Lead-Free" TSSOP on Tape and Reel 2500 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8523BGI www.icst.com/products/hiperclocks.html 15 REV. C SEPTEMBER 16, 2004 ICS8523I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-HSTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page B T5 5 AC Characteristics table. tPD row, changed Min. from 1.2ns to 1.0ns. 1/11/02 1 Revised Features section, Bullet 1,6 - took out 1.8V 5/6/02 B B T2 C T4D C T9 8523BGI 8 - 10 2 4 5 11 - 12 1 9 15 Description of Change Date In the Application Information section, added Schematic Examples Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - changed Output rating. HSTL DC Characteristics Table - changed VOH 1V min. to 0.9V min. Power Considerations - changed Total Power Dissipation to reflect VOH change. Calculations changed due to new Total Power Dissipation. Changed LVHSTL to HSTL throughout data sheet. Added Lead-Free bullet to Features section. Updated LVPECL Clock Input Interface section. Added Lead-Free Par t Number to Ordering Information TAble. www.icst.com/products/hiperclocks.html 16 10/28/02 6/23/03 9/16/04 REV. C SEPTEMBER 16, 2004