ICS ICS95V842

ICS95V842
Integrated
Circuit
Systems, Inc.
DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)
Recommended Application:
1:2 DDRI Clock Driver
Pin Configuration
Switching Characteristics:
• CYCLE - CYCLE jitter: <75ps
• OUTPUT - OUTPUT skew: <60ps
• Period jitter: ±75ps
• Half-Period jitter: ±75ps
VDD2.5
DDRT0
DDRC0
GND
CLK_INT
CLK_INC
AVDD
AGND
1
2
3
4
5
6
7
8
ICS95V842
Product Description/Features:
• Low skew, low jitter PLL clock driver
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• With bypass mode mux
• Operating frequency 60 to 220 MHz
16 pin SSOP
Functionality
INPUTS
OUTPUTS
AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
PLL State
GND
L
H
L
H
L
H
Bypassed/Off
GND
H
L
H
L
H
L
Bypassed/Off
2.5V
(nom)
L
H
L
H
L
H
On
2.5V
(nom)
H
L
H
L
H
L
On
Block Diagram
FB_INT
FB_INC
CLK_INC
CLK_INT
AVDD
0830A—09/10/04
PLL
FB_OUTT
FB_OUTC
DDRT (1:0)
DDRC (1:0)
16
15
14
13
12
11
10
9
GND
DDRC1
DDRT1
VDD2.5
FB_INC
FB_INT
FB_OUTT
FB_OUTC
ICS95V842
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
1
2
3
4
5
6
7
8
VDD2.5
DDRT0
DDRC0
GND
CLK_INT
CLK_INC
AVDD
AGND
PWR
OUT
OUT
PWR
IN
IN
PWR
PWR
9
FB_OUTC
OUT
10
FB_OUTT
OUT
11
FB_INT
IN
12
FB_INC
IN
13
14
15
16
VDD2.5
DDRT1
DDRC1
GND
PWR
OUT
OUT
PWR
DESCRIPTION
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"True" reference clock input.
"Complementary" reference clock input.
3.3V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
Complement single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other DDR outputs,
This output must be connect to FB_INC.
True single-ended feedback output, dedicated external feedback. It
switches at the same frequency as other DDR outputs, This output
must be connect to FB_INT.
True single-ended feedback input, provides feedback signal to internal
PLL for synchronization with CLK_INT to eliminate phase error.
Complement single-ended feedback input, provides feedback signal to
internal PLL for synchronization with CLK_INT to eliminate phase
error.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
0830A—09/10/04
2
ICS95V842
Absolute Maximum Ratings
Supply Voltage: (VDD & AVDD) . . . . . . . . . . . . . . . . -0.5V to 3.6V
Input clamp current: IIK (VI < 0 or VI > VDD) . . . . . . +/- 50mA
Output clamp current: IOK (VO < 0 or VO > VDD) . . +/- 50mA
Continuous output current: I O (VO = 0 to VDD) . . . . +/- 50mA
Package thermal impedance, theta JA: DGG package +89°C/Ω
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
SYMBOL
MIN
TYP
PARAMETER
CONDITIONS
VI = VDD or GND
IIH
5
Input High Current
VI = VDD or GND
IIL
Input Low Current
Operating Supply
Current
IDD2.5
-18
µA
mA
IOL
VDD = 2.3V, VOUT = 1.2V
26
mA
IOZ
VDD=2.7V, Vout=VDD or GND
±10
µA
VIK
Iin = -18mA
VDD = min to max,
IOH = -1 mA
VDD = 2.3V,
IOH = -12 mA
VDD = min to max
IOL=1 mA
VDD = 2.3V
IOH=12 mA
VI = VDD or GND
VI = VDD or GND
-1.2
V
IDDPD
IOH
Output Low Current
High-level output voltage
Low-level output voltage
5
160
UNITS
µA
µA
mA
CL = 0pF, RL = ∞Ω
VDD = 2.3V, VOUT = 1V
Output High Current
High Impedance
Output Current
Input Clamp Voltage
CL = 0pF, RL = ∞Ω
MAX
VOH
VOL
100
VDD - 0.1
V
1.7
V
0.1
0.6
CIN
Input Capacitance1
1
COUT
Output Capacitance
1
Guaranteed by design and characterization, not 100% tested in production.
0830A—09/10/04
3
3
3
V
pF
pF
ICS95V842
DC Electrical Characteristics
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Supply Voltage
VDDQ, AVDD
2.3
2.5
CLK_INT, CLK_INC, FB_INC,
Low level input voltage
VIL
0.4
FB_INT
CLK_INT, CLK_INC, FB_INC,
VDD/2 + 0.18
2.1
High level input voltage
VIH
FB_INT
DC input signal voltage
VIN
-0.3
(note 1,2)
Differential input signal
CLK_INT, CLK_INC, FB_INC,
VID
0.36
voltage (note 3)
FB_INT
Differential output voltage
CLK_INT, CLK_INC, FB_INC,
VOD
0.7
(note 3)
FB_INT
Output differential crossVOX
VDD/2 - 0.15
voltage (note 4)
Input differential crossVDD/2 - 0.2 VDD/2
VIX
voltage (note 4)
Operating free-air
TA
0
temperature
MAX
2.7
UNITS
V
V DD/2 - 0.18
V
V
V DD + 0.3
V
VDD + 0.6
V
VDD + 0.6
V
VDD/2 + 0.15
V
VDD/2 + 0.2
V
85
°C
Notes:
1 Unused inputs must be held high or low to prevent them from floating.
2 DC input signal voltage specifies the allowable DC excursion of differential input.
3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching,
where VTR is the true input level and VCP is the complementary input level.
4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which
the differential signal must be crossing.
Timing Requirements
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
MIN
MAX UNITS
Max clock frequency 3
Application Frequency
Range3
Input clock duty cycle
CLK stabilization
freqop
33
233
MHz
freqApp
60
220
MHz
dtin
TSTAB
40
60
100
%
µs
0830A—09/10/04
4
ICS95V842
Switching Characteristics
TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
CONDITION
SYMBOL
MIN
TYP
3
freq
40
Max clock frequency
op
Application Frequency
freqApp
60
Range3
dtin
Input clock duty cycle
40
tsl(I)
1
Input clock slew rate
TSTAB
CLK stabilization
Low-to high level propagation
CLK_IN to any output
tPLH1
delay time
High-to low level propagation
CLK_IN to any output
tPHL1
delay time
ten
Output enable time
PD# to any output
5
tdis
PD# to any output
5
Output disable time
tjit (per)
-75
Period jitter
tjit(hper)
-75
Half-period jitter
tsl(o)
Over the application
1
Output clock slew rate
frequency range
tcyc-tcyc
-75
Cycle to Cycle Jitter
t(spo)
-50
Static Phase Offset
tskew
Output to Output Skew
40
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,
were the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics are guaranteed for application frequency range. The
PLL Locks over the Max Clock Frequency range, but the device doe not
necessarily meet other timing parameters.
4. Does not include jitter.
0830A—09/10/04
5
MAX
333
UNITS
MHz
220
MHz
60
2
100
%
v/ns
µs
5.5
ns
5.5
ns
75
75
2.5
75
50
60
ns
ns
ps
ps
v/ns
ps
ps
ps
ICS95V842
Parameter Measurement Information
VDD
V(CLKC)
R = 60Ω
R = 60Ω VDD/2
V(CLKC)
ICS95V842
GND
Figure 1. IBIS Model Output Load
VDD/2
C = 14 pF -V
DD/2
ICS95V842
R = 10Ω
Z = 60Ω
SCOPE
Z = 50Ω
R = 50Ω
V(TT)
R = 10Ω
Z = 60Ω
Z = 50Ω
R = 50Ω
V(TT)
C = 14 pF
-VDD/2
-VDD/2
NOTE: V(TT) = GND
Figure 2. Output Load Test Circuit
YX, FB_OUTC
YX, FB_OUTT
tc(n)
tc(n+1)
tjit(cc) = tc(n) ± tc(n+1)
0830A—09/10/04
Figure 3. Cycle-to-Cycle Jitter
6
ICS95V842
Parameter Measurement Information
CLK_INC
CLK_INT
FB_INC
FB_INT
t( ) n
n=N
t( ) n
1
t( )=
N
(N is a large number of samples)
Figure 4. Static Phase Offset
YX #
YX
YX, FB_OUTC
YX, FB_OUTT
t(SK_O)
Figure 5. Output Skew
YX, FB_OUTC
YX, FB_OUTT
YX, FB_OUTC
YX, FB_OUTT
1
fO
t(jit_per) = tC(n) - 1
fO
Figure 6. Period Jitter
0830A—09/10/04
7
t ( ) n+1
ICS95V842
Parameter Measurement Information
YX, FB_OUTC
YX, FB_OUTT
t (hper_n+1)
t (hper_n)
1
fo
t(jit_Hper) = t(jit_Hper_n) - 1
2xfO
Figure 7. Half-Period Jitter
80%
80%
VID , VOD
Clock Inputs
and Outputs
20%
20%
Rise tsl
Fall tsl
Figure 8. Input and Output Slew Rates
0830A—09/10/04
8
ICS95V842
16-Lead, 150 mil SSOP (QSOP)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
1.35
1.75
.053
.069
A1
0.10
0.25
.004
.010
A2
-1.50
-.059
b
0.20
0.30
.008
.012
c
0.18
0.25
.007
.010
SEE VARIATIONS
D
SEE VARIATIONS
E
5.80
6.20
.228
.244
E1
3.80
4.00
.150
.157
e
0.635 BASIC
0.025 BASIC
L
0.40
1.27
.016
.050
SEE VARIATIONS
SEE VARIATIONS
N
a
0°
8°
0°
8°
ZD
SEE VARIATIONS
SEE VARIATIONS
VARIATIONS
D mm.
N
MIN
4.80
16
MAX
5.00
ZD
(Ref)
0.23
D (inch)
MIN
.189
Reference Doc.: JEDEC Publication 95, MO-137
10-0032
Ordering Information
ICS95V842yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0830A—09/10/04
9
MAX
.197
ZD
(Ref)
.009