DATA SHEET MOS INTEGRATED CIRCUIT µPD16874 QUAD Pch HIGH-SIDE SWITCH FOR USB DESCRIPTION The µPD16874 is a power switch IC with an overcurrent limiter that is used for the power bus of a Universal Serial Bus (USB). This product has Pch power MOSFET circuits, each of which has a low-on resistance (100 mΩ TYP.), in its switching block. In addition, the IC is also equipped with an overcurrent detector that is essential for a host/hub controller conforming to the USB Standard, so that the IC can report an overcurrent to the controller. Moreover, a thermal shutdown circuit and an undervoltage lockout circuit are also provided as the protection circuits of the IC. This product has four channels of power switches, control input pins, and flag output pins to simultaneously control four USB ports with a single IC. FEATURES • Four P-ch power MOSFET circuits • Overcurrent detector that outputs active-low control signal from detection report pin • Overcurrent limiter to prevent system voltage drop • Thermal shutdown circuit • Undervoltage lockout circuit • Each of four circuits can be turned on and off independently of the others by a control pin. (CTL input: active low) • 16-pin SOP package ORDERING INFORMATION Part Number Package µPD16874GS 16-pin SOP (7.62 mm (300)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S13894EJ1V0DS00 (1st edition) Date Published February 2001 N CP(K) Printed in Japan © 2001 µPD16874 BLOCK DIAGRAM IN (Input) 1 OUT1 2 (Output 1) 15 OUT2 (Output 2) Reference voltage Reference voltage Overcurrent detection Gate control Gate control Overcurrent detection To VDDC pin To VDDC pin FLG1 3 (Flag output 1) 14 FLG2 (Flag output 2) CTL1 4 (Control input 1) 13 CTL2 (Control input 2) Undervoltage lockout circuit Thermal shutdown circuit CTL3 5 (Control input 3) To VDDC pin To VDDC pin 11 FLG4 (Flag output 4) FLG3 6 (Flag output 3) Overcurrent detection Gate control Gate control Overcurrent detection Reference voltage Reference voltage OUT3 (Output 3) 12 CTL4 (Control input 4) 10 7 9 16 8 VDDC (USB controller power supply) IN (Input) OUT4 (Output 4) GND NOTES ON CORRECT USE • No internal resistor is connected to input pins CTL1 (pin 4), CTL2 (pin 13), CTL3 (pin 5), and CTL4 (pin 12). When using the µPD16874, therefore, be sure to set the voltage level of these input pins to “H” or “L”. • Keep the IN pins (pins 1 and 8) at the same potential. • Supply a voltage lower than that supplied to the IN pins (pins 1and 8) to VDDC (pin 9). • FLG1 (pin 3), FLG2 (pin 14), FLG3 (pin 6), and FLG4 (pin 11) are internally pulled up to VDDC (USB controller supply voltage) (resistance: approx. 400 kΩ). Therefore, no external pull-up resistor has to be connected to these pins. 2 Data Sheet S13894EJ1V0DS µPD16874 PIN CONFIGURATION (Top View) IN 1 16 GND OUT1 2 15 OUT2 FLG1 3 14 FLG2 CTL1 4 13 CTL2 CTL3 5 12 CTL4 FLG3 6 11 FLG4 OUT3 7 10 OUT4 IN 8 9 VDDC 16-pin SOP PIN DESCRIPTION Pin No. Pin Name Pin Function 4/5/12/13 CTL1/CTL2/CTL3/CTL4 Control input (See the truth table below). TTL input 3/6/11/14 FLG1/FLG2/FLG3/FLG4 Detection flag (output): Active-low, Nch open-drain 16 GND 1/8 IN Power input: Source of MOSFET for output. Power supply to internal circuitry of IC 9 VDDC USB controller power supply. Each FLG output is connected via internal resistor. 2/7/10/15 OUT1/OUT2/OUT3/OUT4 Ground Switch output: Drain of MOSFET for output. Usually, connected to load. TRUTH TABLE (H: High level, L: Low level, ON: Output on, OFF: Output off, X: H or L) CTLn (In) FLGn (Out) OUTn (Out) Operation mode L H ON OUTn ON H H OFF OUTn OFF H (all) H (all) OFF (all) L L ON X L (all) OFF (all) Thermal shutdown circuit operation X L (all) OFF (all) Undervoltage lockout circuit operation Standby mode OUTn overcurrent detection Data Sheet S13894EJ1V0DS 3 µPD16874 ABSOLUTE MAXIMUM RATINGS (Unless otherwise specified, TA = 25°°C) Parameter Symbol Conditions Ratings Unit Input voltage VIN −0.3 to +6 V Flag voltage VFLG −0.3 to +6 V Flag current IFLG 50 mA Output voltage VOUT VIN+0.3 V Output current IOUT +0.5 (VIN = VCTL = 5 V) A DC −0.1 (VIN = 0 V, VOUT = 5 V) Pulse width ≤ Single 100 µs pulse Control input +3 VCTL Note 1 −0.3 to +6 V Total power dissipation PD 900 mW Operating temperature range TA −40 to +85 °C +150 °C −55 to +150 °C Note 2 Junction temperature TCH MAX Storage temperature Tstg 1. When mounted on a glass epoxy board measuring 90 mm × 90 mm × 1.6 mm thick Notes 2. This product has an internal thermal shutdown circuit (operating temperature: 150°C or higher TYP.) RECOMMENDED OPERATING RANGE (Unless otherwise specified, TA = 25°°C) Parameter Symbol MIN. TYP. MAX. Unit Input voltage VIN +4 +5.5 V Operating temperature range TA 0 +70 °C ELECTRICAL SPECIFICATIONS DC Characteristics (Unless otherwise specified, VIN = +5 V, TA = +25°°C) Parameter Current consumption Symbol IDD Conditions MIN. TYP. MAX. Unit 1 5 µA VCTL = 0 V, OUT: open 150 µA 1.0 V VCTL = VIN (all CTL pins), OUT: Open Input voltage, low VIL CTL pin Input voltage, high VIH CTL pin Control input current ICTL VCTL = 0 V 0.01 1 µA VCTL = VIN 0.01 1 µA TA = 0 to +70°C, IOUT = 500 mA 100 140 mΩ 10 µA 0.9 1.25 A 2.0 V Output MOSFET on-resistance RON Output leakage current IO LEAK Overcurrent detector threshold ITH TA = 0 to +70°C Flag output resistance RON F IL = 10 mA 10 25 Ω Flag leakage current IO LEAK F VFLAG = 5 V 0.01 1 µA Undervoltage lockout circuit operating voltage VUVLO VIN: When rising 2.2 2.5 2.8 V VIN: When falling 2.0 2.3 2.6 V Hysteresis width 0.05 0.25 V 4 Data Sheet S13894EJ1V0DS 0.6 µPD16874 ELECTRICAL SPECIFICATIONS AC Characteristics (Unless otherwise specified, VIN = +5 V, TA = +25°°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.5 5 8 ms 10 µs Output transition rise time (ON) tRISE RL = 10 Ω per output Output transition fall time (OFF) tFALL RL = 10 Ω per output Overcurrent detection delay time tOVER Overcurrent detection output rise time tSRISE RL = 10 Ω per output 2.5 Minimum CTL high time tCTL CTL : L→H→L 20 µs 20 5 8 ms µs POINTS OF MEASUREMENT Output Transition Rise Time (ON)/Output Transition Fall Time (OFF) CTL pin: H→L/L→H 5 V/3.3 V 90% CTL 0V tRISE tFALL 5V 90% 90% VOUT 10% 0V Overcurrent Detection Delay Time/Minimum CTL High Time ITH IOUT VOUT tOVER tSRISE (Internal time) FLG 90% tCTL CTL 10% 10% Data Sheet S13894EJ1V0DS 5 µPD16874 DESCRIPTION OF FUNCTIONS 1. Overcurrent Detection This IC detects an overcurrent in a range of 0.6 to 1.25 A (0.9 A TYP.) (the USB Standard defines that an overcurrent is 0.5 A MAX.). When the IC detects an overcurrent, the FLG pin goes low (active) and reports the result of detection to the control IC. At this time, the switch is kept ON and the current limiter is activated. In this way, an overcurrent status that lasts for a long time can be prevented. By deasserted the CTL pin inactive by the control IC, the switch is turned OFF and the FLG pin goes back high. Therefore, the CTL signal must be deasserted inactive as soon as the controller IC has detected that the FLG pin has gone low, to avoid overheating this IC. Once the switch has been turned OFF, it turns back ON again only when the CTL signal is asserted active while the FLG pin is high. To prevent an inrush current being detected by mistake, a deadband time (overcurrent detection delay time) is set to elapse before the overcurrent detector is activated. The duration of this deadband time is 20 µs TYP. While the overcurrent limiter is activated, the power consumption of the device may abruptly increase. As a result, the junction temperature may also rise. Make sure that the CTL signal is deasserted inactive and that the switch is turned OFF before the absolute maximum rating is exceeded. 2. Undervoltage Lockout Circuit (UVLO) This circuit prevents malfunctioning of the switch due to fluctuation in supply voltage. When power is turned on (2.5 V or less TYP.) or off (2.3 V or less TYP.), the OUT and FLG pins have the following status: OUT: OFF FLG: “L” (= 0 V) 5V Output voltage 2.3 V 2.5 V 5V Input voltage The above figure does not show the actual waveform. For the related characteristic waveform, refer to Major Characteristic Curves. 6 Data Sheet S13894EJ1V0DS µPD16874 3. Behavior When Power is Turned ON/OFF This IC performs a soft-start operation on power application. This is to prevent an overcurrent from flowing through the IC on power application while the high-capacity capacitor connected to the output pin is charged. Power ON: Soft start (2.5 to 8 ms) Power OFF: No control (10 µs MAX.) 5V Vin 0V 2.5 ms MIN. 8 ms MAX. 10 µ s MAX. 5V Vout 0V The above figure does not show the actual waveform. For the related characteristic waveform, refer to Major Characteristic Curves. Data Sheet S13894EJ1V0DS 7 µPD16874 OPERATION SEQUENCE Power ON/OFF 5V IN (Input) GND 5V OUT (Output) GND 5V Flg (Output) GND 5V 5V CTL (Input) GND Overcurrent detection threshold Iout Note If the CTL signal is asserted active after power has been turned ON, OUT executes the soft-start operation (output transition time: 8 ms MAX.). In addition, FLG output is fixed to “L” if the supply voltage is lower than the operating voltage of the undervoltage lockout circuit (UVLO) on power application. If all the CTL pins are inactive when power is supplied, the IC enters the standby status (IDD = 5 µA MAX.). When Control Signals Are Input 5V IN (Input) GND 5V OUT (Output) FLG (Output) CTL (Input) 8 GND 5V GND 5V GND Data Sheet S13894EJ1V0DS µPD16874 On Detection of Overcurrent 5V IN (Input) 5V Flg (Output) GND 5V CTL (Input) GND 5V OUT (Output) IOUT GND Overcurrent detection threshold When overcurrent (inrush current) is detected Slow start period When overcurrent is detected (output is short-circuited) If an overcurrent is detected after the overcurrent detection delay time of 20 µs, the IC executes a slow-start operation again. If an overcurrent is detected while the IC is executing the slow-start operation again, it is assumed that the output is short-circuited and the FLG pin goes low. When the CTL signal is deasserted inactive, OUT is turned OFF and FLG goes high. If the CTL signal is asserted active, OUT is turned back ON unless the undervoltage lockout circuit or thermal shutdown circuit is activated. Data Sheet S13894EJ1V0DS 9 µPD16874 When Thermal Shutdown Circuit Operates 5V IN (Input) Standby status Non-standby status GND 5V OUT (Output) FLG (Output) GND 5V GND 5V CTL (Input) Tch GND Thermal shutdown circuit operating temperature (falling) Thermal shutdown circuit operating temperature (rising) While the thermal shutdown circuit is activated, the output pins are in the OFF status. However, the IC does not enter the standby status even if all the CLT pins are deasserted inactive at the same time. The thermal shutdown circuit is not activated even if the junction temperature exceeds 150°C TYP. while the IC is in the standby mode (when all the CTL pins are inactive). TEST CIRCUIT +5 V 10 Ω 10 Ω 10 1 IN 2 OUT1 OUT2 15 3 FLG1 FLG2 14 4 CTL1 CTL2 13 5 CTL3 CTL4 12 6 FLG3 FLG4 11 7 OUT3 OUT4 10 8 IN GND 16 VDDC Data Sheet S13894EJ1V0DS 9 10 Ω 10 Ω µPD16874 MAJOR CHARACTERISTIC CURVES (Unless otherwise specified, TA = +25°°C, VIN = +5 V) Total Power Dissipation PT vs. Ambient Temperature TA Total consumption PT (mW) 1200 900 600 300 0 −40 0 40 80 120 160 200 Ambient temperature TA (˚C) Output On-Resistance RON vs. Supply Voltage VIN 120 100 80 60 40 20 0 −20 0 20 40 60 80 Output on-resistance RON (mΩ) Output on-resistance RON (mΩ) Output On-Resistance RON vs. Ambient Temperature TA 140 140 120 100 80 60 40 20 0 3.5 4.0 4.5 Ambient temperature TA (˚C) 160 140 120 100 80 20 0 20 40 60 100 80 20 4.0 0.06 0.04 0.02 60 Ambient temperature TA (˚C) 80 Current consumption in standby mode ( µ A) Current consumption in standby mode ( µ A) 0.08 40 4.5 5.0 5.5 6.0 6.5 Supply voltage (V) Current Consumption (Standby) IDD vs. Ambient Temperature TA 20 6.5 120 0 3.5 80 0.10 0 6.0 140 Ambient temperature TA (˚C) 0.00 −20 5.5 Current Consumption IDD vs. Supply Voltage VIN Current consumption ( µ A) Current consumption ( µ A) Current Consumption IDD vs. Ambient Temperature TA 180 0 −20 5.0 Supply voltage (V) Current Consumption (Standby) IDD vs. Supply Voltage VIN 0.10 0.08 0.06 0.04 0.02 0.00 3.5 Data Sheet S13894EJ1V0DS 4.0 4.5 5.0 5.5 6.0 6.5 Supply voltage (V) 11 µPD16874 MAJOR CHARACTERISTIC CURVES (Unless otherwise specified, TA = +25°°C, VIN = +5 V) Input Voltage VI vs. Ambient Temperature TA Input Voltage VI vs. Supply Voltage VIN 1.70 1.70 Input voltage, low VIL (V) Input voltage, high VIH (V) Input voltage, low VIL (V) Input voltage, high VIH (V) 1.80 VIH 1.60 VIL 1.50 1.40 1.30 −20 0 20 40 60 1.65 1.60 1.55 1.50 3.5 80 VIH VIL 4.0 4.5 Ambient temperature TA (˚C) 1.2 1.0 0.8 0.6 0.4 0.2 0 20 40 60 80 1.0 0.8 0.6 0.4 0.2 0.0 3.5 4.0 4.5 Undervoltage lockout circuit operating voltage VUVLO (V) 12 Voltage (V) Voltage (V) Output voltage 4 2 1 0 2 3 4 0 Undervoltage Lockout Circuit Operating Voltage Characteristics 50 40 UVLO (L H) 30 20 UVLO (H L) 20 40 0.4 Time ( µ s) Time ( µ s) 0 Output voltage 3 0 00 −20 6.5 5 1 10 6.0 6 3 1 5.5 Output Fall Delay Time Characteristics 4 0 5.0 Supply voltage (V) Input voltage 2 6.5 1.2 Output Rise Delay Time Characteristics 5 6.0 1.4 Ambient temperature TA (˚C) 6 5.5 Overcurrent Threshold ITH vs. Supply Voltage VIN Overcurrent detection value (A) Overcurrent detection value (A) Overcurrent Threshold ITH vs. Ambient Temperature TA 1.4 0.0 −20 5.0 Supply voltage (V) 60 80 Ambient temperature TA (˚C) Data Sheet S13894EJ1V0DS 0.8 1.2 µPD16874 APPLICATION CIRCUIT 3.3 V 5V VBUS D+ D+ D- D− IN USB controller VDDC Enable GND GND 1µ F 150 µ F CTL1 VBUS CTL2 OUT1 D+ CTL3 D− CTL4 OUT2 FLG1 Over current 150µ F GND FLG2 OUT3 FLG3 FLG4 OUT4 VBUS 150 µ F µ PD16874 D+ D− GND VBUS 150 µ F D+ D− GND USB connector Data Sheet S13894EJ1V0DS 13 µPD16874 PACKAGE DRAWING 16-PIN PLASTIC SOP (7.62 mm (300)) 16 9 detail of lead end P 1 8 A H F I G J S B N S L K C D M M E NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 10.2±0.2 B 0.78 MAX. C 1.27 (T.P.) D 0.42 +0.08 −0.07 E 0.1±0.1 F 1.65±0.15 G 1.55 H 7.7±0.3 I 5.6±0.2 J 1.1±0.2 K 0.22 +0.08 −0.07 L 0.6±0.2 M 0.12 N 0.10 P 3° +7° −3° P16GM-50-300B-6 14 Data Sheet S13894EJ1V0DS µPD16874 RECOMMENDED SOLDERING CONDITIONS The µPD16874 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended, contact your NEC sales representative. Surface Mount Type For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). µPD16874GS Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher), Note Count: two times, Exposure limit: Not limited IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher), Note Count: two times, Exposure limit: Not limited VP15-00-2 Wave soldering Solder bath temperature: 260°C Max., Time: 10 sec. Max., Count: once, Note Exposure limit: not limited WS60-00-1 Partial heating Pin temperature: 300°C Max., Time: 3 sec. Max., Exposure limit: not limited Note Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Cautions Do not use different soldering methods together (except for partial heating). REFERENCE Quality Grades on NEC semiconductor Devices C11531E Semiconductor Device Mounting Technology Manual C10535E NEC Semiconductor Device Reliability/Quality Control System C10983E Semiconductor Selection Guide X10679X Data Sheet S13894EJ1V0DS 15 µPD16874 [MEMO] 16 Data Sheet S13894EJ1V0DS µPD16874 [MEMO] Data Sheet S13894EJ1V0DS 17 µPD16874 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 18 Data Sheet S13894EJ1V0DS µPD16874 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7 Data Sheet S13894EJ1V0DS 19