PCS5I9658 November 2006 rev 0.3 3.3V 1:10 LVCMOS PLL Clock Generator Features and the reference clock frequency determines the VCO • 1:10 PLL based low-voltage clock generator frequency. Both must be selected to match the VCO • Supports zero-delay operation • 3.3V power supply • Generates clock signals up to 250MHz • Maximum output skew of 120pS • Differential LVPECL reference clock input • External PLL feedback • Drives up to 20 clock lines • 32 lead LQFP & TQFP Packages • Pin and function compatible to the MPC958 and frequency range. The internal VCO of the PCS5I9658 is running at either 2x or 4x of the reference clock frequency. The PCS5I9658 has a differential LVPECL reference input along with an external feedback input. The PCS5I9658 is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. MPC9658 The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other Functional Description The PCS5I9658 is a 3.3V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250MHz and output skews less than 120pS the device meets the needs of the most demanding clock applications. The PCS5I9658 is specified for the temperature range of 0°C to +70°C. The PCS5I9658 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the PCS5I9658 requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125MHz or 100 to 250MHz. The two available post-PLL PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The PCS5I9658 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50Ω transmission lines. For series terminated transmission lines, each of the PCS5I9658 outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP & TQFP Packages. dividers selected by VCO_SEL (divide-by-2 or divide-by-4) PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. PCS5I9658 November 2006 rev 0.3 Block Diagram Q VCC 2-25k PCLK PCLK Q 0 & Ref VCC VCO 0 ÷1 0 1 ÷2 1 ÷2 Q 1 Q PLL Q 200-500MHz 25k FB_IN VCC Q FB Q 3-25k Q PLL_EN Q VCO_SEL Q9 BYPASS QFB MR/OE 25k GND Q5 VCC Q4 GND Q3 Q2 Pin Configuration VCC Figure 1. PCS5I9658 Logic Diagram 24 23 22 21 20 19 18 17 GND 25 16 Q6 Q1 26 15 VCC VCC 27 14 Q7 Q0 28 13 GND PCS5I9658 9 1 2 3 4 5 6 7 8 GND 10 32 PCLK 31 PCLK VCC VCO_SEL MR/OE VCC PLL_EN Q8 11 BYPASS 12 30 FB_IN 29 QFB VCC_PLL GND Q9 GND Figure 2. PCS5I9658 32-Lead Package Pinout (Top View) 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 2 of 15 PCS5I9658 November 2006 rev 0.3 Table 1: Pin Configuration Pin # Pin Name 6 7 2 PCLK, PCLK FB_IN 32 VCO_SEL I/O Type Input LVPECL Function LVPECL reference clock signal Input LVCMOS PLL feedback signal input, connect to QFB Input LVCMOS Operating frequency range select Input LVCMOS PLL and output divider bypass select Input LVCMOS PLL enable/disable Input LVCMOS Output enable/disable (high-impedance tristate) and device reset Q0-9 Output LVCMOS Clock outputs QFB Output LVCMOS Clock output for PLL feedback, connect to FB_IN GND Supply Ground 1 VCC_PLL Supply VCC 11,15,19, 23,27,31 VCC Supply VCC 3 4 5 28,26,24, 22,20,18, 16,14,12, 10 30 8,9,13,17 21,25,29 BYPASS PLL_EN MR/OE Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 2: Function Table Control Default 0 1 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. PCS59658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the VCO output1 BYPASS 1 Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. PCS59658 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the output dividers. VCO_SEL 1 VCO ÷ 1 (High frequency range). fREF = fQ0-9 =2. fVCO VCO ÷ 2 (Low frequency range). fREF =fQ0-9 =4.fVCO Outputs enabled (active) Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). PLL_EN MR/OE 0 1 Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 3 of 15 PCS5I9658 November 2006 rev 0.3 Table 3: Absolute Maximum Ratings1 Symbol Characteristics Min Max Unit V VCC Supply Voltage -0.3 3.9 VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VCC+0.3 V ±20 mA ±50 mA 125 °C VOUT IIN IOUT TS DC Input Current DC Output Current Storage Temperature -65 Condition Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Table 4: GENERAL SPECIFICATIONS Symbol Characteristics Min Typ Max VCC÷2 Unit VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V 200 Condition V LU Latch-Up Immunity CPD Power Dissipation Capacitance 10 pF Per output CIN Input Capacitance LQFP 32 Thermal resistance junction to ambient JESD 51-3, single layer test board 4.0 pF Inputs Natural convection θJA JESD 51-6, 2S2P multilayer test board θJC LQFP 32 Thermal resistance junction to case mA 83.1 86.0 °C/W 73.3 68.9 75.4 70.9 °C/W 63.8 57.4 65.3 59.6 °C/W 59.0 54.4 52.5 60.6 55.7 53.8 °C/W °C/W 50.4 47.8 51.5 48.8 °C/W 23.0 26.3 °C/W 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. °C/W °C/W °C/W °C/W 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min MIL-SPEC 883E Method 1012.1 4 of 15 PCS5I9658 November 2006 rev 0.3 Table 5: DC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C) Symbol Characteristics VIH Input high voltage VIL VOH Input low voltage Peak-to-peak input voltage (PCLK) Common Mode Range (PCLK) Output High Voltage VOL Output Low Voltage3 ZOUT Output impedance VPP 1 VCMR IIN ICC_PLL ICCQ Input Current Min Typ 2.0 Max Unit VCC +0.3 V 0.8 V LVCMOS mV LVPECL V LVPECL V IOH=-24 mA2 V V IOL=24mA IOL=12mA 250 VCC-0.6 1.0 2.4 0.55 0.30 14 -17 4 Maximum PLL Supply Current Maximum Quiescent Supply Current 12 13 Condition LVCMOS Ω ±200 µA VIN=VCC or GND 15 15 mA mA VCC_PLL Pin All VCC Pins Note: 1. VCMR (DC) is the cross point of the differential input signal. Functional operation is obtained ,when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2.The PCS5I9658 is capable of driving 50Ωtransmission lines on the incident edge. Each output drives one 50Ωparallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ωseries terminated transmission lines. 3.The PCS5I9658 output levels are compatible to the MPC958 output levels. 4.Inputs have pull-down or pull-up resistors affecting the input current. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 5 of 15 PCS5I9658 November 2006 rev 0.3 Table 6: AC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1 Symbol Characteristics fREF fVCO fMAX Input reference frequency PLL mode, external feedback ÷2 feedback2 3 ÷4 feedback Input reference frequency in PLL bypass mode4 VCO operating frequency range5 3 Output Frequency ÷2 feedback 4 ÷4 feedback tsk(O) Peak-to-peak input voltage PCLK Common Mode Range PCLK Input Reference Pulse Width7 Propagation Delay (static phase offset) 8 PCLK to FB_IN fREF=100MHz any frequency Propagation Delay PLL and divider bypass, PCLK to Q0-9 Output-to-output Skew9 DC Output duty cycle10 VPP VCMR6 tPW,MIN t(Ø) tPD tR ,tF tPLZ, HZ tPZL, LZ Min Max Unit 100 50 250 125 MHz MHz 0 250 MHz 200 100 50 500 250 125 MHz MHz MHz PLL locked PLL locked 500 1000 mV LVPECL 1.2 VCC-0.9 V LVPECL 2.0 +80 +125 pS pS 1.0 4.0 120 (T÷2) +400 1.0 7.0 6.0 nS pS T÷2 nS nS nS tJIT(CC) Cycle-to-cycle jitter 80 pS Period Jitter I/O Phase Jitter fVCO=500MHz and ÷ 2 feedback, RMS (1σ)11 fVCO=500MHz and ÷ 4 feedback, RMS (1σ) 12 ÷2 feedback3 PLL closed loop bandwidth 4 PLL mode, external feedback ÷4 feedback Maximum PLL Lock Time 80 pS 5.5 6.5 pS pS MHz MHz mS BW tLOCK 6-20 2-8 10 PLL locked pS tJIT(PER) tJIT(Ø) Condition PLL locked PLL locked nS -70 -125 (T÷2) -400 0.1 Output Rise/Fall Time Output Disable Time Output Enable Time Typ 0.55 to 2.4V Note:1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. ÷2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0. 3.÷4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0. 4.In bypass mode, the PCS5I9658 divides the input reference clock. 5.The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB. 6.VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(Ø). 7.Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF. 100% and DCREF,MAX = 100% - DCREF,MIN. 8.Valid for fREF=50MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(Ø) [pS] = 50 pS ± (1÷(120 . fREF)). 9.See application section for part-to-part skew calculation in PLL zero-delay mode. 10.Output duty cycle is DC = (0.5 ± 400pS. fOUT) V 100%. E.g. the DC range at fOUT=100MHz is 46%<DC<54%. T = output period. 11.See application section for a jitter calculation for other confidence factors than 1 and a characteristic for other VCO frequencies. 12.-3 dB point of PLL transfer characteristics. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 6 of 15 PCS5I9658 November 2006 rev 0.3 Applications Information Driving Transmission Lines The PCS5I9658 supports output clock frequencies from 50 to 250MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500MHz for stable and optimal operation. Two operating frequency ranges are supported: 50 to 125MHz and 100 to 250 MHz. Table 7 illustrates the configurations supported by the PCS5I9658. PLL zero-delay is supported if BYPASS=1, PLL_EN=1 and the input frequency is within the specified PLL reference frequency range. Table 7: PCS5I9658 Configurations (QFB connected to FB_IN) BYPASS PLL_ EN VCO_ SEL Operation 0 X X Test mode: PLL and divider bypass 1 0 0 1 0 1 Ratio Frequency Output range (fQ0-7) VCO fQ0-9 =fREF 0-250MHz n/a Test mode: PLL bypass fQ0-9 =fREF ÷ 2 0-125MHz n/a Test mode: PLL bypass fQ0-9 =fREF ÷ 4 0-62.5MHz n/a 1 1 0 PLL mode (high frequency range) fQ0-9 =fREF 100 to 250MHz fVCO =fREF. 2 1 1 1 PLL mode (low frequency range) fQ0-9 =fREF 50 to 125MHz fVCO =fREF. 4 CF = 22 µF RF = 5-15Ω Power Supply Filtering RF The PCS5I9658 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The PCS5I9658 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the PCS5I9658. Figure 3. illustrates a typical power supply filter scheme. The PCS5I9658 frequency and phase stability is most susceptible to noise with spectral content in the 100KHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 12mA (20 mA maximum), assuming that a minimum of 2.835V must be maintained on the VCC_PLL pin. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide attenuation greater than 40 dB for VCC VCC_PLL CF 10 nF PCS5I9658 VCC 33…100 nF Figure 3. VCC_PLL Power Supply Filter noise whose spectral content is above 100KHz. In the example RC filter shown in Figure 3.“VCC_PLL Power Supply Filter”, the filter cut-off frequency is around 3-5KHz and the noise attenuation at 100KHz is better than 42dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the PCS5I9658 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 7 of 15 PCS5I9658 November 2006 rev 0.3 in this section should be adequate to eliminate power supply noise related problems in most designs. Using the PCS5I9658 in zero-delay applications Nested clock trees are typical applications for the PCS5I9658. Designs using the PCS5I9658, as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the PCS59658 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. Calculation of part-to-part skew Figure 4. PCS5I9658 max device-to-device skew Due to the statistical nature of I/O jitter a RMS value (1σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8: Confidence Factor CF Probability of clock edge within the CF distribution ± 1σ 0.68268948 ± 2σ 0.95449988 ± 3σ 0.99730007 ± 4σ 0.99993663 ± 5σ 0.99999943 ± 6σ 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (±3σ) is assumed, resulting in a worst case timing uncertainty from input to any output of -214pS to 224pS relative to PCLK (fREF = 100MHz, fVCO = 400MHz): FB=÷4, tjit(φ)=8pS RMS at The PCS5I9658 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more PCS5I9658 are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: tSK(PP) = t(φ) + tSK(O) + tPD, LINE(FB) + tJIT(φ) .CF tSK(PP) = [–214pS...224pS] + tPD, LINE(FB) This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: Due to the frequency dependence of the I/O jitter, Figure 5. can be used for a more precise timing performance analysis. PCLKCommon [(8Ps . –3)...(8pS . 3)] + tPD, LINE(FB) tPD,LINE (FB) -t(Ø) QFBDevice 1 tSK(PP) = [–70pS...80pS] + [–120pS...120pS] + tJIT(Ø) Any QDevice 1 +tSK(O) +t(Ø QFBDevice 2 tJIT(Ø) Any QDevice 2 Max. skew Figure 5. Maximum I/O Jitter versus frequency +tSK(O) tSK(PP) 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 8 of 15 PCS5I9658 November 2006 rev 0.3 looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Driving Transmission Lines The PCS5I9658 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20Ω the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. PCS5I9658 OUTPUT BUFFER IN 14Ω RS = 36 Ω|| 36Ω R0 = 14Ω VL = 3.0 ( 25 ÷(18+14+25)) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 1.0 0.5 Z0=50Ω RS=36Ω Z0 = 50Ω|| 50Ω VOLTAGE (V) This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCS59658 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the PCS5I9658 clock driver is effectively doubled due to its capability to drive multiple lines. VL = VS ( Z0 ÷(RS+R0 +Z0)) OUTA 0 PCS5I9658 OUTPUT BUFFER IN 2 Z0=50Ω RS=36Ω 4 6 OUTB0 14Ω RS=36Ω Z0=50Ω OUTB1 Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the PCS5I9658 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43pS exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the PCS5I9658. The output waveform in Figure 7. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen 8 10 12 14 TIME (nS) Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 8. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. PCS5I9658 OUTPUT BUFFER IN RS=22Ω 14Ω RS=22Ω Z0=50Ω Z0=50Ω 14Ω + 22Ω || 22Ω = 50Ω || 50Ω 25Ω = 25Ω Figure 8. Optimized Dual Line Termination 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 9 of 15 PCS5I9658 November 2006 rev 0.3 Z0=50Ω Z0=50Ω Differential Pulse Generator Z=50Ω RT=50Ω RT=50Ω VTT VTT Figure 9. PCLK PCS5I958 AC test reference VCC VCC ÷2 GND VCC VCC ÷2 tSK(O) GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 10. Output–to–Output Skew tSK(O) PCLK VPP = 0.8V VCMR = VCC – 1.3V PCLK VCC VCC ÷2 FB_IN t(PD) GND Figure 11. Propagation Delay (t(PD)). Static phase offset test reference 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 10 of 15 PCS5I9658 November 2006 rev 0.3 VCC VCC ÷2 GND tP T0 DC= (tP ÷T0 Χ 100%) The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage. Figure 12. Output Duty Cycle (DC) CCLK FB_IN TJIT(Ø) =│T0-T1 mean│ The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 13.I/O Jitter T0 TN TN-1 TJIT(CC) =│TN-TN-1│ The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs TJIT(PER) =│TN-1/f0│ The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 15. Period Jitter Figure 14. Cycle-to-cycle Jitter VCC = 3.3V 2.4 0.55 tF tR Figure 16. Output Transition Time Test Reference 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 11 of 15 PCS5I9658 November 2006 rev 0.3 Package Information 32-lead TQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.031 BASE 0.8 BASE 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 12 of 15 PCS5I9658 November 2006 rev 0.3 32-lead LQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0630 … 1.6 A1 0.0020 0.0059 0.05 0.15 A2 0.0531 0.0571 1.35 1.45 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.20 e a 0.031 BASE 0° 7° 0.8 BASE 0° 7° 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 13 of 15 PCS5I9658 November 2006 rev 0.3 Ordering Information Part Number Marking Package Type Operating Range PCS5I9658G-32-ER PCS5I9658G 32-pin TQFP, Green Industrial PCS5I9658G-32-LR PCS5I9658G 32-pin LQFP –Tape and Reel, Green Industrial Device Ordering Information P C S 5 I 9 6 5 8 G - 3 2 - L R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 14 of 15 PCS5I9658 November 2006 rev 0.3 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS5I9658 Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V 1:10 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 15 of 15