SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
D
Widebus Family
UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Mode
Operates From 1.65 V to 3.6 V
Max tpd of 4.4 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Simultaneously Generates and Checks
Parity
Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering information
This 18-bit (dual-octal) noninverting registered
transceiver is designed for 1.65-V to 3.6-V VCC
operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit
parity transceiver with registers. The device can
operate as a feed-through transceiver or it can
generate/check parity from the two 8-bit data
buses in either direction.
DGG PACKAGE
(TOP VIEW)
1CLKENAB
LEAB
CLKAB
1ERRA
1APAR
GND
1A1
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
2A5
VCC
2A6
2A7
2A8
GND
2APAR
2ERRA
OEAB
SEL
2CLKENAB
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
1CLKENBA
LEBA
CLKBA
1ERRB
1BPAR
GND
1B1
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
2B5
VCC
2B6
2B7
2B8
GND
2BPAR
2ERRB
OEBA
ODD/EVEN
2CLKENBA
The SN74ALVCH16901 features independent
clock (CLKAB or CLKBA), latch-enable (LEAB or
LEBA), and dual 9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and
parity-select (ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The
direction of data flow is controlled by OEAB and OEBA. When SEL is low, the parity functions are enabled. When
SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered transceiver.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − DGG
Tape and reel
SN74ALVCH16901DGGR
ALVCH16901
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and UBT are trademarks of Texas Instruments.
Copyright 2004, Texas Instruments Incorporated
!"#$%&" ' ()##*& %' "! +),-(%&" .%&*/
#".)(&' ("!"#$ &" '+*(!(%&"' +*# &0* &*#$' "! *1%' '&#)$*&'
'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The A and B I/Os and APAR and BPAR inputs have bus-hold circuitry. Active bus-hold circuitry holds unused
or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is
not recommended.
Function Tables
FUNCTION†
INPUTS
CLKENAB
OEAB
LEAB
CLKAB
A
OUTPUT
B
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
L
L
X
X
H
B0‡
L
L
L
↑
L
L
L
L
L
↑
H
L
L
L
H
B0‡
L
X
B0§
† A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA,
LEBA, and CLKENBA.
‡ Output level before the indicated steady-state input conditions were
established
§ Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low
L
L
L
H
X
PARITY ENABLE
INPUTS
2
OPERATION OR FUNCTION
SEL
OEBA
OEAB
L
H
L
Parity is checked on port A and is generated on port B.
L
L
H
Parity is checked on port B and is generated on port A.
L
H
H
Parity is checked on port B and port A.
L
L
L
Parity is generated on port A and B if device is in FF mode.
H
L
L
H
L
H
H
H
L
H
H
H
QA data to B, QB data to A
Parity functions are disabled;
device acts as a standard
18-bit registered transceiver.
POST OFFICE BOX 655303
QB data to A
QA data to B
Isolation
• DALLAS, TEXAS 75265
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
Function Tables (Continued)
PARITY
INPUTS
OUTPUTS
SEL
OEBA
OEAB
ODD/EVEN
Σ OF INPUTS
A1−A8 = H
Σ OF INPUTS
B1−B8 = H
APAR
BPAR
APAR
ERRA
BPAR
ERRB
L
H
L
L
0, 2, 4, 6, 8
N/A
L
N/A
N/A
H
L
Z
L
H
L
L
1, 3, 5, 7
N/A
L
N/A
N/A
L
H
Z
L
H
L
L
0, 2, 4, 6, 8
N/A
H
N/A
N/A
L
L
Z
L
H
L
L
1, 3, 5, 7
N/A
H
N/A
N/A
H
H
Z
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
L
L
Z
N/A
H
L
L
H
L
N/A
1, 3, 5, 7
N/A
L
H
Z
N/A
L
L
L
H
L
N/A
0, 2, 4, 6, 8
N/A
H
L
Z
N/A
L
L
L
H
L
N/A
1, 3, 5, 7
N/A
H
H
Z
N/A
H
L
H
L
H
0, 2, 4, 6, 8
N/A
L
N/A
N/A
L
H
Z
L
H
L
H
1, 3, 5, 7
N/A
L
N/A
N/A
H
L
Z
L
H
L
H
0, 2, 4, 6, 8
N/A
H
N/A
N/A
H
H
Z
L
H
L
H
1, 3, 5, 7
N/A
H
N/A
N/A
L
L
Z
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
L
H
Z
N/A
L
L
L
H
H
N/A
1, 3, 5, 7
N/A
L
L
Z
N/A
H
L
L
H
H
N/A
0, 2, 4, 6, 8
N/A
H
H
Z
N/A
H
L
L
H
H
N/A
1, 3, 5, 7
N/A
H
L
Z
N/A
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
Z
H
Z
H
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
L
L
Z
L
Z
L
L
H
H
L
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
Z
L
Z
L
L
H
H
L
1, 3, 5, 7
1, 3, 5, 7
H
H
Z
H
Z
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
L
L
Z
L
Z
L
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
L
L
Z
H
Z
H
L
H
H
H
0, 2, 4, 6, 8
0, 2, 4, 6, 8
H
H
Z
H
Z
H
L
H
H
H
1, 3, 5, 7
1, 3, 5, 7
H
H
Z
L
Z
L
PE†
PO‡
Z
PE†
PO‡
Z
L
L
L
L
N/A
N/A
N/A
N/A
L
L
L
H
N/A
N/A
N/A
N/A
Z
Z
† Parity output is set to the level so that the specific bus side is set to even parity.
‡ Parity output is set to the level so that the specific bus side is set to odd parity.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
functional block diagram
LEAB
1CLKENAB
2CLKENAB
CLKAB
OEAB
2
1, 32
2
3
30
35
1A1−1A8
1APAR
1ERRB
5
61
2A1−2A8
2APAR
2ERRB
ODD/EVEN
SEL
28
36
18-Bit
Storage
18
A-Port
Parity
Generate
and
Check
B Data
18
QB
18-Bit
Storage
1B1−1B8
18
QA
18
OEBA
60
B-Port
Parity
Generate
and
Check
A Data
4
1BPAR
1ERRA
2B1−2B8
37
29
2BPAR
2ERRA
34
31
62
2
64, 33
63
CLKBA
1CLKENBA
2CLKENBA
LEBA
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I/O ports (see Notes 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed..
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51−7.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
recommended operating conditions (see Note 4)
VCC
VIH
Supply voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
IOH
IOL
∆t/∆v
MIN
MAX
1.65
3.6
Input voltage
1.7
0.35 × VCC
0.7
High-level output current
VCC = 2.7 V
VCC = 3 V
VCC = 1.65 V
VCC = 2.3 V
Low-level output current
VCC = 2.7 V
VCC = 3 V
Input transition rise or fall rate
V
0.8
0
VCC = 1.65 V
VCC = 2.3 V
V
2
0
Output voltage
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
Low-level input voltage
UNIT
VCC
VCC
V
V
−4
−12
−12
mA
−24
4
12
12
mA
24
10
ns/V
TA
Operating free-air temperature
−40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −100 µA
IOH = −4 mA
VCC
MIN
1.65 V to 3.6 V
VCC − 0.2
1.2
1.65 V
IOH = −6 mA
VOH
IOH = −12 mA
IOH = −24 mA
IOL = 100 µA
Control inputs
Cio
A or B ports
Co
ERR ports
3V
2.4
3V
2
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
±5
3.6 V
1.65 V
25
1.65 V
−25
VI = 0.7 V
VI = 1.7 V
2.3 V
45
2.3 V
−45
VI = 0.8 V
VI = 2 V
3V
75
3V
−75
IO = 0
Other inputs at VCC or GND
UNIT
V
0.45
VI = 0.58 V
VI = 1.07 V
VI = VCC or GND,
One input at VCC − 0.6 V,
∆ICC
Ci
2.2
2.3 V
VI = 0 to 3.6 V‡
VO = VCC or GND
IOZ§
ICC
2.7 V
1.65 V
IOL = 24 mA
VI = VCC or GND
II(hold)
1.7
0.2
IOL = 12 mA
II
2
2.3 V
MAX
1.65 V to 3.6 V
IOL = 4 mA
IOL = 6 mA
VOL
2.3 V
TYP†
V
µA
µA
3.6 V
±500
3.6 V
±10
µA
3.6 V
40
µA
3 V to 3.6 V
750
µA
VI = VCC or GND
VO = VCC or GND
3.3 V
3
pF
3.3 V
7.5
pF
VO = VCC or GND
3.3 V
6
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§ For I/O ports, the parameter IOZ includes the input leakage current.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.8 V
MIN
fclock
tw
tsu
th
Clock frequency
Pulse
duration
Setup time
Hold time
MAX
†
VCC = 2.5 V
± 0.2 V
MIN
MAX
VCC = 2.7 V
MIN
125
MAX
VCC = 3.3 V
± 0.3 V
MIN
125
125
CLK↑
†
3
3
3
LE high
†
3
3
3
A, APAR or B, BPAR before CLK↑
†
1.9
2
1.7
CLKEN before CLK↑
†
2.1
2.1
1.7
A, APAR or B, BPAR before LE↓
†
1.4
1.3
1.2
A, APAR or B, BPAR after CLK↑
†
0.4
0.4
0.5
CLKEN after CLK↑
†
0.5
0.5
0.7
A, APAR or B, BPAR after LE↓
†
0.9
1.1
0.9
UNIT
MAX
MHz
ns
ns
ns
† This information was not available at the time of publication.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
VCC = 1.8 V
TO
(OUTPUT)
MIN
†
fmax
A or B
APAR or BPAR
ODD/EVEN
SEL
tpd
CLKAB or CLKBA
LEAB or LEBA
TYP
VCC = 2.5 V
± 0.2 V
MIN
MAX
125
VCC = 2.7 V
MIN
MAX
125
VCC = 3.3 V
± 0.3 V
MIN
UNIT
MAX
125
MHz
B or A
†
1
5.2
4.8
1
4.4
BPAR or APAR
†
2
8.9
7.6
2
6.7
BPAR or APAR
†
1
5.7
5.2
1
4.7
ERRA or ERRB
†
2
9.7
8.7
2
7.5
ERRA or ERRB
†
1.5
8.7
7.9
1.5
6.8
BPAR or APAR
†
1.5
8.3
7.6
1.5
6.5
BPAR or APAR
†
1
6.1
5.9
1
5.1
A or B
†
1
6.4
5.8
1
5.1
BPAR or APAR
parity feed through
†
1.5
7.1
6.3
1.5
5.6
BPAR or APAR
parity generated
†
2.5
10.2
8.7
2
7.7
ERRA or ERRB
†
2.5
10.5
8.9
2
7.9
A or B
†
1
6
5.5
1
4.8
BPAR or APAR
parity feed through
†
1.5
6.7
6
1.5
5.3
BPAR or APAR
parity generated
†
2.5
9.8
8.3
2
7.4
ERRA or ERRB
†
2.5
9.9
8.5
2
7.5
ns
ten
OEAB or OEBA
B, BPAR or A,
APAR
†
1.4
6.3
6.1
1
5.3
ns
tdis
OEAB or OEBA
B, BPAR or A,
APAR
†
1.3
6.1
5.2
1.5
4.9
ns
ten
OEAB or OEBA
ERRA or ERRB
†
1.4
6.2
5.5
1
4.9
ns
tdis
OEAB or OEBA
ERRA or ERRB
†
1.3
7.3
6.5
1
5.7
ns
ten
SEL
ERRA or ERRB
†
1.4
6.7
6.5
1
5.5
ns
tdis
ERRA or ERRB
SEL
† This information was not available at the time of publication.
†
1.3
6.4
5.4
1.5
4.9
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF,
VCC = 1.8 V
TYP
†
f = 10 MHz
† This information was not available at the time of publication.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
†
VCC = 2.5 V
TYP
VCC = 3.3 V
TYP
22
27
5
8
UNIT
pF
SCES010F − JULY 1995 − REVISED SEPTEMBER 2004
PARAMETER MEASUREMENT INFORMATION
RL
From Output
Under Test
VLOAD
Open
S1
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V
2.5 V ± 0.2 V
2.7 V
3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLZ
VLOAD/2
VM
tPZH
tPHL
VOH
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74ALVCH16901DGGRE4
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74ALVCH16901DGGRG4
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ALVCH16901DGGR
ACTIVE
TSSOP
DGG
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74ALVCH16901DGGR TSSOP
DGG
64
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.4
17.3
1.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALVCH16901DGGR
TSSOP
DGG
64
2000
346.0
346.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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• DALLAS, TEXAS 75265
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