Jul ?$shortyear>
CONFIDENTIAL
CS1500
Digital Power Factor Correction IC
Features & Description
Description
Digital EMI Noise Shaping
The CS1500 is a high-performance power factor correction (PFC)
controller for universal AC input, which uses a proprietary digital
algorithm for discontinuous conduction mode (DCM) with variable
on-time and variable frequency control, ensuring unity power factor.
Excellent Efficiency Under All Load Conditions
Minimal External Devices Required
Optimized Digital Loop Compensation
The CS1500 incorporates all the safety features necessary for
robust and compact PFC stages. In addition, it has burst mode
control to lower the light-load/standby losses to a minimum.
Protection features such as overvoltage, overcurrent, overpower,
open- and short-circuit protection, overtemperature, and brownout
help protect the device during abnormal transient conditions.
Comprehensive Safety Features
• Undervoltage Lockout (UVLO)
• Output Overvoltage Protection
• Input Current Limiting
• Output Overpower Protection
The digital controller optimizes the system stability and transient
performance, simplifies the PFC design, reduces the external
component count and BOM costs. The simple design and
minimum cost makes CS1500 the ideal choice for PFC up to 300
watts.
• Input Brownout Protection
• Open/short Loop Protection for IAC & FB Pins
• Thermal Shutdown
Pin Assignments
NC
1
8
NC
STBY
2
7
VDD
IAC
3
6
GD
FB
4
5
GND
8-lead SOIC
D1
D2
LB
R AC
R FB
R1a
R1 b
BR1
R2a
1
3
C1
AC
Mains
VDD
C2
7
5
NC
NC
IAC
FB
VDD
STBY
GND
GD
R2b
8
4
C3
Regulated
DC Output
2
6
R3
Q1
CS1500
Advance Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
This document contains information for a product under development.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
JUL ‘10
DS849A7
Jul ?$shortyear>
CONFIDENTIAL
CS1500
Table 1. Pin Descriptions
Pin Name
Pin #
I/O
NC
1, 8
-
2
IN
Remote On/Off Control — A voltage below 0.8 V shuts down the IC (not latched) and
brings the device into low power consumption mode. The input has an internal 600 kΩ
pull-up resistor to the VDD pin and should be driven with an open-collector device.
3
IN
Rectifier Voltage Sense — A current proportional to the rectified line voltage (Vrect) is
fed into this pin. The current is measured with an A/D converter.
4
IN
Link Voltage Sense — A current proportional to the output link voltage (Vlink) of the
PFC is fed into this pin. The current is measured with an A/D converter.
5
-
Ground — Current return for both the input signal portion of the IC and the gate driver.
6
OUT
Gate Driver Output — The totem pole stage is able to drive the power MOSFET with a
peak current of 0.5 A source and 1.0 A sink. The high-level voltage of this pin is
clamped at VZ to avoid excessive gate voltages.
7
IN
IC Supply Voltage — Supply voltage of both the input signal portion of the IC and the
gate driver.
STBY
IAC
FB
GND
GD
VDD
2
Description
NC — No connections
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CONFIDENTIAL
CS1500
1. CHARACTERISTICS AND SPECIFICATIONS
1.1 Absolute Maximum Ratings
Pin
Symbol
7
VDD
1,2,3,4,8
-
3,4
-
6
VGD
6
-
Parameter
Value
Unit
VZ
V
Analog Input Maximum Voltage
-0.5 to VZ
V
Analog Input Maximum Current
50
mA
Gate Drive Output Voltage
-0.3 to VZ
V
IGD
Gate Drive Output Current
-1.0 / +0.5
A
PD
Total Power Dissipation @ TA=50° C
600
mW
TA
Operating Ambient Temperature Range1
-40 to +125
ºC
-
TJ
Junction Temperature Operating Range
-40 to +125
ºC
-
TStg
Storage Temperature Range
-65 to +150
ºC
IC Supply Voltage
1.2 Electrical Characteristics
(TA = 25º C, VDD = 13V, -40º < TJ < +125º C, CL=1nF between pin GD and GND, all voltages are measured with respect to
GND; all current are positive when flowing into the IC; unless otherwise specified). Recommended VDD = 10 – 15 V.
Parameter
Condition
Symbol
Min
Typ
Max
Unit
Turn-on Threshold Voltage
VDD Increasing
VDD(on)
8.4
8.8
9.3
V
Turn-off Threshold Voltage (UVLO)
VDD Decreasing
VDD(off)
7.1
7.4
7.9
V
VHys
-
1.3
-
V
IDD = 20 mA
VZ
16.8
17.9
18.5
V
Start-up Supply Current
VDD = VDD(on)
IST
-
68
80
μA
Standby Supply Current
STBY < 0.8 V
ISB
-
80
112
μA
CL=1nF, fSW(max)=70kHz
IDD
-
1.7
1.9
mA
VDD = 13V
fSW(max)
62
66
70
kHz
VDD = 13V
fSW(min)
20
22
23
kHz
VDD = 13V
Dmax
64
66
68
%
Output Source Resistance
IGD = 100mA,VDD = 13V
ROH
-
9
-
Ω
Output Sink Resistance
IGD = -200mA,VDD = 13V
ROL
-
6
-
Ω
CL=1nF,VDD = 13V
tr
-
32
60
ns
VDD Supply Voltage
UVLO Hysteresis
Zener Voltage
VDD Supply Current
Operating Supply Current
PFC Gate Drive
Maximum Operating Frequency6
Minimum Operating Frequency
Maximum Duty Cycle6
Rising Time
6
CL=1nF,VDD = 13V
tf
-
15
30
ns
Output Voltage Low State
IGD = -200mA,VDD = 13V
Vol
-
0.9
1.3
V
Output Voltage High State
IGD = 100mA,VDD = 13V
Voh
11.3
11.8
-
V
Falling Time
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CONFIDENTIAL
Parameter
Feedback &
CS1500
Condition
Symbol
Min
Typ
Max
Unit
25º C
IREF
-
129
-
μA
25º C, 115 VAC
VO(startup)
-
360
-
V
VO(nom)
-
400
-
V
VOVP
415
418
421
V
VOVP(Hy)
-
4
-
V
Protection2,3
Reference Current 1
Output Voltage at Startup Mode
Output Voltage at Normal Mode
Overvoltage Protection Threshold
25º C, 115 VAC
Overvoltage Protection Hysteresis
Overpower Protection Threshold
2,4
25º C, 115 VAC
-
130
-
%
Overpower Protection Recovery
2,4
25º C, 115 VAC
-
100
-
%
Input Brownout Protection Threshold
25º C, GDRV turns off
VBP(th)
62
65
69
Vrms
Input Brownout Recovery Threshold
25º C, GDRV turns on
VBR
76
80
83
Vrms
Thermal Shutdown Threshold
TSD
130
143
155
ºC
Thermal Shutdown Hysteresis
TSD(Hy)
-
9
-
ºC
Logic Threshold Low
-
-
0.8
V
Logic Threshold High
Vdd-0.8
-
-
V
Thermal Protection
STBY Input
1
5
NOTES:
1.
2.
3.
4.
5.
6.
1.3
Thermal Characteristics
Symbol
Parameter
Value
Unit
RθJA
Thermal Resistance (Junction to Ambient)7.
159
ºC / W
RθJC
Thermal Resistance (Junction to Case)7.
39
ºC / W
7.
4
Specifications guaranteed by design & characterization and correlation with statistical process controls.
Specification are based upon a PFC system configured for AC input of 90-265 VAC (Sine), 45/65 Hz, Vlink= 400 V,
RAC = 3 x 1.0 MΩ, RFB = 3 x 1.0 MΩ, C3 = 180 μF, LB = 360 μH, 90 W. For other Vlink voltages, refer to Section 4
Application Example.
Detailed Calculation See Section 4 Application Example.
Overpower protection is scaled to rated power.
STBY is designed to be driven by an open collector. The input is internally pulled up with a 600 kΩ resistor.
Normal operation mode, see Section 3.2.
The package thermal impedance is calculated in accordance with JESD 51.
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CONFIDENTIAL
CS1500
2. TYPICAL ELECTRICAL PERFORMANCE
3.5
13
CL = 1 nF
fSW(max) = 70 kHz
TA = 25 °C
3
12
11
VDD (V)
IDD (mA)
2.5
2
10
1.5
9
1
Startup
8
0.5
Rising
Falling
UVLO
0
0
2
4
6
8
10
12
14
16
18
20
7
-50
0
50
100
150
TEMP (o C)
VDD (V)
Figure 1. Supply Current vs. Supply Voltage
Figure 2. Start-up & UVLO vs. Temp
19
2
18.5
1.5
VZ (V)
UVLO Hysteresis (V)
IDD = 20 mA
1
18
17.5
0.5
0
17
-50
0
50
100
TEMP ( o C)
Figure 3. UVLO Hysteresis vs. Temp
DS849A7
150
-50
0
50
100
150
TEMP ( oC)
Figure 4. VDD Zener Voltage vs. Temp
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Jul ?$shortyear>
CONFIDENTIAL
100
1.8
Operating
90
80
VDD = 13 V
CL = 1 nF
fSW(max) = 70 kHz
1.4
1.2
Frequency (kHz)
Supply Current (mA)
1.6
1.0
0.8
0.6
0.4
0.2
CS1500
70
Max Freq
60
50
40
30
Min Freq
20
Start-up
0
-50
10
Standby
Start-up
Standby
0
50
100
0
150
-60
-40
-20
0
TEMP ( o C)
40
60
80
100
120
140
TEMP ( oC)
Figure 5. Supply Current (ISB, IST, IDD) vs. Temp
Figure 6. Min/Max Operating Frequency vs. Temp
14
425
420
12
OVP
415
10
Vlink (V)
Zout (Ohm)
Source
8
6
VDD = 13 V
Isource = 100 mA
Isink = 200 mA
Sink
4
0
-60
410
405
Normal
400
395
2
390
-40
-20
0
20
40
60
80
100
120
Gate Resistor (ROH, ROL) Temp (oC)
Figure 7. Gate Resistance (ROH, ROL) vs. Temp
6
20
140
385
-50
0
50
100
150
Temperature (°C)
Figure 8. OVP vs. Temp
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Jul ?$shortyear>
CONFIDENTIAL
CS1500
3. INTRODUCTION
NC
CS1500
8
IAC
3
VDD
7
FB
4
NC
1
ADC
Processor
Logic
Oscillator
2
STBY
Protection
5
GND
PWM
Driver
6
GD
Figure 9. CS1500 Block Diagram
The CS1500 digital power factor controller operates in variable
on-time, variable frequency, discontinuous conduction mode
(DCM). The CS1500 uses a proprietary digital algorithm to
maximize the efficiency and reduce the conductive EMI.
proves system stability and transient response. No
external feedback error signal compensation components
are required.
• Overcurrent Mitigation
The analog-to-digital converter (ADC) shown in the CS1500
block diagram in Figure 9 is used to sense the PFC output
voltage ( Vlink ) and the rectified AC line voltage ( Vrect ) by
measuring currents through their respective resistors. The
magnitudes of these currents are measured as a proportion of a
reference current (IREF) that functions as the reference for the
ADCs. The digital signal is then processed in a control algorithm
which determines the behavior of the CS1500 during start-up,
normal operation, and under fault conditions, such as brownout,
overvoltage, overcurrent, overpower, and over-temperature
conditions.
The CS1500s digital controller algorithm limits the ON
time of the Power MOSFET by the following equation:
• DCM with Variable On-Time, Variable Switching Frequency
Where Ton is the max time that the power MOSFET is
turned on and Vrect is the rectified line voltage. In the
event of a sudden line surge or sporadic, high dv/dt line
voltages, this equation may not limit the ON time appropriately. For this type of line disturbance, additional protection mechanisms such as fusible resistors, fast-blow
fuses, or other current-limiting devices are recommended.
The CS1500 PFC switching frequency varies with the
Vrect on a cycle-by-cycle basis, and its digital algorithm
calculates the on-time accordingly for unity power factor.
Unlike traditional Critical Conduction Mode (CRM) PFC
controller, CS1500 operates at its low switching frequency near the zero-crossing point of the AC input voltage,
even no switching at all, and it operates at its high switching frequency at the peak of its AC input voltage (this is
the opposite of the switching frequency profile for a CRM
PFC controller), thus CS1500 reduces switching losses
especially under light-load conditions, spreads conducted
EMI energy peaks over a wide frequency band and increases overall system efficiency.
• Optimized Digital Loop Compensation
The proprietary digital control engine optimizes the feedback error signal using an adaptive control algorithm, im-
DS849A7
0.001126
T on ≤ ------------------------V rect
• Over Voltage Protection
Under steady-state conditions, the voltage loop keeps
PFC output voltage close to its nominal value. Under light
load startup or feedback loop open conditions, the output
voltage may pass the overvoltage protection threshold.
The digital control engine initiates a fast response loop to
shut down gate driving signal to reduce the energy delivered to the output for PFC capacitor protection. When the
link voltage drop below VOVP-VOVP(Hy), PFC resumes
normal operation.
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CONFIDENTIAL
One key feature of the CS1500 is its operating frequency
profile. Figure 10 illustrates how the frequency varies over half
cycle of the line voltage in steady-state operation. When
power is first applied to the CS1500, it first examines the line
voltage and adapts its operating frequency to the exposed line
voltage as shown in Figure 11. The operating frequency is
varied in about a 2-to-1 ratio from the peak to the trough.
During start-up the control algorithm limits the maximum ontime, provides nearly square-wave envelop current within
every half line cycle by adjusting the operating frequency for
fast startup behavior.
120
The CS1500 is designed to function as a DCM (discontinuous
conduction mode) controller, however it may operate in a
quasi-CRM operation mode near the peak periods. For
90~265VAC main input applications, PFC can be also
designed in quasi-CRM at a peak of 90VAC and full load as
shown in Figure 12.
DCM
Quasi CRM
Inductor Current
3.1 PFC Operating Frequency
CS1500
DCM
Quasi CRM
DCM
ILB
IAC
Switching Freq. (% of Max.)
100
% of Max
t [ms]
80
Figure 12. DCM and quasi-CRM Operation with CS1500
60
3.2 Start-up vs. Normal Operation Mode
40
Line Voltage (% of Max.)
20
0
0
45
90
135
180
Rectified Line Voltage Phase (Deg.)
Figure 10. Switching Frequency vs. Phase Angle
CS1500 has two discrete operation modes: Start-up and
Normal. Start-up mode will be activated when Vlink is less than
90% of nominal value and remains active until Vlink reaches
100% of nominal value, as shown in Figure 13. Startup mode
is activated during initial system power-up. Any Vlink drop to
less than 90% of nominal value, such as load change, can
cause the system to enter Start-up Mode until Vlink is brought
back into regulation.
Vlink
[V]
70
Vin < 150 VAC
Vin > 150 VAC
Normal
Mode
Startup Mode
40
90%
Startup Mode
50
46
Burst Mode
FSW max (kHz)
100%
60
56
Normal
Mode
20
t [ms]
Figure 13. Start-up and Normal Modes
0
5
20
40
60
80
100
% PO max
Figure 11. Switching Frequency vs. Output Power
Figure 11 illustrates how the operating frequency (as a
percentage of maximum frequency) changes with output
power and the peak of the line voltage. Burst mode (when Po
below 5%) will be discussed in a later section.
8
3.3 Burst Mode
Burst mode is utilized to improve system efficiency when the
system output power (Po) is < 5% of nominal. Burst mode is
implemented by intermittently disabling the PFC over a full
half-line period cycle under light load conditions, as shown in
Figure 14.
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CONFIDENTIAL
CS1500
Resistor RFB (shown as R2a & R2b in Figure 21) sets the
feedback current and is calculated as follows:
Po
[W]
V link – V dd
R FB = ---------------------------I ref
Burst Threshold
Burst Mode
Active
[Eq.3]
Vlink
t [ms]
Vin
[V]
IFB
PFC
Disable
Vin
RFB
FET
Vgs
VDD
FB
7
4
ADC
t [ms]
Figure 14. Burst Modes
3.4 Output Power and PFC Boost Inductor
Figure 15. Feedback Input Pin Model
Maximum output power in normal mode is defined by the
following equation:
The ADC is used to measure the magnitude of the IFB current
through resistor RFB. The magnitude of the IFB current is then
compared to an internal reference current, Iref.
2 V link – ( V in ( min ) × 2 )
Po = α × η × ( V in ( min ) ) × --------------------------------------------------------2 × f max × L B × V link
[Eq.1]
where, Vin(min), Vlink, and LB are user defined based on
application requirements and maximum operating switching
frequency fmax = 70kHz. α is a margin factor to guarantee
rated power (Po) against tolerances and transients. α is
typically set to 0.9.
The PFC Boost Inductor (LB in Figure 21) value can be
calculated using Equation 1 as follows:
V link – ( V in ( min ) × 2 )
L B = α × η × ( V in ( min ) ) × --------------------------------------------------------2 × f max × Po × V link
2
where Vin(min) is volts RMS, Vlink is volts DC, and
0.9.
By using digital loop compensation, the voltage feedback
signal does not require an external compensation network.
It is recommended that a ceramic capacitor of up to 2.2 nF be
placed between the FB pin and the VDD pin to filter noise in
the layout.
3.7 IAC Signal
Vrect
IAC
RAC
VDD
[Eq.2]
α is set to
IAC
7
3
ADC
3.5 PFC Output Capacitor
The value of the PFC output capacitor should be chosen
based upon voltage ripple and hold-up requirements. This is
described in more detail in the application section 4.1.6 PFC
Output Capacitor on page 13. To ensure system stability with
the digital controller, the recommended value of the capacitor
is within the range of 0.5 μF / watt to 2.0 μF / watt.
3.6 Output Feedback & Regulation
A current proportional to the PFC output voltage, Vlink, is
supplied to the IC on pin FB and is used as a feedback control
signal. This current is compared against a fixed-value internal
reference current, Iref.
DS849A7
Figure 16. IAC Input Pin Model
A current proportional to the AC input voltage is supplied to the
IC on pin IAC and is used by the PFC control algorithm.
Resistor RAC (shown as R1a & R1b in Figure 21) sets the IAC
current and is calculated as follows:
R AC = R FB
[Eq.4]
For optimal performance, resistor RAC, RFB should use less
than 1% tolerance resistor. Resistors can be separated in two
9
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CONFIDENTIAL
The CS1500 has the ability to ensure nearly constant
overpower constraint over a wide range of line voltages, as
shown in Figure 19.
Vlink
[V]
100%
Overpower
t0
Normal Mode
During the brownout state, the device continues monitoring
the input line voltage. The device exits the brownout state
when the input voltage peak value exceeds the brownout
upper threshold for at least 56 ms.
Startup Mode
90%
Normal Mode
Figure 17 illustrates the brownout protection mechanism
whereby the CS1500 enters standby, and upon recovery from
brownout, enters normal operation mode. In order to avoid the
fault trigger, a digital filter is added for line voltage detection.
The measured peak of the line voltage will be clamped to a
threshold (128 V) set by the IC within half of a line cycle if it is
higher than the threshold. It then decreases the voltage with a
slew rate of 5 V / trough (8 ms). The CS1500 initiates a timer
when the measured voltage falls below the lower brownout
threshold. The IC asserts the brownout protection and stops
the gate drive only if the timer reaches more than 56 ms,
which is set by the algorithm based on minimum line
frequency.
Startup Mode
3.8 Brownout Protection
If the PFC remains in startup mode for longer than a given
time, set by the digital controller, it senses an overload
condition and initiates the overpower protection.
Normal Mode
It is recommended that a ceramic capacitor of up to 2.2 nF be
placed between the IAC pin and the VDD pin to filter noise in
the layout.
protection is asserted, the IC stops gate drive, goes into a lowpower state, and restarts every 3 seconds. In the case of an
intermittent or minor fault, the device will continue to regulate the
output voltage (Vlink) to its nominal value.
Startup Mode
or more series elements if voltage breakdown or regulatory
compliance is of concern.
CS1500
Figure 18. Overpower Protection Mechanism
The maximum response time of the brownout protection
normally happens at light load conditions. It can be calculated
by the following equation:
L < LB
[Eq.5]
Po(max)
T Brownout
8 ms
= 8 ms + ------------ ( 128 V – V BP ( th ) ) + 56 ms
5V
8
= 8 + --- ( 128 – 95 ) + 56
5
t [ms]
t0 + tovrpwr
= 116.8 ms
Po / α
L = LB
L = LB / α
Po
In the brownout state, the PFC gate driver will restart every 3
seconds, trying to regulate Vlink to nominal value.
TBrownout
56 ms
90
Brownout
Thresholds
Upper
56 ms
265
V AC(rms )
Figure 19. Maximal Output Power vs. Line Voltage
Lower
3.10
Start
Timer
Enter Standby
Start Timer
Exit Standby
Figure 17. Brownout Sequence
Overvoltage Protection
The overvoltage protection will trigger immediately and stop
the gate drive when the current into the FB pin (IOVP) exceeds
105% of the reference current value (Iref). The IC resumes
gate drive switching when the link voltage drops below
VOVP – VOVP(HY).
3.9 Overpower Protection
3.11 Open/short Loop Protection
During normal operation, if the load is increased beyond the
overpower threshold, the output voltage starts falling. When the
output voltage is below the startup threshold voltage, the CS1500
switches to startup mode and the output voltage will rise back
again to the nominal value and will operate in normal mode if the
load is reduced to a normal level. Otherwise, the PFC oscillates
between startup mode and normal mode and the digital engine
declares the overpower condition. When the overpower
If the PFC output sense resistor RFB fails (open or short to
GND), the measured output voltage decreases at a slew rate
of about 2V / μs, which is determined by ADC sampling rate.
The IC stops the gate drive when the measured output voltage
is lower than the measured line voltage. The IC resumes gate
drive switching when the current into the FB pin becomes
larger than or equal to the current into the IAC pin and Vlink is
10
DS849A7
Jul ?$shortyear>
CONFIDENTIAL
greater than the peak of the line voltage (Vrect(pk)). The
maximum response time of open/short loop protection for RFB
is about 150 μs in the CS1500.
CS1500
shown in Figure 20. Since the pull-up resistor has a high
impedance, the user may need to provide a filter capacitor (up
to 1000 pF) on this pin.
If the PFC input sense resistor RAC fails (open or short to
GND), the current reference signal supplied to the IC on pin
IAC falls to zero. This failure is equivalent to a brownout
condition and will be handled by the brownout protection
mechanism described in Section 3.8.
3.12 Overcurrent Limiting
Boost inductor saturation is a fatal condition for a PFC
converter. To prevent inductor current saturation conditions,
the IC utilizes a proprietary digital algorithm that keeps the
boost inductor current away from its saturation current. The
boost inductor should be designed for full load, minimal line
voltage, maximum switching frequency, and with enough
margin to prevent saturation in normal operation mode.
3.13 Standby (STBY) Function
The standby (STBY) pin provides a means by which an
external signal can cause the CS1500 to enter into a nonoperating, low-power state. The STBY input is intended to be
driven by an open-collector/open-drain device. Internal to the
pin, there is a pull-up resistor connected to the VDD pin as
DS849A7
VDD
600 kΩ
STBY
CS1500
<1 nF
See Text
GND
Figure 20. STBY Pin Connection
When the STBY pin is not used, it is recommended that the pin
be tied to VDD (pulled high).
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CONFIDENTIAL
CS1500
4. APPLICATION EXAMPLE
The following sections describe an example application. The
example is based upon the typical connection diagram
illustrated in Figure 21.
Equations are provided to demonstrate how a user would
calculate the values for the components shown in the diagram.
D1
D2
LB
R AC
R FB
R1a
R2a
R1 b
1
BR1
3
C1
AC
Mains
VDD
7
5
C2
NC
NC
IAC
FB
VDD
STBY
GND
GD
R2b
8
4
C3
Regulated
DC Output
2
6
R3
Q1
CS1500
Figure 21. CS1500 Basic Application Circuit
4.1 PFC for Power Supply Application
The following design example is for a universal main input,
front-end PFC converter with the following parameters:
Vin(min)
90 VAC
Vin(max)
265 VAC
Vlink
400 V
Po
90 W
[Eq.7]
R AC = R FB
R AC = 3.0MΩ
Maximum power dissipation in each sense resistor is
calculated as follows (the equation ignores the voltage drop
across RIAC & RIFB):
2
4.1.1
V link
P ( R FB ) = --------------R FB
IAC and IFB Sensing Inputs
The rectified AC input voltage (Vrect) and boosted PFC output
voltage (Vlink) are sensed as currents into the IC. The sensing
currents are set by resistors RAC and RFB, respectively:
R FB
V link – V dd
= ---------------------------I ref
R FB
400 – 12 = --------------------------–6
129 × 10
[Eq.8]
2
400
P ( R FB ) = ------------------6
3 × 10
P ( R FB ) = 53.3mW
[Eq.6]
2
R FB = 3.0MΩ
[ V in ( max ) ]
P ( R AC )max = ----------------------------R AC
[Eq.9]
2
265
P ( R AC )max = ------------------63 × 10
P ( R AC )max = 23.4mW
12
DS849A7
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CONFIDENTIAL
4.1.2
PFC Input Filter Capacitor
To achieve unity power factor, a DCM PFC circuit needs an
input filtering circuit to bypass the high-frequency current so
that the input current consists of the low-frequency portion
only. There are two main factors on PFC input filter capacitor
selection: its voltage ripple and phase lag, which both will
worsen power factor. The filtering capacitance is proportional
to Po and it is suggested as follows:
nF
C 1 ≥ 3.3 ------- × Po
W
[Eq.10]
C 1 ≥ 3.3 × 120
4.1.4
I FET ( pk ) = I LB ( pk )
[Eq.14]
I FET ( pk ) = 3.3A
4.1.5
PFC Diode
The PFC diode peak current in normal mode is the equal to the
inductor peak current:
I D ( pk ) = I LB ( pk )
Use 0.47 μF for tolerance.
If a PI filter used for suppression of conducted EMI is located
on the DC side of the input rectifier, the Vrect sense point has
to be moved to the second capacitor.
The PFC Diode average current is calculated as follows:
PFC Boost Inductor
2 V link – ( V in ( min ) × 2 )
L B = α × η × ( V in ( min ) ) × --------------------------------------------------------2 × f max × Po × V link
Po
I D ( avg ) = ----------V link
The following equation defines the size of the output capacitor
to meet the output voltage ripple requirements:
Choose a 360 μH inductor.
[Eq.12]
4 × 90
I LB ( pk ) = ----------------------------------------------------0.9 × 0.95 × 90 × 2
η is the efficiency.
The inductor should be designed so that its saturation current
meets the following requirement, where 0.001126 is a predefined threshold for the current protection algorithm:
where L is the inductance in Henrys.
PO
C out ( rip ) = --------------------------------------------------------------------------------------2π × f line ( min ) × V link × ΔV link ( rip )
[Eq.17]
fline(min) is the minimum line frequency the design is required
to support, Vlink is the output voltage from the PFC, ΔVlink(rip),
is the output voltage ripple requirement in volts peak-to-peak.
The equation will provide the value of the output capacitor
needed to meet the ripple requirement.
I LB ( pk ) = 3.3A
0.001126
I sat ≤ ------------------------L
PFC Output Capacitor
The value of the output capacitor is determined by several
requirements. It must meet the voltage ripple and hold-up time
requirements and the RMS current in the capacitor should not
exceed its RMS current rating.
L B = 374μH
4 × Po
I LB ( pk ) = -----------------------------------------------------α × η × V in ( min ) × 2
I D ( avg ) = 0.225A
4.1.6
400 – ( 90 × 2 )
L B = 0.9 × 0.95 × 90 × ------------------------------------------------------------------3
2 × ( 70 × 10 ) × 90 × 400
[Eq.16]
90
I D ( avg ) = ---------400
[Eq.11]
2
[Eq.15]
I D ( pk ) = 3.3A
The value of the inductor in normal mode can be calculated by
the following equation, with α = 0.9 as a derating factor to
ensure the inductor is sized to guarantee DCM operation and
provide a slightly higher power than required by the load:
DS849A7
PFC MOSFET
In normal mode, the PFC MOSFET peak current is equal to
the peak current in the PFC boost inductor:
C 1 ≥ 390nF = 0.39μF
4.1.3
CS1500
[Eq.13]
For 10 V of ripple and minimum line frequency of 45 Hz, the
equation becomes:
90
C out ( rip ) = ------------------------------------------------- = 80μFu use u100μF
2π × 45 × 400 × 10
A second requirement that the output capacitor may be
required to meet is hold-up time. The value of the capacitor
13
Jul ?$shortyear>
CONFIDENTIAL
needed to meet the hold-up time required is defined by the
following equation:
C out ( hold )
2 × P O × t hold
= ----------------------------------------------------------------------------------------ΔV out ( rip ) 2
2
V
------------------------- – ( V link ( min ) )
link –
2
Choose a 100 μF capacitor.
14
Overvoltage Protection
Overvoltage protection is activated when Vlink exceeds 105%
of the nominal value:
[Eq.18]
tHOLD is the magnitude of the hold-up time in seconds. For
10 ms of hold-up time and Vlink(min) of 300 V, the equation
becomes:
2 × 90 × 0.010
C out ( hold ) = -----------------------------------------------------= 27μF
2
2
400 – 10
------ – ( 300 )
2
4.1.7
CS1500
V ovp = V link × 1.05
[Eq.19]
V ovp = 400 × 1.05
V ovp = 420V
While in overvoltage protection mode, gate drive output is
disabled. GD output is re-enabled when Vlink falls below its
nominal value.
DS849A7
Jul ?$shortyear>
CONFIDENTIAL
4.1.8
CS1500
Summary of Component Values
DS849A7
Designator
Value
Description
R1a
1.5 MΩ
SFR25 axial film res - 0.4W-1%
R1b
1.5 MΩ
SFR25 axial film res - 0.4W-1%
R2a
1.5 MΩ
SFR25 axial film res - 0.4W-1%
R2b
1.5 MΩ
SFR25 axial film res - 0.4W-1%
R3
4.7 Ω
SFR25 axial film res - 0.4W-1%
C1
0.47 μF
ECQ2W474KH
C2
0.47 μF
50V Ceramic cap - X7R
C3
100 μF, 450V
LLS2W101MELA
BR1
4A, 600V
GBU4J-BP
D1
1 A, 600 V
1N4005
D2
1 A, 600 V
STTH1R06
LB
360 μH
Premier Magnetics
Q1
12 A, 500 V
STP12NM50FP
CS1500
PFC Controller
CS1500
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Jul ?$shortyear>
CONFIDENTIAL
CS1500
5. PERFORMANCE PLOTS
100
Vin=230V
95
Vin=115V
Efficiency
90
85
80
75
70
0
10
20
30
40
50
60
70
80
90
100
110
Load (%)
Figure 22. Efficiency vs. Load, Typical
100
90
80
THD(%)
70
60
50
40
Vin = 230
30
20
Vin = 115
10
0
0
10
20
30
40
50
60
70
80
90
100
Load (% )
Figure 23. Distortion vs. Load, Typical
16
DS849A7
Jul ?$shortyear>
CONFIDENTIAL
CS1500
1
Vin = 115
Power Factor
0.9
Vin = 230
0.8
0.7
0.6
0.5
0.4
0
10
20
30
40
50
60
70
80
90
100
Load (% )
Figure 24. Power Factor vs. Load, Typical
DS849A7
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Jul ?$shortyear>
CONFIDENTIAL
CS1500
Figure 25. Load Transient — 20% to 80% (60 mA to 240 mA), 0.8 A/μsec Slew, 90 VAC
Figure 26. Load Transient — 20% to 80% (60 mA to 240 mA), 0.8 A/μsec Slew, 260 VAC
18
DS849A7
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CONFIDENTIAL
CS1500
Figure 27. Overload — 240 mA to 500 mA, 90 VAC
Figure 28. Overload — 240 mA to 500 mA, 265 VAC
DS849A7
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CONFIDENTIAL
CS1500
6. DEFINITIONS
Variable
η
The efficiency factor.
α
A margin factor to guarantee rated power against tolerances and transients.
fline(min)
The minimum AC line frequency.
IAC
The current generated by Vrect that flows into the IAC pin.
IFB
The current generated by Vlink that flows into the FB pin.
IFET(pk)
The PFC MOSFET peak current, which is equal to the peak current in the PFC boost inductor.
Irms
The magnitude of the RMS current.
Isat
The boost inductor LB saturation current.
Ist
The sum of the current into the IAC and FB pins.
IST
The startup current of the chip.
LB
The PFC boost inductor.
Po
The nominal output power from the CS1500 PFC circuit.
Po(max)
The maximum value of the output power from the CS1500 PFC circuit.
RAC
The sense resistor used to measure current into the IAC pin.
RFB
The sense resistor used to measure current into the FB pin.
Vin(min)
The minimum specified line voltage for proper operation (volts RMS).
Vlink
The magnitude of the output voltage from the PFC.
Vlink(min)
The magnitude of the output voltage from the PFC.
ΔVlink(rip)
ΔVlink(rip), is the output voltage ripple requirement in volts peak-to-peak
Vrect
20
Definition
The instantaneous value of the rectified line voltage (volts).
DS849A7
Jul ?$shortyear>
CONFIDENTIAL
CS1500
7. PACKAGE DRAWING
8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
∝
A
L
e
A1
INCHES
DIM
A
A1
B
C
D
E
e
H
L
∝
MIN
0.053
0.004
0.013
0.007
0.189
0.150
0.040
0.228
0.016
0°
MAX
0.069
0.010
0.020
0.010
0.197
0.157
0.060
0.244
0.050
8°
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.02
1.52
5.80
6.20
0.40
1.27
0°
8°
JEDEC # MS-012
8. ORDERING INFORMATION
Part #
Temperature Range
Package Description
CS1500-FSZ
-40 °C to +125 °C
8-lead SOIC, Lead (Pb) Free
9. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number
Peak Reflow Temp
MSL Ratinga
Max Floor Lifeb
CS1500-FSZ
260 °C
2
365 Days
a. MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
b. Stored at 30 °C, 60% relative humidity.
DS849A7
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CONFIDENTIAL
CS1500
10.REVISION HISTORY
Revision
Date
Changes
A1
APR 2009
Initial Advance Information release.
A2
JUN 2009
No substantive changes. Document number incremented to avoid
confusion among previous, pre-released versions.
A3
DEC 2009
Revised feature list & product description. Revised electrical characteristics to include brownout & open-loop protection. Modified definition table. Modified data sheet format.
A4
MAR 2010
Updated to correspond to C1 silicon.
A5
MAY 2010
Updated performance data.
A6
MAY 2010
Updated with additional test bench data for EP level.
A7
JUL 2010
Updated zener voltage, OPP threshold, brownout protection/recovery.
Updated Fig.1 with new data.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com
IMPORTANT NOTICE
"Advance" product information describes products that are in development and subject to development changes.
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
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Cirrus Logic, Cirrus, the Cirrus Logic logo designs, EXL CORE, and the EXL CORE logo designs are trademarks of Cirrus Logic, Inc. All other brand and product
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22
DS849A7