TI SN74GTLPH32916

SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
FEATURES
•
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus+™
Family
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, and
Clock-Enabled Modes
TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
GTLP Buffered CLKAB Signal (CLKOUT)
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
•
•
•
•
•
•
•
LVTTL Outputs (–24 mA/24 mA)
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
Bus Hold on A-Port Data Inputs
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The SN74GTLPH32916 is a medium-drive, 34-bit UBT transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of
data transfer. Additionally, it provides for a copy of CLKAB at GTLP signal levels (CLKOUT) and conversion of a
GTLP clock to LVTTL logic levels (CLKIN). The device provides a high-speed interface between cards operating
at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster
than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V),
reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP
OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several
backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with
equivalent load impedance down to 19 Ω.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH32916 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and
VREF = 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
LFBGA – GKF
Tape and reel
ORDERABLE PART NUMBER
SN74GTLPH32916KR
TOP-SIDE MARKING
GM916
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, UBT, TI-OPC, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
GKF PACKAGE
(TOP VIEW)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
2
2
3
4
5
6
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
TERMINAL ASSIGNMENTS
(1)
1
2
3
4
5
6
A
1A2
1A1
1LEAB
1CLKAB
1B1
1B2
B
1A4
1A3
1OEAB
1CEAB
1B3
1B4
C
1A6
1A5
GND
GND
1B5
1B6
D
1A8
1A7
1VCC
1BIAS VCC
1B7
1B8
E
1A10
1A9
GND
GND
1B9
1B10
F
1A12
1A11
GND
GND
1B11
1B12
G
1A14
1A13
1VCC
1VREF
1B13
1B14
H
1A15
1A16
GND
GND
1B16
1B15
J
1A17
1CLKIN
1OEBA
1CLKBA
1CLKOUT
1B17
K
NC
2LEAB
1LEBA
1CEBA
2CLKAB
NC
L
2A2
2A1
2OEAB
2CEAB
2B1
2B2
M
2A4
2A3
GND
GND
2B3
2B4
N
2A6
2A5
2VCC
2BIAS VCC
2B5
2B6
P
2A8
2A7
GND
GND
2B7
2B8
R
2A10
2A9
GND
GND
2B9
2B10
T
2A12
2A11
2VCC
2VREF
2B11
2B12
U
2A14
2A13
GND
GND
2B13
2B14
V
2A15
2A16
2OEBA
2CLKBA
2B16
2B15
W
2A17
2CLKIN
2LEBA
2CEBA
2CLKOUT
2B17
(1)
NC - No internal connection
FUNCTIONAL DESCRIPTION
The SN74GTLPH32916 is a medium-drive (50 mA), 34-bit UBT transceiver containing D-type latches and D-type
flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of
the functions shown in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH32916 UBT Transceiver Replacement Functions
8 BIT
9 BIT
10 BIT
16 BIT
18 BIT
Transceiver
FUNCTION
'245, '623, '645
'863
'861
'16245, '16623
'16863
Buffer/driver
'241, '244, '541
'827
'16241, '16244, '16541
'16825
'16543
'16472
'16373
'16843
'16646, '16652
'16474
Latched transceiver
'543
Latch
'373, '573
Registered transceiver
'646, '652
Flip-flop
'374, '574
'843
'841
'821
'16374
Standard UBT
'16500, '16501
Universal bus driver
'16835
Registered transceiver with clock enable
'2952
Flip-flop with clock enable
'377
'16470, '16952
'823
Standard UBT with clock enable
'16823
'16600, '16601
SN74GTLPH32916 UBT transceiver replaces all above functions
3
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
FUNCTIONAL DESCRIPTION (CONTINUED)
Additionally, it allows for transparent conversion of CLKAB-to-GTLP signal levels (CLKOUT) and
CLKOUT-to-LVTTL logic levels (CLKIN).
Data flow in each direction is controlled by clock enables (CEAB and CEBA), latch enables (LEAB and LEBA),
clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA enable all 17 bits, and
OEAB and OEBA control the 17 bits of data and the CLKOUT/CLKIN buffered clock path for the A-to-B and
B-to-A directions, respectively.
For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data is
latched, regardless of the state of CLKAB (high or low) and if LEAB is high, the device is in transparent mode.
When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to A to B, except CEBA, OEBA, LEBA, and CLKBA are used.
FUNCTION TABLES
xxx
OUTPUT ENABLE (1)
INPUTS
CEAB
OEAB
LEAB
X
H
L
L
L
(1)
(2)
(3)
OUTPUT B
MODE
X
Z
Isolation
X
B0 (2)
X
B0 (3)
CLKAB
A
X
X
L
H
L
L
L
X
L
H
X
L
L
X
L
H
X
H
H
L
L
L
↑
L
L
L
L
L
↑
H
H
H
L
L
X
X
B0 (3)
Latched storage of A data
True transparent
Clocked storage of A data
Clock inhibit
A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and CLKBA.
The condition when OEAB and OEBA are both low at the same time is not recommended.
Output level before the indicated steady-state input conditions were established, provided that
CLKAB was high before LEAB went low
Output level before the indicated steady-state input conditions were established
BUFFERED CLOCK
INPUTS
(1)
4
CE
LE
OEAB
OEBA
OPERATION OR
FUNCTION
MODE
X
X
H
H
Z
Isolation
X
X
L
H
CLKAB to CLKOUT
X
X
H
L
CLKOUT to CLKIN
X
X
L
L
CLKAB to CLKOUT,
CLKOUT to CLKIN
This condition is not recommended.
True delayed clock signal
True delayed clock signal
with feedback path (1)
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
LOGIC DIAGRAM (POSITIVE LOGIC)(1)
1VREF
1OEAB
1CEAB
1CLKAB
1LEAB
1LEBA
1CLKBA
1CEBA
1OEBA
CE
1D
1A1
CE
1D
C1
CLK
1B1
C1
CLK
1 of 17 Channels
1CLKOUT
1CLKIN
(1)
1VCC and 1BIAS VCC are associated with these channels.
5
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
LOGIC DIAGRAM (POSITIVE LOGIC)(1)(CONTINUED)
2VREF
2OEAB
2CEAB
2CLKAB
2LEAB
2LEBA
2CLKBA
2CEBA
2OEBA
CE
1D
2A1
CE
1D
C1
CLK
2B1
C1
CLK
1 of 17 Channels
2CLKOUT
2CLKIN
(1)
6
2VCC and 2BIAS VCC are associated with these channels.
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
VCC
BIAS VCC
Supply voltage range
VI
Input voltage range (2)
VO
Voltage range applied to any output in the
high-impedance or power-off state (2)
IO
Current into any output in the low state
IO
Current into any A-port output in the high state (3)
MIN
MAX
–0.5
4.6
A-port and control inputs
–0.5
7
B port and VREF
–0.5
4.6
A port
–0.5
7
B port
–0.5
4.6
A port
48
B port
100
UNIT
V
V
V
mA
48
mA
±100
mA
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
36
°C/W
150
°C
Continuous current through each VCC or GND
θJA
Package thermal
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
impedance (4)
–65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51-7.
7
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
Recommended Operating Conditions (1) (2) (3) (4)
VCC,
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IIK
Input clamp current
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
Power-up ramp rate
TA
Operating free-air temperature
(1)
(2)
(3)
(4)
8
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
B port
VTT
Except B port
B port
Except B port
VCC
5.5
VREF + 0.05
VREF – 0.05
Except B port
V
V
V
2
B port
V
0.8
V
–18
mA
A port
–24
mA
A port
24
B port
50
Outputs enabled
10
20
–40
mA
ns/V
µs/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is
acceptable, but generally, GND is connected first.
VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is
activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current
drain.
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range for GTLP (unless otherwise noted)
PARAMETER
VIK
VOH
A port
VCC = 3.15 V,
II = –18 mA
VCC = 3.15 V to 3.45 V,
IOH = –100 µA
VCC – 0.2
IOH = –12 mA
2.4
IOH = –24 mA
2
VCC = 3.15 V
VCC = 3.15 V to 3.45 V,
A port
VOL
VCC = 3.15 V
VCC = 3.15 V to 3.45 V,
B port
II
Control inputs
IOZH (2)
IOZL (2)
A port
B port
MIN TYP (1)
TEST CONDITIONS
VCC = 3.15 V
VCC = 3.45 V,
VCC = 3.45 V
MAX
UNIT
–1.2
V
V
IOL = 100 µA
0.2
IOL = 12 mA
0.4
IOL = 24 mA
0.5
IOL = 100 µA
0.2
IOL = 10 mA
0.2
IOL = 40 mA
0.4
IOL = 50 mA
0.55
VI = 0 or 5.5 V
±10
VO = VCC
10
VO = 1.5 V
10
–10
V
µA
µA
A and B ports
VCC = 3.45 V,
VO = GND
(3)
A port
VCC = 3.15 V,
VI = 0.8 V
75
µA
IBHH (4)
A port
VCC = 3.15 V,
VI = 2 V
–75
µA
IBHLO (5)
A port
VCC = 3.45 V,
VI = 0 to VCC
500
µA
(6)
A port
VCC = 3.45 V,
VI = 0 to VCC
–500
IBHL
IBHHO
ICC
A or B port
Cio
Co
(1)
(2)
(3)
(4)
(5)
(6)
(7)
µA
Outputs high
100
Outputs low
100
Outputs disabled
100
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
∆ICC (7)
Ci
VCC = 3.45 V, IO = 0,
VI (A port or control input) = VCC or GND,
VI (B port) = VTT or GND
µA
3
mA
1.5
mA
4
pF
Control inputs
VI = 3.15 V or 0
A port
VO = 3.15 V or 0
6.5
8
B port or CLKOUT
VO = 1.5 V or 0
8.5
10.5
CLKIN
VO = 3.15 V or 0
5
6
pF
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameters IOZH and IOZL include the input leakage current.
The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND
and then raising it to VILmax.
The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC
and then lowering it to VIHmin.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
9
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
Hot-Insertion Specifications for A Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
MIN
VCC = 0,
BIAS VCC = 0,
VI or VO = 0 to 5.5 V
IOZPU
VCC = 0 to 1.5 V,
VO = 0.5 V to 3 V,
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
MAX
UNIT
10
µA
OE = 0
±30
µA
OE = 0
±30
µA
MAX
UNIT
Live-Insertion Specifications for B Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
MIN
VCC = 0,
BIAS VCC = 0,
VI or VO = 0 to 1.5 V
IOZPU
VCC = 0 to 1.5 V,
BIAS VCC = 0,
IOZPD
VCC = 1.5 V to 0,
BIAS VCC = 0,
ICC (BIAS VCC)
VCC = 0 to 3.15 V
VCC = 3.15 V to 3.45 V
10
µA
VO = 0.5 V to 1.5 V, OE = 0
±30
µA
VO = 0.5 V to 1.5 V, OE = 0
±30
µA
5
mA
10
µA
1.05
V
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0 to 1.5 V
VO
VCC = 0,
BIAS VCC = 3.3 V,
IO = 0
0.95
IO
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0.6 V
–1
µA
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted)
MIN
fclock
tw
tsu
th
10
Clock frequency
Pulse duration
Setup time
Hold time
CLKAB to B or CLKBA to A
LEAB or LEBA high
CLKAB to B or CLKBA to A
2.8
High or low
2.8
A before CLKAB↑
1.8
B before CLKBA↑
1.5
A before LEAB↓
1
B before LEBA↓
2
CEAB before CLKAB↑
1.5
CEBA before CLKBA↑
1.5
A after CLKAB↑
0.3
B after CLKBA↑
0.4
A after LEAB↓
1.1
B after LEBA↓
0.5
CEAB after CLKAB↑
1
CEBA after CLKBA↑
1
MAX
UNIT
175
MHz
ns
ns
ns
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
CLKAB or CLKBA
B or A
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
B
LEAB
B
CLKAB
B
CLKAB
CLKOUT
OEAB
B or CLKOUT
tr
Rise time, B outputs (20% to 80%)
tf
Fall time, B outputs (80% to 20%)
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
(1)
A
MIN TYP (1)
MAX
175
MHz
2.1
6
2.1
6
2.2
6.5
2.2
6.5
2.2
6.5
2.2
6.5
3.2
8
3.2
8
2.2
6.5
2.2
6.5
2.4
A
LEBA
A
CLKBA
A
CLKOUT
CLKIN
OEBA
A or CLKIN
ns
ns
ns
ns
ns
ns
2
B
UNIT
ns
1.8
5.8
1.8
5.8
1.5
5.3
1.5
5.3
1.8
5.7
1.8
5.7
2.5
6.5
2.5
6.5
1
6.2
1
5.9
ns
ns
ns
ns
ns
All typical values are at VCC = 3.3 V, TA = 25°C.
11
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
1.5 V
6V
Open
S1
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 50 pF
(see Note A)
500 Ω
25 Ω
S1
Open
6V
GND
From Output
Under Test
Test
Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
tw
3V
3V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
tsu
th
VOH
Data
Input
VM
VM
0V
3V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(VM = 1.5 V for A port and 1 V for B port)
(VOH = 3 V for A port and 1.5 V for B port)
VOH
Output
1V
1V
3V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
1V
1V
0V
tPLH
1.5 V
tPLZ
3V
1.5 V
VOL + 0.3 V
VOL
tPZH
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
VOH
Output
1.5 V
tPZL
1.5 V
Input
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
tPHZ
VOH
1.5 V
VOH − 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
12
SN74GTLPH32916
34-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCES380A – JANUARY 2002 – REVISED JUNE 2005
Distributed-Load Backplane Switching Characteristics
The preceding switching characteristics table shows the switching characteristics of the device into a lumped
load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical
representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a
resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum
performance in this RLC circuit. The following switching characteristics table shows the switching characteristics
of the device into the RLC load, to help the designer better understand the performance of the GTLP device in
this typical backplane. See www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
.25”
2”
Conn.
Conn.
1”
1”
Conn.
1”
2”
38 Ω
38 Ω
1.5 V
ZO = 70 Ω
.25”
19 Ω
From Output
Under Test
Conn.
LL = 19 nH
Test
Point
CL = 9 pF
1”
Rcvr
Rcvr
Rcvr
Slot 2
Slot 9
Slot 10
Drvr
Slot 1
Figure 3. Medium-Drive RLC Network
Figure 2. Medium-Drive Test Backplane
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP
(see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
LEAB
B
CLKAB
B
CLKAB
CLKOUT
OEAB
B or CLKOUT
TYP (1)
4.5
4.5
4.7
4.7
4.7
4.7
6
6
4.8
4.4
UNIT
ns
ns
ns
ns
ns
tr
Rise time, B outputs (20% to 80%)
1.2
ns
tf
Fall time, B outputs (80% to 20%)
2.5
ns
All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
13
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
PACKAGING INFORMATION
Orderable Device
SN74GTLPH32916ZKFR
Status
(1)
ACTIVE
Package Type Package
Drawing
LFBGA
ZKF
Pins
Package Qty
114
1000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
SNAGCU
MSL Peak Temp
(3)
Samples
(Requires Login)
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74GTLPH32916ZKFR
Package Package Pins
Type Drawing
LFBGA
ZKF
114
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
5.8
B0
(mm)
K0
(mm)
P1
(mm)
16.3
1.8
8.0
W
Pin1
(mm) Quadrant
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74GTLPH32916ZKFR
LFBGA
ZKF
114
1000
333.2
345.9
31.8
Pack Materials-Page 2
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