TI SLVS164

TPS9110
CELLULAR SUBSCRIBER TERMINAL
POWER SUPPLY
SLVS164 – AUGUST 1997
D
D
D
D
D
D
D
D
PW PACKAGE
(TOP VIEW)
Complete Power Supply for Cellular
Handsets
Three Low-Dropout Regulators (LDOs) with
100-mV Dropout
Less Than 1 µA Supply Current in
Shutdown Typ
250-ms Microprocessor Reset Output
10-mA Charge-Pump Driver Configurable
For Inverted or Doubled Output
Separate Enables for LDOs and Charge
Pump
1.185-V Reference
28-Pin TSSOP Package
RESET
VCP
GND_CP
CP
EN_CP
GND
EN
ON
VA
CA
PA
GND
EN_A
VCC
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VCC
PL
GND
ON
CL
VL
REF
OFF
VB
CB
ON_REM
GND
EN_B
PB
description
The TPS9110 incorporates a complete power supply system for a cellular subscriber terminal that uses battery
packs with three or four NiMH/NiCd cells or a single lithium-ion cell. The device includes three low-dropout linear
regulators rated for 3.3 V or 3 V at 100 mA each, a charge-pump driver, and logic that includes a 250-ms reset,
on/off control, and processor interface. Regulators A and B and the charge-pump driver have separate enables
allowing circuitry to be powered up or down as necessary to conserve battery power. Regulators VL, VA, and
VB, and the charge pump driver are active as soon as UVLO and OTP are valid and ON is toggled low.
The TPS9110 operates over a free-air temperature range of – 40°C to 85°C and is supplied in a 28-pin TSSOP
package.
AVAILABLE OPTIONS
TA
– 40°C to 85°C
PACKAGED DEVICE
TSSOP (PW)
CHIP FORM
(Y)
TPS9110IPWLE
TPS9110Y
The PW package is only available left-end taped and reeled.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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TPS9110
CELLULAR SUBSCRIBER TERMINAL
POWER SUPPLY
SLVS164 – AUGUST 1997
functional block diagram
VCP
ChargePump
Driver
2
VCC
CP
GND_CP
EN_CP
EN
Voltage
Reference
REF
UVLO†
and
OTP‡
LDO
Regulator
B
LDO
Regulator
A
EN_A
LDO
Regulator
L
EN_B
GND
4
VB
1Ω
CB
PB
VA
1Ω
CA
PA
VL
1Ω
CL
PL
Reset
Generator
RESET
OFF
ON
ON
ON_REM
† UVLO - Undervoltage lockout
‡ OTP - Overtemperature protection
2
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TPS9110
CELLULAR SUBSCRIBER TERMINAL
POWER SUPPLY
SLVS164 – AUGUST 1997
TPS9110Y chip information
These chips, when properly assembled, display characteristics similar to those of the TPS9110. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
23
24
25
22
21
20
19
18
26
17
27
16
28
15
CHIP THICKNESS:
15 TYPICAL
BONDING PADS:
3.3 × 3.3 MINIMUM
TJ max = 150°C
94
14
TOLERANCES ARE ± 10%.
ALL DIMENSIONS
ARE IN MILS.
1
2
13
3
12
4
5
6
8
7
9
10
11
153
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TPS9110
CELLULAR SUBSCRIBER TERMINAL
POWER SUPPLY
SLVS164 – AUGUST 1997
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
CA
10
EN_A
13
I
Regulator A enable input. A logic low on EN_A turns on regulator A.
PA
11
I
Program A. PA provides programming input for regulator A.
VA
9
O
Regulator A output voltage
CB
19
EN_B
16
PB
VB
CL
24
PL
27
I
Program L. PL provides voltage programming input for regulator L.
VL
23
O
Regulator L output voltage
GND
Regulator A filter capacitor connection
Regulator B filter capacitor connection
I
Regulator B enable input. A logic low on EN_B turns on regulator B.
15
I
Program B. PB provides programming input for regulator B.
20
O
Regulator B output voltage
Regulator L filter capacitor connection
6, 12,
17, 26
REF
22
VCC
14, 28
Ground. GND terminals should be externally connected to ground to ensure proper functionality.
O
1.185-V reference output. Decouple REF with an external 0.01-µF to 0.1-µF capacitor to ground.
Supply voltage input. VCC terminals are not connected internally and must be externally connected to ensure
proper functionality.
CP
4
O
Charge pump driver output
EN_CP
5
I
Charge pump driver enable input. Logic low on EN_CP turns on the charge pump.
GND_CP
3
Charge pump driver ground
VCP
2
Charge pump driver supply voltage
EN
7
I/O
OFF
21
I
Off-signal input. A logic low on OFF turns off the TPS9110.
ON
8
O
On-signal output. ON is the logical inversion of ON.
ON
25
I
On signal. A logic low on ON enables the TPS9110.
ON_REM
18
I
Remote on. A logic high on ON_REM enables the TPS9110.
RESET
1
O
Microprocessor reset output. RESET is a logic low for 250 ms at power-up.
4
Enable signal input/output. A logic low on EN enables the TPS9110.
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TPS9110
CELLULAR SUBSCRIBER TERMINAL
POWER SUPPLY
SLVS164 – AUGUST 1997
detailed description
voltage reference
The regulators and reset generator utilize an internal 1.185-V band-gap voltage reference. The reference is also
buffered and brought out on REF for external use; REF can source a maximum of 2 mA. A 0.01-µF to 0.1-µF
capacitor must be connected between REF and ground.
LDO regulators
The TPS9110 includes three low-dropout regulators, implemented with 1-Ω PMOS series-pass transistors, with
quiescent supply currents of 100 µA. Each of the regulators can supply up to 100 mA of continuous output
current. The 1-Ω PMOS series-pass transistor achieves the dropout voltage of 100 mV at the maximum-rated
output current. Each regulator output voltage can be independently programmed to either 3.3 V or 3 V using
its programming control input PL, PA or PB (Px). A logic low on Px sets the output voltage of the regulator to
3.3 V; a logic high sets it to 3 V.
Each LDO contains a current limit circuit. When the current demand on the regulator exceeds the current limit,
the output voltage drops in proportion to the excess current. When the excess load current is removed, the
output voltage returns to regulation. Exceeding the current limit on VL can disable the TPS9110. If enough
current demand is placed on VL, the output voltage drops below the reset threshold voltage causing RESET
to go low, effectively unlatching the enable.
VL is intended to be the primary supply voltage for the microprocessor and other system logic functions. VA and
VB can power low-noise analog circuits and/or implement system power management. The enable terminals
EN_A and EN_B are utilized to power down circuitry when it is not required. EN_A and EN_B are
TTL-compatible inputs with 10-µA active current-source pullups. A logic low enables the respective regulator
while a logic high pulls the regulator output voltage to ground and reduces the regulator quiescent current to
leakage levels.
Stability of the LDOs is ensured by the addition of compensation terminals CL, CA, and CB, which connect to
the output of the regulator through an internal 1-Ω resistor. This compensation scheme allows for capacitors
with equivalent series resistance (ESR) of up to 15 Ω, eliminating the need for expensive, low-ESR capacitors.
reset generator
RESET is a microprocessor reset signal that goes to logic low at power-up, or whenever VL drops below 2.93 V
(2.6 V for 3-V applications), and remains in that state for 250 ms after VL exceeds the RESET threshold (see
Figure 5). The open-drain output has a 30-µA pullup that eliminates the need for an external pullup resistor and
still allows it to be connected with other open-drain or open-collector signals. RESET is valid for supply voltages
as low as 1.5 V.
ON, OFF, ON, ON_REM and EN functions
The ON input is intended to be the main enable for the TPS9110 and should be connected to ground through
a pushbutton switch. Once the switch is pressed, internal logic pulls EN low. EN is designed to sink 3.2 mA and
can be used as a pulldown to enable other functions on the TPS9110 or other system circuitry. When EN is pulled
low, the TPS9110 checks to make sure the supply voltage is above the undervoltage lockout (UVLO) threshold
voltage and the die temperature is below 160°C. If both of these conditions are met, the reference circuitry,
regulator L, reset generator, and other support circuitry are enabled. When RESET goes high, the system can
respond with a logic high on OFF, which latches the TPS9110 on, and the ON pushbutton can then be released.
The TPS9110 is disabled in a similar manner. If the ON pushbutton is pressed while the TPS9110 is enabled,
ON responds with a logic high. Once this logic high is detected, the system can respond with a logic low on OFF,
disabling the TPS9110 and reducing supply currents to 1 µA (see Figure 1).
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POWER SUPPLY
SLVS164 – AUGUST 1997
ON, OFF, ON, ON_REM and EN functions (continued)
ON_REM can be used in the same manner as ON in enabling or disabling the TPS9110. The signal is provided
as a system interface to increase the flexibility of the system. EN can also be used as an input wired-OR open
collector/drain to enable the TPS9110; however, it does not produce a logic signal on ON and, therefore, cannot
be used in the disable sequence described above. It is not recommended that EN be used as the primary enable
signal for the TPS9110.
Enable Sequence
ON
Disable Sequence
ON must be held low until system
responds with a high at OFF.
ON is pressed to turn off
the system (phone).
ON
EN
VL, VA, VB
Once EN goes low, the status of the
UVLO and the OTP are checked.
If the UVLO and OTP are valid, VL, VA,
VB, CP, and other functions are
enabled.
250 ms
RESET
250 ms after VL rises above the reset
threshold voltage, RESET goes high.
OFF
The system can now
respond with a high at OFF.
Once OFF and RESET are high,
the enable is latched on.
System detects the high
signal at ON and responds
with a low signal at OFF.
Figure 1. Recommended Enable and Disable Sequence
undervoltage lockout (UVLO)
UVLO prevents operation of the functions in the TPS9110 until the supply voltage exceeds the threshold voltage,
eliminating abnormal power-up conditions internally and externally, and providing an orderly turn-on.
overtemperature shutdown
When the die temperature exceeds 160°C, the thermal protection circuit shuts off the TPS9110. When the die
temperature drops below 150°C, the device can be restarted with the ON input.
charge pump driver
An unregulated inverting or doubler charge pump is implemented by connecting a network of two capacitors
and two diodes to CP (see Figure 26). In the inverting configuration, the charge pump can power a liquid-crystal
display (LCD) or provide gate bias for a GaAs power amplifier. A 5-V supply for flash-memory programming or
powering the subscriber identity module (SIM) European applications can be achieved using the doubler
configuration and an external LDO. A logic-low input to the charge-pump enable, EN_CP, turns on the oscillator
and driver; a logic high turns them off. The charge pump driver can be turned on as soon as UVLO and OTP
are valid and ON is toggled low. EN_CP has an 10-µA internal pullup.
6
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TPS9110
CELLULAR SUBSCRIBER TERMINAL
POWER SUPPLY
SLVS164 – AUGUST 1997
DISSIPATION RATING TABLE 1 – Free-Air Temperature
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PW
700 mW
5.6 mW/°C
448 mW
364 mW
PACKAGE
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
PW
4025 mW
32.2 mW/°C
DISSIPATION RATING TABLE 2 – Case Temperature
TC = 70°C
POWER RATING
2576 mW
800
600
RθJA = 178°C/W
400
200
0
25
50
75
100
125
150
2093 mW
MAXIMUM CONTINUOUS POWER DISSIPATION
vs
CASE TEMPERATURE
PD – Maximum Continuous Power Dissipation – mW
PD – Maximum Continuous Power Dissipation – mW
MAXIMUM CONTINUOUS POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1000
TC= 85°C
POWER RATING
5000
4000
3000
RθJC = 57°C/W
2000
1000
0
25
TA – Free-Air Temperature – °C
50
75
100
125
150
TC – Case Temperature – °C
Figure 3
Figure 2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†‡
Supply voltage range, VCC, VCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 12 V
Input voltage range at OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range at PL, PA, PB, EN, EN_A, EN_B, ON, ON_REM, EN_CP . . . . . . . . . . . . . – 0.3 V to VCC
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are with respect to GND.
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POWER SUPPLY
SLVS164 – AUGUST 1997
recommended operating conditions
MIN
MAX
Supply voltage, VCC, VCP
3
10
V
Input voltage, OFF
0
5
V
Input voltage at PL, PA, PB, EN, EN_A, EN_B, ON, ON_REM, EN_CP
0
V
Reference output current
0
VCC
2
mA
Continuous regulator output current
0
100
mA
– 40
85
°C
Operating free-air temperature
UNIT
electrical characteristics over recommended operating free-air temperature range,
VCC = VCP = 4 V, Px = 0 V, IO(Vx) = 35 mA, OFF = VL, ON open, ON_REM = 0 V, Cx = 10 µF (unless
otherwise noted)
voltage reference (REF)
TEST CONDITIONS†
PARAMETER
TA = 25°C,
4 V ≤ VCC ≤ 10 V,
Output voltage
IO = 0
0 ≤ IO≤ 2 mA
MIN
TYP
MAX
1.185
1.161
UNIT
V
1.209
V
† Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effect must be
taken into account separately.
LDO regulators
TEST CONDITIONS†
PARAMETER
TA = 25°C
0 ≤ IO(Vx) ≤ 100 mA,
Output voltage at VA, VB, VL (Vx)
Px = VCC,
Px = VCC,
3.2 V ≤ VCC ≤ 10 V
Dropout voltage
3.5 V ≤ VCC ≤ 10 V
TA = 25°C
0 ≤ IO(Vx) ≤ 100 mA,
MIN
TYP
MAX
UNIT
3.25
3.3
3.35
V
3.4
V
3
3.05
V
3.10
V
200
mV
3.2
2.95
2.9
IO(Vx) = 100 mA,
VCC = 3.2 V
IO(Vx) = 0 mA to 100 mA
Load regulation
Line regulation
IO(Vx) = 100 mA,
f = 120 Hz
Ripple rejection
100
VCC = 3.5 V to 10 V
Quiescent current (each regulator)
30
mV
10
mV
60
dB
100
µA
† Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effect must be
taken into account separately.
charge pump driver
PARAMETER
Frequency
Duty cycle
TYP
MAX
UNIT
50
100
150
kHz
30
Ω
50%
Output resistance
8
MIN
15
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RESET
TEST CONDITIONS†
PARAMETER
MIN
TYP
MAX
UNIT
2.871
2.93
2.989
V
2.548
2.6
2.652
125
250
375
Input threshold voltage
VL voltage decreasing
Input threshold voltage
VL voltage decreasing,
Timeout delay at RESET
See Figure 5
High-level output voltage
IO = – 40 µA
IO = 1 mA,
2.4
Low level output voltage
Low-level
PL = VCC
V
VCC = 1.5 V
0.4
IO = 3.2 mA
0.4
Hysteresis
V
ms
40
V
mV
† Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effect must be
taken into account separately.
logic inputs at EN_A, EN_B
PARAMETER
MIN
High-level input voltage
TYP
MAX
2
V
Low-level input voltage
Input current
– 20
UNIT
0.8
V
– 10
1
µA
MIN
MAX
logic inputs at PL, PA, PB, OFF, ON_REM
PARAMETER
High-level input voltage
2
Low-level input voltage
Input current
UNIT
V
0.8
V
–1
1
µA
MIN
MAX
logic inputs at ON‡
PARAMETER
High-level input voltage
2
Low-level input voltage
Input current
UNIT
V
0.8
V
– 20
1
µA
MIN
MAX
‡ High and low level voltages are dependent on VCC (see Figure 17).
logic inputs at EN‡
PARAMETER
TEST CONDITIONS
High-level input voltage
2.4
Low-level input voltage
V
0.8
IO = –50 µA
IO = 3.2 mA,
High-level output voltage
Low-level output voltage
OFF = 0
2.4
ON = 0
UNIT
V
V
0.4
V
‡ High and low-level input voltages are dependent on VCC (see Figure 18).
logic outputs at ON
PARAMETER
TEST CONDITIONS
High-level output voltage
1-mA source current
Low-level output voltage
1-mA sink current
MIN
MAX
2.4
UNIT
V
0.4
V
overtemperature shutdown
PARAMETER
MIN
TYP
MAX
UNIT
Temperature threshold
160
°C
Temperature hysteresis
10
°C
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undervoltage lockout (UVLO)
PARAMETER
TEST CONDITIONS
Threshold voltage
VCC increasing
MIN
TYP
1.80
Hysteresis
MAX
2.52
50
UNIT
V
mV
supply current
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shutdown
OFF = 0 V
0.5
10
µA
Operating
EN_CP = VCP
0.7
1
mA
TPS9110Y electrical characteristics, TJ = 25°C, VCC = VCP = 4 V, Px = 0 V, IO(Vx) = 35 mA, OFF = VL,
ON open, ON_REM = 0 V, Cx = 10 µF (unless otherwise noted)
voltage reference (REF)
TEST CONDITIONS†
PARAMETER
MIN
TYP
MAX
UNIT
Output voltage
IO = 0
1.185
V
† Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; the thermal effect must
be taken into account separately.
LDO regulators
TEST CONDITIONS†
PARAMETER
Output voltage at VA, VB, VL (Vx)
Px = VCC
IO(Vx) = 100 mA,
Dropout voltage
MIN
2.95
VCC = 3.2 V
IO(Vx) = 0 mA to 100 mA
Load regulation
Line regulation
IO(Vx) = 100 mA,
f = 120 Hz
Ripple rejection
VCC = 3.5 V to 10 V
Quiescent current (each regulator)
TYP
MAX
3
3.05
UNIT
V
100
mV
30
mV
10
mV
60
dB
100
µA
† Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effect must be
taken into account separately.
charge-pump driver
PARAMETER
MIN
TYP
Frequency
100
Duty cycle
50%
Output resistance
MAX
UNIT
kHz
Ω
15
RESET
TEST CONDITIONS†
PARAMETER
Threshold voltage
Delay
VL voltage decreasing
VL voltage decreasing,
See Figure 5
Hysteresis
MIN
TYP
2.93
PL = VCC
2.6
MAX
UNIT
V
250
ms
40
mV
† Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effect must be
taken into account separately.
10
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PARAMETER MEASUREMENT INFORMATION
VCP
VCC
14
22
REF
0.1 µF
28
2
4
Voltage
Reference
Charge-Pump
Driver
3
20
REF
19
Regulator
B
+
5
15
9
16
10
Regulator
A
13
VL
ON
ON_REM
1
21
25
8
18
6
12
17
10 µF
+
27
Reset
Generator
7
11
+
23
24
Regulator
L
EN
10 µF
10 µF
RESET
OFF
ON
26
Figure 4. Test Circuit
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PARAMETER MEASUREMENT INFORMATION
VL
VIT+
t
RESET
RESET
Timeout Delay
t
5
4
VCC = 4 V
Px = 0 V
TA = 25°C
IO = 0 mA
Cx = 10 µF
3
Enable
2
1
0
4
3
2
VO
1
0
0
4
8
12
16
VO – Output Voltage – V
Enable Input Voltage – V
Figure 5. RESET Timing Diagram
20
t – Time – ms
Figure 6. LDO-Regulator Output-Voltage Rise Time and Fall Time
12
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125
VCC = 4 V
Px = 0 V
TA = 25°C
Cx = 10 µF
100
75
50
25
0
3.5
3.4
3.3
3.2
3.1
0
0.5
1
1.5
VO – Output Voltage – V
I O – LDO Regulator
Output Current – mA
PARAMETER MEASUREMENT INFORMATION
2
t – Time – ms
4.4
4.2
4
3.8
3.6
3.4
3.3
Px = 0 V
TA = 25°C
IO = 10 mA
Cx = 10 µF
0
0.3
0.8
0.5
3.2
VO – Output Voltage – V
VCC – Supply Voltage – V
Figure 7. LDO-Regulator Load Transient, 1 mA to 100 mA Pulsed Load
3.1
1
t – Time – ms
Figure 8. LDO-Regulator Line Transient
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
ICC
Quiescent current
Dropout voltage
vs Supply voltage
9
vs Output current
10
vs Junction temperature
11
∆VO
VO
Change in output voltage
vs Junction temperature
12
Output voltage, VL
vs Supply voltage
13
∆VO
∆VO
Change in output voltage
vs Supply voltage
14
Change in output voltage
vs Output current
15
ICC
Shutdown current
vs Supply voltage
16
Input threshold voltage, ON
vs Supply voltage
17
Input threshold voltage, EN
vs Supply voltage
18
Input threshold voltage, ON_REM
vs Supply voltage
19
Ripple rejection
vs Frequency
20
Output spectral noise density
vs Frequency
21
Change in frequency, CP
vs Junction temperature
22
rO
Output resistance into CP
vs Supply voltage
23
rO
Output resistance out of CP
vs Supply voltage
24
LDO REGULATORS
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
160
1
TA = 25°C
140
0.9
120
Dropout Voltage – mV
I CC – Quiescent Current – mA
Px = 0
IO = 0
0.8
85°C
0.7
–40°C
25°C
100
Px = VCC
80
60
Px = 0
40
0.6
20
0.5
3
4
7
8
5
6
VCC – Supply Voltage – V
9
10
0
0
10
Figure 9
14
20
30 40 50 60 70 80
IO – Output Current – mA
Figure 10
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TYPICAL CHARACTERISTICS
LDO REGULATORS
LDO REGULATORS
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
CHANGE IN OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
10
140
IO = 100 mA
Px = 0
Dropout Voltage – mV
120
110
100
90
80
70
60
–50
–25
0
VCC = 4 V
Px = 0
8
∆VO – Change in Output Voltage – mV
130
25
50
75
100
6
IO = 0 mA
4
2
0
–2
–4
IO = 100 mA
–6
–8
–10
–50
125
–25
25
50
75
100
125
TJ – Temperature – °C
TJ – Temperature – °C
Figure 11
Figure 12
REGULATOR L
LDO REGULATORS
OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
CHANGE IN OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
4
3.5
∆VO – Change in Output Voltage – mV
Px = 0
TA = 25°C
EN = 0
3
VO – Output Voltage, VL – V
0
2.5
2
1.5
1
0.5
Px = 0 or
Px = VCC
TA = 25°C
IO = 35 mA
3
2
1
0
–1
–2
–3
–4
0
2
2.2
2.4 2.6 2.8
3
3.2 3.4 3.6
3.8
4
3
VCC – Supply Voltage – V
Figure 13
4
5
6
7
8
VCC – Supply Voltage – V
9
10
Figure 14
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TYPICAL CHARACTERISTICS
LDO REGULATORS
SHUTDOWN CURRENT
vs
SUPPLY VOLTAGE
CHANGE IN OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4
VCC = 4 V
Px = 0 or Px = VCC
TA = 25°C
15
OFF = 0
3.5
I CC – Shutdown Current – µ A
∆VO – Change in Output Voltage – mV
20
10
5
0
–5
–10
3
2.5
2
1.5
1
–15
0.5
–20
0
0
10
20
30
40
50
60
70
80
90 100
TA = 40°C
2
3
IO – Output Current – mA
5
6
7
8
9
10
Figure 16
INPUT THRESHOLD VOLTAGE, EN
vs
SUPPLY VOLTAGE
INPUT THRESHOLD VOLTAGE, ON
vs
SUPPLY VOLTAGE
4.9
1.8
OFF = 0 V
EN = Open
ON_REM = 0 V
–40°C
V IT – Input Threshold Voltage, EN – V
V IT – Input Threshold Voltage, ON – V
4
VCC – Supply Voltage – V
Figure 15
1.6
25°C
1.4
85°C
1.2
1
OFF = 0 V
ON = Open
ON_REM = 0 V
4.4
3.9
3.4
2.9
2.4
1.9
1.4
0.8
2
8
4
6
VCC – Supply Voltage – V
10
2
3
4
5
6
Figure 18
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8
VCC – Supply Voltage – V
Figure 17
16
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TA = 85°C
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TYPICAL CHARACTERISTICS
LDO REGULATORS
INPUT THRESHOLD VOLTAGE, ON_REM
vs
SUPPLY VOLTAGE
RIPPLE REJECTION
vs
FREQUENCY
80
EN = Open
ON = Open
OFF = 0 V
3.5
Ripple Rejection – dB
V IT – Input Threshold Voltage, ON_REM – V
4
3
2.5
2
60
40
VCC = 4 V
TA = 25°C
Cx = 10 µF
IO = 35 mA
1.5
1
2
3
4
5
6
7
8
9
20
0.01
10
0.1
1
VCC – Supply Voltage – V
10
100
1000
f – Frequency – kHz
Figure 19
Figure 20
REGULATOR L
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
CHANGE IN FREQUENCY, CP
vs
JUNCTION TEMPERATURE
4
VCC = 4 V
Px = 0 V
TA = 25°C
IO = 35 mA
VCP = 4 V
∆f – Change in Frequency, CP – kHz
Output Spectral Noise Density – µV / Hz
100
10
1
1
10
100
1000
10000
3
2
1
0
–1
–2
–3
–50
–25
f – Frequency – Hz
0
25
50
75
100
125
TJ – Temperature – °C
Figure 21
Figure 22
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TYPICAL CHARACTERISTICS
OUTPUT RESISTANCE, CP
vs
SUPPLY VOLTAGE
OUTPUT RESISTANCE, CP
vs
SUPPLY VOLTAGE
30
30
Current Out of CP
Current Into CP
25
ro – Output Resistance, CP – Ω
ro – Output Resistance, CP – Ω
25
20
85°C
15
25°C
10
–40°C
20
15
85°C
10
25°C
5
5
–40°C
0
0
3
4
5
6
7
8
9
VCC(VCP) – Supply Voltage – V
3
10
4
8
9
5
6
7
VCC(VCP) – Supply Voltage – V
Figure 23
10
Figure 24
THERMAL INFORMATION
Using thermal resistance, junction-to-ambient (RθJA), maximum power dissipation can be calculated with the
equation:
T
T
J(max)
A
P
D(max)
R
qJA
*
+
Where TJ(max) is the maximum allowable junction temperature or 150°C.
This limit should then be applied to the internal power dissipation of the TPS9110. The equation for calculating
total internal power dissipation of the TPS9110 is:
P
D(max)
+
ȍǒ
V
x
I
Ǔ
* VX
I
X
) VI
I
Q
Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces,
and the presence of other heat-generating components affect the power dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are:
•
•
•
18
Improving the power dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in the system
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APPLICATION INFORMATION
BATTERY
1 µF
Voltage
Reference
REF
0.1 µF
Charge Pump
4.7 µF
RF
Section
REF
Regulator
B
3.3 V
Regulator
A
3.3 V
Regulator
L
3.3 V
7–13 µF
Analog
Section
7–13 µF
7–13 µF
Reset
Generator
RESET
OFF
EN
Processor
and
Logic
Section
ON
ON
ON_REM
GND
Figure 25. Typical Application
LDOs (VL, VA, VB) output capacitors
A 10-µF capacitor must be tied to Cx (CL, CA, or CB). The Cx terminal is connected internally to the output of
the LDO through a 1-Ω resistor. The stability of LDOs is dependent on the ESR of the output filter capacitor. Most
LDOs are designed to be stable over a narrow range of ESR with lower limits and upper limits, thus limiting the
type of capacitor that can be used. With the use of the internal 1-Ω resistor, the lower ESR limit of the capacitor
is eliminated, permitting the upper limit to be raised. Therefore, almost any tantalum or ceramic capacitor can
be used, provided the ESR does not exceed 15 Ω over operating temperature range.
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charge pump design
VCC
VCC
VCP
VCP
C1
C1
VO
CP
VO
CP
+
C2
C2
+
GND_CP
GND_CP
a. Voltage Inverter
b. Voltage Doubler
Figure 26. Charge-Pump Configurations
The charge-pump terminal can drive either a voltage inverter or a voltage doubler. In either case only two
capacitors and two signal diodes are needed. The output voltage is unregulated and a regulator may be added
if needed.
The charge transfer of C1 is:
Dq + C1
* VO)
(VCC
This occurs f times a second and the charge transfer per unit time (current) is:
I
+f
C1
(VCC
* VO)
Rewriting this equation in the form of I = V/R gives:
I
where
+
1
f
C1
V
CC
* VO
1
f C1
is an equivalent resistor.
An equivalent circuit can now be drawn taking the diodes into account.
Rinternal
Requiv
Rinternal
– (VCC – Vdiode)
Requiv
2VCC – Vdiode
+
C2
+
a. Voltage Inverter
b. Voltage Doubler
Figure 27. Equivalent Circuit for Charge Pump
20
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charge-pump design (continued)
The output voltage for the doubler is then:
VO
+2
VCC
*2
Vdiode
* IO
Rtotal
and the output voltage for the inverter is:
VO
+ * (VCC * 2
Vdiode)
) IO
Rtotal
To determine the size of C1 use:
C
+f
I
DV
where f = 100,000 and ∆V = ripple voltage.
For an output current of 10 mA calculate:
C1
+ 100 kHz0.010.1A Vripple + 1mF
Because of losses caused by diode switching and ESR, the calculated capacitance should be multiplied
by 1.5 to 2. A 2-µF capacitance should drive a 10-mA voltage doubler or inverter.
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MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,32
0,19
0,65
14
0,13 M
8
0,15 NOM
4,50
4,30
6,70
6,10
Gage Plane
0,25
1
7
0°– 8°
0,75
0,50
A
Seating Plane
1,20 MAX
0,10
0,10 MIN
PINS **
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064 / D 10/95
NOTES: A.
B.
C.
D.
22
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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