ETC HY514400BT

HY514400B
FUNCTIONAL BLOCK DIAGRAM
DQ0 ~ DQ3
4
8
Data Input Buffer
WE
CAS
OE
Data Output Buffer
4
4
CAS Clock
Generator
4
A0
Cloumn
Predecoder
(10)
A1
10
Column Decoder
A3
A4
A5
A6
Address Buffer
A2
Sense Amp
I/O Gate
Refresh Controller
Refresh Counter
(10)
Row
Decoder
A7
A8
A9
RAS
Memory Array
1,048,576 x 4
10
Row Predecoder
(10)
RAS Clock
Generator
Substrate Bias
Generator
1Mx4,FP DRAM
Rev.10 / Jan.97
2
VCC
VSS
HY514400B
PIN CONFIGURATION (Marking Side)
DQ0
1
26
VSS
DQ0
1
26
VSS
DQ1
2
25
DQ3
DQ1
2
25
DQ3
WE
3
24
DQ2
WE
3
24
DQ2
RAS
4
23
CAS
RAS
4
23
CAS
A9
5
22
OE
A9
5
22
OE
A0
9
18
A8
A0
9
18
A8
A1
10
17
A7
A1
10
17
A7
A2
11
16
A6
A2
11
16
A6
A3
12
15
A5
A3
12
15
A5
Vcc
13
14
A4
Vcc
13
14
A4
20/26 Pin Plastic SOJ (300mil)
20/26 Pin Plastic TSOP- II (300mil)
PIN DESCRIPTION
Pin Name
Parameter
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
/OE
Output Enable
A0~A9
Address Input
DQ0~DQ3
Data In/Out
Vcc
Power (5V)
Vss
Ground
1Mx4,FP DRAM
Rev.10 / Jan.97
3
HY514400B
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Unit
TA
Ambient Temperature
0 to 70
°C
TSTG
Storage Temperature
-55 to 150
°C
VIN, VOUT
Voltage on Any Pin relative to VSS
-1.0 to 7.0
V
VCC
Voltage on VCC relative to VSS
-1.0 to 7.0
V
IOS
Short Circuit Output Current
50
mA
PD
Power Dissipation
0.9
W
TSOLDER
Soldering Temperature Ÿ Time
260 Ÿ 10
°C Ÿ sec
Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability
RECOMMENDED DC OPERATING CONDITIONS
(TA = 0°C to 70°C )
Symbol
Parameter
Min
Typ
Max
UNIT
VCC
Power Supply Voltage
4.5
5.0
5.5
V
VIH
Input High Voltage
2.4
-
VCC+1.0
V
VIL
Input Low Voltage
-1.0
-
0.8
V
Note : All voltages are referenced to VSS.
DC OPERATING CHARACTERISTICS
Symbol
Parameter
Test condition
Min
Max
Unit
ILI
Input Leakage Current
(Any input)
VSS ≤ VIN ≤ VCC + 1.0
All other pins not under test = VSS
-10
10
µA
ILO
Output Leakage Current
(Any input)
VSS ≤ VOUT ≤ VCC
/RAS & /CAS at VIH
-10
10
µA
VOL
Output Low Voltage
IOL = 4.2mA
-
0.4
V
VOH
Output High Voltage
IOH = -5.0mA
2.4
-
V
1Mx4,FP DRAM
Rev.10 / Jan.97
4
HY514400B
DC CHARACTERISTICS
(TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.)
Symbol
Parameter
Test condition
Speed
Max.
Unit
50
60
70
100
90
80
mA
2
mA
ICC1
Operating Current
/RAS, /CAS Cycling
tRC = tRC(min)
ICC2
TTL Standby
Current
/RAS, /CAS ≥ VIH(min)
Other inputs ≥ VSS
ICC3
/RAS-only Refresh
Current
/RAS Cycling,/CAS = VIH
tRC = tRC(min)
50
60
70
100
90
80
mA
Fast Page mode Current
/CAS Cycling, /RAS = VIL
tHPC = tHPC(min)
50
60
70
70
60
50
mA
CMOS Standby
Current
/RAS = /CAS ≥ VCC - 0.2V
SL-part
1
200
mA
µA
ICC6
/CAS-before-/RAS
Refresh Current
/RAS & /CAS = 0.2V
tRC = tRC(min.)
50
60
70
100
90
80
mA
ICC7
Battery Back-up
Current (SL-part)
tRC=125µs
/CAS = CBR cycling or 0.2V
/OE & /WE = VCC - 0.2V
Address = Vcc-0.2V or 0.2V
DQ0~DQ3 = Vcc-0.2, 0.2V or Open
300
/RAS & /CAS = 0.2V
Other pins are same as ICC7
200
ICC4
ICC5
ICC8
Self Refresh Current
(SL-part)
µA
µA
Note
1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tPC).
2. Specified values are obtained with output unloaded.
3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4,
address can be changed maximum once while /CAS=VIH within one cycle time tPC.
4. Only tRAS(max) = 1µs is applied to refresh of battery backup but tRAS(max) = 10µs is to applied to normal functional
operation.
5. Icc5(max.), Icc7 and Icc8 are applied to SL-part only.
1Mx4,FP DRAM
Rev.10 / Jan.97
5
HY514400B
AC CHARACTERISTICS
(TA = 0 °C to 70 °C, VCC = 5V ± 10% , VSS = 0V, unless otherwise noted.)
60ns
50ns
Symbol
70ns
Parameter
Unit
Min
Max
Min
Max
Min
Max
Note
tRC
Random read or write cycle time
90
-
110
-
130
-
ns
tRWC
Read-modify-write cycle time
130
-
155
-
185
-
ns
tPC
Fast Page mode cycle time
35
-
40
-
45
-
ns
tPRWC
Fast Page mode read-modify-write cycle time
75
-
80
-
95
-
ns
tRAC
Access time from /RAS
-
50
-
60
-
70
ns
4,9,10
tCAC
Access time from /CAS
-
15
-
15
-
20
ns
4,9
tAA
Access time from column address
-
25
-
30
-
35
ns
4,10
tCPA
Access time from /CAS precharge
-
30
-
35
-
40
ns
4,15
tCLZ
/CAS to output low impedance
0
-
0
-
0
-
ns
4
tT
Transition time(rise and fall)
3
50
3
50
3
50
ns
3
tRP
/RAS precharge time
30
-
40
-
50
-
ns
tRAS
/RAS pulse width
50
10K
60
10K
70
10K
ns
tRASP
/RAS pulse width(FP mode)
50
200K
60
200K
70
200K
ns
tRSH
/RAS hold time
15
-
15
-
20
-
ns
tCSH
/CAS hold time
50
-
60
-
70
-
ns
tCAS
/CAS pulse width
15
10K
15
10K
20
10K
ns
tRCD
/RAS to /CAS delay time
15
35
20
45
20
50
ns
9
tRAD
/RAS to column address delay time
10
25
15
30
15
35
ns
10
tCRP
/CAS to /RAS precharge time
5
-
5
-
5
-
ns
15
tCP
/CAS precharge time
10
-
10
-
10
-
ns
17
tASR
Row address set-up time
0
-
0
-
0
-
ns
tRAH
Row address hold time
8
-
10
-
10
-
ns
tASC
Column address set-up time
0
-
0
-
0
-
ns
14
tCAH
Column address hold time
15
-
15
-
15
-
ns
14
tAR
Column address hold time from /CAS
40
-
50
-
55
-
ns
tRAL
Column address to /RAS lead time
25
-
30
-
35
-
ns
tRCS
Read command set-up time
0
-
0
-
0
-
ns
14
tRCH
Read command hold time referenced to /CAS
0
-
0
-
0
-
ns
6,14
tRRH
Read command hold time referenced to /RAS
0
-
0
-
0
-
ns
6
tWCH
Write command hold time
10
-
10
-
15
-
ns
14
tWCR
Write command hold time from /RAS
40
-
45
-
55
-
ns
tWP
Write command pulse width
10
-
10
-
15
-
ns
tRWL
Write command to /RAS lead time
15
-
15
-
20
-
ns
1Mx4,FP DRAM
Rev.10 / Jan.97
6
HY514400B
AC CHARACTERISTICS
Continued
60ns
50ns
Symbol
70ns
Parameter
Min
Max
Min
Max
Min
Max
Unit
Note
tCWL
Write command to /CAS lead time
15
-
15
-
20
-
ns
16
tDS
Data-in set-up time
0
-
0
-
0
-
ns
7
tDH
Data-in hold time
15
-
15
-
15
-
ns
7
tDHR
Data-in hold time Referenced to /RAS
40
-
45
-
55
-
ns
Refresh period(1024 cycles)
16
-
16
-
16
-
ms
12
Refresh period(SL-part)
128
-
128
-
128
-
ms
11
tREF
tWCS
Write command set-up time
0
-
0
-
0
-
ns
84
tCWD
/CAS to /WE delay time
35
-
40
-
50
-
ns
8
tRWD
/RAS to /WE delay time
70
-
85
-
100
-
ns
8
tAWD
Column address to /WE delay time
45
-
55
-
65
-
ns
8
tCSR
/CAS set-up time(CBR cycle)
5
-
5
-
5
-
ns
14
tCHR
/CAS hold time(CBR cycle)
10
-
10
-
10
-
ns
15
tRPC
/RAS to /CAS precharge time
5
-
5
-
5
-
ns
14
tCPT
/CAS precharge time(CBR counter test)
20
-
20
-
25
-
ns
17
tROH
/RAS hold time referenced to /OE
10
-
10
-
10
-
ns
tOEA
/OE access time
-
15
-
15
-
20
ns
tOED
/OE to data delay
15
-
15
-
20
-
ns
tOEZ
Output buffer turn-off delay time from /OE
0
15
0
15
0
20
ns
tOEH
/OE command hold time
15
-
15
-
20
-
ns
tCPWD
/WE delay time from /CAS precharge
50
-
55
-
65
-
ns
tRHCP
/RAS hold time from /CAS precharge
30
-
35
-
40
-
ns
tRASS
/RAS pulse width(self refresh)
100
-
100
-
100
-
ns
tRPS
/RAS Precharge Time (Self refresh)
120
-
130
-
150
-
ns
tCHS
/CAS Hold Time (Self refresh)
-50
-
-50
-
-50
-
ns
tWRP
/WE to /RAS Precharge time (CBR cycle)
10
-
10
-
10
-
ns
tWRH
/WE to /RAS Hold time (CBR cycle)
10
-
10
-
10
-
ns
tWTS
Write Command Set-up time (Test Mode In)
10
-
10
-
10
-
ns
tWTH
Write Command Hole time (test Mode In)
10
-
10
-
10
-
ns
1Mx4,FP DRAM
Rev.10 / Jan.97
7
5
8
HY514400B
NOTE
1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper
device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of
8 /RAS-only refresh cycles are required.
2. If /RAS=Vss during power-up,the HY514400B could begin an active cycle. This condition results in higher current than
necessary current which is demanded from the power supply during power-up. It is recommended that /RAS and /CAS
track with Vcc during power-up or be held at a valid VIH in other to minimize the power-up current.
3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured
between VIH(min.) and VIL(max.),and are assumed to be 5ns for all inputs.
4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 100pF.
5. tOFF(max.) and tOEZ define the time at which the output achieves the open circuit condition and is not referenced to
output voltage levels.
6. Either tRCH or tRRH must be satisfied for a read cycle.
7. t CEZ and t OEZ define the time at which the output achieves the open circuit condition and is not referenced
to output voltage levels.
8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as
electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open
circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥
tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither
of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
9. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC.
10.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA.
11.tREF(max.)=128ms is applied to SL-parts only.
12.A burst of 1024 CBR refresh cycles must be executed within 16ms (128ms for SL-part) after exiting self refresh.
13.When CAS goes low at the same time, 4bits data are written into the device.
14.These parameters are determined by the earlier falling edge of /CAS.
15.These parameters are determined by the later rising edge of /CAS.
16.tCWL must be satisfied by /CAS for 4bits access cycle.
17.tCP and tCPT are measured when /CAS and is high state.
CAPACITANCE
(TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.)
Symbol
Parameter
Typ.
Max
Unit
CIN1
Input Capacitance (A0~A9)
-
5
pF
CIN2
Input Capacitance (/RAS, /CAS, /WE, /OE)
-
7
pF
CDQ
Data Input / Output Capacitance (DQ0~DQ3)
-
7
pF
1Mx4,FP DRAM
Rev.10 / Jan.97
8