ETC P06B03LV

Logic Level Enhancement P06B03LV
NIKO-SEM Dual P-Channel
Mode Field Effect Transistor
SOP-8
PRODUCT SUMMARY
V(BR)DSS
RDS(ON)
ID
-30
50mΩ
-6A
G :GATE
D :DRAIN
S :SOURCE
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
LIMITS
UNITS
Drain-Source Voltage
VDS
-30
V
Gate-Source Voltage
VGS
±20
V
TC = 25 °C
Continuous Drain Current
Pulsed Drain Current
-6
ID
TC = 70 °C
1
-5
IDM
TC = 25 °C
Power Dissipation
-30
2.5
PD
TC = 70 °C
Operating Junction & Storage Temperature Range
A
W
1.3
Tj, Tstg
-55 to 150
°C
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
SYMBOL
Junction-to-Ambient
TYPICAL
MAXIMUM
UNITS
62.5
°C / W
RθJA
1
Pulse width limited by maximum junction temperature.
Duty cycle ≤ 1%
2
ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
LIMITS
UNIT
MIN TYP MAX
STATIC
Drain-Source Breakdown Voltage
V(BR)DSS
VGS = 0V, ID = -250µA
-30
VGS(th)
VDS = VGS, ID = -250µA
-0.9
Gate-Body Leakage
IGSS
VDS = 0V, VGS = ±20V
Zero Gate Voltage Drain Current
IDSS
On-State Drain Current1
ID(ON)
Drain-Source On-State
Resistance1
RDS(ON)
Gate Threshold Voltage
Forward Transconductance1
gfs
-1.5
-3
±100 nA
VDS = -24V, VGS = 0V
1
VDS = -20V, VGS = 0V, TJ = 125 °C
10
VDS = -5V, VGS = -10V
V
-30
µA
A
VGS = -4.5V, ID =- 5A
65
80
VGS = -10V, ID = -6A
40
50
VDS = -10V, ID = -6A
16
mΩ
S
MAY-19-2003
1
Logic Level Enhancement P06B03LV
NIKO-SEM Dual P-Channel
Mode Field Effect Transistor
SOP-8
DYNAMIC
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
70
Qg
10
Total Gate Charge
2
Gate-Source Charge2
Gate-Drain Charge
2
Turn-On Delay Time
Rise Time
2
2
Turn-Off Delay Time
2
Fall Time2
530
VGS = 0V, VDS = -15V, f = 1MHz
Qgs
VDS = 0.5V(BR)DSS, VGS = -10V,
2.2
Qgd
ID = -6A
2
td(on)
pF
135
14
nC
5.7
tr
VDS = -15V, RL = 1Ω
10
td(off)
ID ≅ -1A, VGS = -10V, RGS = 6Ω
18
tf
nS
5
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C)
Continuous Current
IS
-2.1
Pulsed Current3
ISM
-4
Forward Voltage1
VSD
IF = -1A, VGS = 0V
Reverse Recovery Time
trr
IF = -5A, dlF/dt = 100A / µS
Reverse Recovery Charge
Qrr
-1.2
A
V
15.5
nS
7.9
nC
1
Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%.
Independent of operating temperature.
3
Pulse width limited by maximum junction temperature.
2
REMARK: THE PRODUCT MARKED WITH “P06B03LV”, DATE CODE or LOT #
MAY-19-2003
2
Logic Level Enhancement P06B03LV
NIKO-SEM Dual P-Channel
Mode Field Effect Transistor
SOP-8
Typical Characteristics
MAY-19-2003
3
Logic Level Enhancement P06B03LV
NIKO-SEM Dual P-Channel
Mode Field Effect Transistor
SOP-8
MAY-19-2003
4
Logic Level Enhancement P06B03LV
NIKO-SEM Dual P-Channel
Mode Field Effect Transistor
SOP-8
SOIC-8 (D) MECHANICAL DATA
Dimension
mm
Min.
Typ.
Max.
A
4.8
4.9
5.0
B
3.8
3.9
C
5.8
D
0.38
E
Dimension
mm
Min.
Typ.
Max.
H
0.5
0.715
0.83
4.0
I
0.18
0.254
0.25
6.0
6.2
J
0.445
0.51
K
1.27
0.22
0°
4°
8°
L
F
1.35
1.55
1.75
M
G
0.1
0.175
0.25
N
MAY-19-2003
5