TI 54ACT11533

SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
•
•
•
•
•
•
•
•
•
•
Eight Latches in a Single Package
3-State Bus-Driving Inverting Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
54ACT11533 . . . JT PACKAGE
74ACT11533 . . . DW OR NT PACKAGE
(TOP VIEW)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
OC
1D
2D
3D
4D
VCC
VCC
5D
6D
7D
8D
C
54ACT11533 . . . FK PACKAGE
(TOP VIEW)
The eight latches of the ′ACT11533 are
transparent D-type latches. While the enable (C)
is high, the Q outputs will follow the complements
of the (D) inputs. When the output control OC is
taken low, the Q outputs will be latched. The
′ACT11533 is functionally equivalent to the
′ACT11373 except for having inverted outputs.
A buffered output-control (OC) input can be used
to place the eight outputs in either a normal
logic state (high or low logic levels) or a highimpedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines
significantly. The high-impedance third state and
increased drive provide the capability to drive the
bus lines in a bus-organized system without need
for interface or pullup components.
The output control (OC) does not affect the
internal operations of the latches. Old data can be
retained or new data can be entered while the
outputs are off.
2D
1D
OC
NC
1Q
2Q
3Q
5
4
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
11
19
12 13 14 15 16 17 18
7D
8D
C
NC
8Q
7Q
6Q
4Q
GND
GND
NC
GND
GND
5Q
These eight latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
3D
4D
VCC
NC
VCC
5D
6D
description
NC − No internal connection
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OC
C
D
L
H
H
L
L
H
L
H
L
L
X
Q0
H
X
X
Z
The 54ACT11533 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT11533 is characterized for operation from − 40°C to 85°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright  1993, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2−1
SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
logic symbol†
OC
C
1D
2D
3D
4D
5D
6D
7D
8D
24
13
23
22
logic diagram (positive logic)
EN
OC
C1
C
1D
1
2
21
3
20
4
17
9
16
10
15
11
14
12
1Q
2Q
1D
3Q
4Q
2D
24
13
23
22
5Q
6Q
7Q
3D
8Q
4D
21
20
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
5D
6D
7D
8D
17
16
15
14
C1
1
1D
C1
2
1D
C1
3
1D
C1
4
1D
C1
9
1D
C1
10
1D
C1
11
1D
C1
1D
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Pin numbers shown are for the DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 200 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2−2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
recommended operating conditions
54ACT11533
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
Dt /Dv
Low-level output current
TA
Operating free-air temperature
High-level input voltage
74ACT11533
2
2
0.8
Input transition rise or fall rate
UNIT
V
V
0.8
V
VCC
VCC
V
−24
−24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/ V
−55
125
− 40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = − 50 mA
A
VOH
IOH = − 24 mA
IOH = − 50 mA{
IOH = − 75 mA{
TA = 25°C
MIN
TYP
54ACT11533
MAX
MIN
MAX
MIN
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
MAX
UNIT
V
3.85
5.5 V
IOL = 24 mA
74ACT11533
4.5 V
5.5 V
IOL = 50 mA
A
VOL
VCC
3.85
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
V
IOL = 50 mA{
IOL = 75 mA{
5.5 V
IOZ
VO = VCC or GND
5.5 V
± 0.5
± 10
±5
mA
II
VI = VCC or GND
5.5 V
± 0.1
±1
±1
mA
ICC
VI = VCC or GND,
5.5 V
8
160
80
mA
DICC}
One input at 3.4 V,
Other inputs at GND or VCC
5.5 V
0.9
1
1
mA
Ci
VI = VCC or GND
1.65
5.5 V
IO = 0
5V
1.65
4
Co
VO = VCC or GND
5V
10
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
pF
pF
2−3
SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
54ACT11533
MIN
74ACT11533
MAX
MIN
MAX
UNIT
tw
tsu
Pulse duration, C high
5
5
5
ns
Setup time, data before C↓
3.5
3.5
3.5
ns
th
Hold time, data after C↓
3.5
3.5
3.5
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
D
Q
tPLH
tPHL
C
Any Q
tPZH
tPZL
OC
Any Q
tPHZ
tPLZ
OC
Any Q
TA = 25°C
MIN
TYP
MAX
54ACT11533
74ACT11533
MIN
MAX
MIN
MAX
1.5
7
10.1
1.5
11.9
1.5
11.3
1.5
6.5
8.4
1.5
10.2
1.5
9.5
1.5
8.5
11.3
1.5
14.1
1.5
13
1.5
8.5
10.7
1.5
13.2
1.5
12.2
1.5
7.5
10.7
1.5
13.6
1.5
12.5
1.5
7.5
10.9
1.5
12.9
1.5
12
1.5
10.5
12.1
1.5
13.1
1.5
12.8
1.5
7.5
9.5
1.5
10.7
1.5
10.3
UNIT
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
2−4
Power dissipation capacitance per latch
Outputs disabled
POST OFFICE BOX 655303
TYP
UNIT
69
CL = 50 pF,
• DALLAS, TEXAS 75265
f = 1 MHz
58
pF
SCAS017A − D2957, JULY 1987 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
(see Note B)
1.5 V
0V
tw
tsu
3V
Input
1.5 V
1.5 V
th
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
(see Note B)
1.5 V
1.5 V
0V
tPHL
Output
tPLH
50% VCC
VOH
50% VCC
VOL
3V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note C)
Output
Waveform 2
S1 at GND
(see Note C)
1.5 V
1.5 V
50% VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2−5
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
74ACT11533DW
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
74ACT11533DWR
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
74ACT11533DWR
OBSOLETE
SOIC
DW
24
TBD
Call TI
Call TI
74ACT11533NT
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
74ACT11533NT
OBSOLETE
PDIP
NT
24
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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