TI SNJ54HC164FK

 SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
D
D
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 20 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
AND-Gated (Enable / Disable) Serial Inputs
Fully Buffered Clock and Serial Inputs
Direct Clear
SN54HC164 . . . J OR W PACKAGE
SN74HC164 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
A
B
QA
QB
QC
QD
GND
description/ordering information
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
QH
QG
QF
QE
CLR
CLK
SN54HC164 . . . FK PACKAGE
(TOP VIEW)
B
A
NC
VCC
QH
These 8-bit shift registers feature AND-gated
serial inputs and an asynchronous clear (CLR)
input. The gated serial (A and B) inputs permit
complete control over incoming data; a low at
either input inhibits entry of the new data and
resets the first flip-flop to the low level at the next
clock (CLK) pulse. A high-level input enables the
other input, which then determines the state of the
first flip-flop. Data at the serial inputs can be
changed while CLK is high or low, provided the
minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition
of CLK.
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
QG
NC
QF
NC
QE
QD
GND
NC
CLK
CLR
QA
NC
QB
NC
QC
NC − No internal connection
ORDERING INFORMATION
PACKAGE†
TA
PDIP − N
SN74HC164N
Tube of 50
SN74HC164D
Reel of 2500
SN74HC164DR
Reel of 250
SN74HC164DT
Reel of 2000
SN74HC164NSR
Tube of 90
SN74HC164PW
Reel of 2000
SN74HC164PWR
Reel of 250
SN74HC164PWT
CDIP − J
Tube of 25
SNJ54HC164J
SNJ54HC164J
CFP − W
Tube of 150
SNJ54HC164W
SNJ54HC164W
LCCC − FK
Tube of 55
SNJ54HC164FK
SOP − NS
TSSOP − PW
−55°C
125°C
−55
C to 125
C
TOP-SIDE
MARKING
Tube of 25
SOIC − D
−40°C to 85°C
ORDERABLE
PART NUMBER
SN74HC164N
HC164
HC164
HC164
SNJ54HC164FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
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POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
FUNCTION TABLE
OUTPUTS
INPUTS
CLR
CLK
A
B
QA
QB . . . QH
L
X
X
X
L
L
L
H
L
X
X
QA0
QB0
QH0
H
↑
H
H
H
QAn
QGn
H
↑
L
X
L
QAn
QGn
H
↑
X
L
L
QAn
QGn
QA0, QB0, QH0 = the level of QA, QB, or QH, respectively,
before the indicated steady-state input conditions were
established
QAn, QGn = the level of QA or QG before the most recent
↑ transition of CLK: indicates a 1-bit shift
logic diagram (positive logic)
CLK
A
B
CLR
8
1
2
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
9
3
4
5
6
QA
QB
QC
QD
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
2
C1
1D
R
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
10
QE
11
QF
12
QG
13
QH
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
typical clear, shift, and clear sequence
Serial Inputs
CLR
A
B
CLK
QA
QB
Outputs
QC
QD
QE
QF
QG
QH
Clear
Clear
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
recommended operating conditions (see Note 3)
SN54HC164
VCC
Supply voltage
VIH
VCC = 2 V
VCC = 4.5 V
High-level input voltage
VCC = 6 V
VCC = 2 V
VIL
VI
VO
Input voltage
NOM
MAX
2
5
6
NOM
MAX
2
5
6
1.5
3.15
3.15
4.2
4.2
0
VCC = 6 V
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
1.8
VCC
VCC
VCC = 2 V
VCC = 4.5 V
Input transition rise/fall time
MIN
1.5
0
Output voltage
∆t/∆v†
MIN
VCC = 4.5 V
VCC = 6 V
Low-level input voltage
SN74HC164
0
VCC
VCC
0
1000
1000
500
500
400
400
V
V
V
ns
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
† If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced
grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally,
the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −20 µA
VOH
VI = VIH or VIL
IOH = −4 mA
IOH = −5.2 mA
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
Ci
4
VI = VCC or 0
VI = VCC or 0,
IO = 0
TA = 25°C
TYP
MAX
SN54HC164
SN74HC164
VCC
MIN
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
MIN
MAX
5.2
MIN
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
8
160
80
µA
10
10
10
pF
6V
2 V to 6 V
POST OFFICE BOX 655303
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• DALLAS, TEXAS 75265
V
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
fclock
Clock frequency
CLR low
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK↑
CLR inactive
th
CLK↑
Hold time, data after CLK
TA = 25°C
MIN
MAX
SN54HC164
MIN
MAX
SN74HC164
MIN
MAX
2V
6
4.2
5
4.5 V
31
21
25
6V
36
25
28
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
80
120
100
4.5 V
16
24
20
6V
14
20
18
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
100
150
125
4.5 V
20
30
25
6V
17
25
21
2V
5
5
5
4.5 V
5
5
5
6V
5
5
5
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPHL
tpd
CLR
CLK
Any Q
Any Q
tt
VCC
MIN
TA = 25°C
TYP
MAX
SN54HC164
MIN
MAX
SN74HC164
MIN
2V
6
10
4.2
5
4.5 V
31
54
21
25
6V
36
62
25
28
MAX
UNIT
MHz
2V
140
205
295
255
4.5 V
28
41
59
51
6V
24
35
51
46
2V
115
175
265
220
4.5 V
23
35
53
44
6V
20
30
45
38
2V
38
75
110
95
4.5 V
8
15
22
19
6V
6
13
19
16
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TEST CONDITIONS
TYP
UNIT
No load
135
pF
5
SCLS115D − DECEMBER 1982 − REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
VCC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL = 50 pF
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
90%
90%
tr
th
90%
50%
10%
tPHL
Out-of-Phase
Output
90%
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
tPLH
50%
10%
tf
tf
VOH
50%
10%
VOL
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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