Evaluation board available. NX2119/2119A SYNCHRONOUS PWM CONTROLLER WITH CURRENT LIMIT PROTECTION PRELIMINARY DATA SHEET Pb Free Product DESCRIPTION FEATURES n n n n n n Bus voltage operation from 2V to 25V The NX2119 controller IC is a synchronous Buck conFixed 300kHz and 600kHz troller IC designed for step down DC to DC converter Internal Digital Soft Start Function applications. It is optimized to convert bus voltages from Prebias Startup 2V to 25V to outputs as low as 0.8V voltage. The Less than 50 nS adaptive deadband NX2119 operates at fixed 300kHz, while NX2119A operCurrent limit triggers latch out by sensing Rdson of ates at fixed 600kHz, making it ideal for applications Synchronous MOSFET requiring ceramic output capacitors. The NX2119 emn No negative spike at Vout during startup and ploys fixed loss-less current limiting by sensing the Rdson shutdown of synchronous MOSFET followed by latch out feature. n Pb-free and RoHS compliant Feedback under voltage triggers Hiccup. Other features of the device are: 5V gate drive, Adaptive deadband control, Internal digital soft start, Vcc n Graphic Card on board converters undervoltage lock out and shutdown capability via the n Memory Vddq Supply comp pin. n On board DC to DC such as 12V to 3.3V, 2.5V or 1.8V n ADSL Modem APPLICATIONS TYPICAL APPLICATION L2 1uH Vin C4 100uF C3 1uF 7 HI=SD M3 5 1 BST COMP C2 2.2nF 6 Cin 280uF 18mohm D1 MBR0530T1 Vcc R4 37.4k C7 27pF C5 1uF R5 10 C6 0.1uF Hdrv 2 M1 L1 1.5uH NX2119 +5V SW Ldrv Vout +1.8V 9A 8 4 FB Co 2 x (1500uF,13mohm) R1 4k M2 R2 10k C1 4.7nF Gnd 3 R3 8k Figure1 - Typical application of 2119 ORDERING INFORMATION Device NX2119CSTR NX2119ACSTR NX2119ACUTR Rev.3.2 04/10/08 Temperature 0 to 70oC 0 to 70o C 0 to 70o C Package SOIC - 8L SOIC - 8L MSOP - 8L Frequency 300kHz 600kHz 600kHz Pb-Free Yes Yes Yes 1 NX2119/2119A ABSOLUTE MAXIMUM RATINGS VCC to GND & BST to SW voltage .................... -0.3V to 6.5V BST to GND Voltage ........................................ -0.3V to 35V SW to GND ...................................................... -2V to 35V All other pins .................................................... -0.3V to VCC+0.3V or 6.5V Storage Temperature Range ............................... -65oC to 150oC Operating Junction Temperature Range ............... -40oC to 125oC ESD Susceptibility ........................................... 2kV CAUTION: Stresses above those listed in "ABSOLUTE MAXIMUM RATINGS", may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. PACKAGE INFORMATION 8-LEAD PLASTIC SOIC(S) 8-LEAD PLASTIC MSOP θJA ≈ 130o C/W BST 1 HDrv 2 θJA ≈ 216o C/W 8 SW BST HDrv Gnd LDrv 7 Comp Gnd 3 6 Fb LDrv 4 5 Vcc 1 8 2 7 3 6 4 5 SW Comp Fb Vcc ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply over Vcc = 5V, and TA= 0 to 70oC. Typical values refer to Ta = 25oC. Low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. PARAMETER Reference Voltage Ref Voltage Ref Voltage line regulation Supply Voltage(Vcc) VCC Voltage Range VCC Supply Current (Static) VCC Supply Current (Dynamic) VCC ICC (Static) Outputs not switching ICC CLOAD=3300pF FS=300kHz (Dynamic) Supply Voltage(VBST) VBST Supply Current (Static) IBST (Static) Outputs not switching VBST Supply Current (Dynamic) IBST CLOAD=3300pF (Dynamic) Rev.3.2 04/10/08 SYM Test Condition Min VREF TYP MAX 0.8 0.2 FS=300kHz 4.5 5 3 TBD Units V % 5.5 V mA mA 0.2 mA TBD mA 2 NX2119/2119A PARAMETER Under Voltage Lockout VCC-Threshold VCC-Hysteresis Oscillator (Rt) Frequency Ramp-Amplitude Voltage Max Duty Cycle Min Duty Cycle Min LDRV on time Controllable Min on time Error Amplifiers Transconductance Input Bias Current Comp SD Threshold Soft Start Soft Start time High Side Driver(CL=3300pF) Output Impedance , Sourcing Current Output Impedance , Sinking Current Rise Time Fall Time Deadband Time SYM TEST CONDITION VCC_UVLO VCC Rising VCC_Hyst VCC Falling FS 2119 2119A VRAMP Ib Tss FS=300kHz MIN TYP MAX UNITS 3.8 4 0.2 4.2 V V 300 600 1.5 93 0 250 100 kHz kHz V % % nS nS 2000 10 0.3 umho nA V 6.8 mS Rsource(Hdrv) I=200mA 0.9 ohm Rsink(Hdrv) I=200mA 0.65 ohm THdrv(Rise) VBST-VSW=4.5V THdrv(Fall) VBST-VSW=4.5V Tdead(L to Ldrv going Low to Hdrv going H) High, 10%-10% 50 50 30 ns ns ns Rsource(Ldrv) I=200mA Rsink(Ldrv) I=200mA TLdrv(Rise) 10% to 90% TLdrv(Fall) 90% to 10% Tdead(H to SW going Low to Ldrv going L) High, 10% to 10% 0.9 0.5 50 50 30 ohm ohm ns ns ns 320 mV Low Side Driver (CL=3300pF) Output Impedance, Sourcing Current Output Impedance, Sinking Current Rise Time Fall Time Deadband Time OCP OCP voltage Rev.3.2 04/10/08 3 NX2119/2119A PIN DESCRIPTIONS PIN # PIN SYMBOL PIN DESCRIPTION 5 VCC 1 BST This pin supplies voltage to high side FET driver. A high freq 0.1uF ceramic capacitor is placed as close as possible to and connected to these pins and respected SW pins. 3 GND Ground pin. 6 FB 7 COMP Power supply voltage. A high freq 1uF ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. This pin is the error amplifier inverting input. This pin is connected via resistor divider to the output of the switching regulator to set the output DC voltage. When FB pin voltage is lower than 0.6V, hiccup circuit starts to recycle the soft start circuit after 2048 switching cycles. This pin is the output of the error amplifier and together with FB pin is used to compensate the voltage control feedback loop. This pin is also used as a shut down pin. When this pin is pulled below 0.3V, both drivers are turned off and internal soft start is reset. This pin is connected to source of high side FET and provides return path for the high side driver. It is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. LDRV can only go high if SW is below 1V threshold . 8 SW 2 HDRV High side gate driver output. 4 LDRV Low side gate driver output. Rev.3.2 04/10/08 4 NX2119/2119A BLOCK DIAGRAM VCC FB Hiccup Logic 0.6V Bias Generator 1.25V OC 0.8V UVLO BST POR START HDRV COMP SW 0.3V OC Control Logic START 0.8V PWM OSC Digital start Up VCC ramp S R LDRV Q FB 0.6V CLAMP COMP START 1.3V CLAMP 320mV latch out OCP comparator GND Figure 2 - Simplified block diagram of the NX2119 Rev.3.2 04/10/08 5 NX2119/2119A APPLICATION INFORMATION Symbol Used In Application Information: VIN - Input voltage VOUT - Output voltage IOUT - Output current VIN -VOUT VOUT 1 × × LOUT VIN FS = DVRIPPLE - Output voltage ripple FS ∆IRIPPLE = ...(2) 5V-1.8V 1.8v 1 × × = 2.56A 1.5uH 5v 300kHz Output Capacitor Selection - Working frequency Output capacitor is basically decided by the DIRIPPLE - Inductor current ripple amount of the output voltage ripple allowed during steady state(DC) load condition as well as specification for the load transient. The optimum design may require a couple Design Example VIN = 5V of iterations to satisfy both condition. Based on DC Load Condition The amount of voltage ripple during the DC load VOUT=1.8V condition is determined by equation(3). The following is typical application for NX2119, the schematic is figure 1. FS=300kHz ∆VRIPPLE = ESR × ∆IRIPPLE + IOUT=9A DVRIPPLE <=20mV ∆IRIPPLE 8 × FS × COUT ...(3) Where ESR is the output capacitors' equivalent DVDROOP<=100mV @ 9A step series resistance,COUT is the value of output capacitors. Typically when large value capacitors are selected Output Inductor Selection such as Aluminum Electrolytic,POSCAP and OSCON The selection of inductor value is based on induc- types are used, the amount of the output voltage ripple tor ripple current, power rating, working frequency and is dominated by the first term in equation(3) and the efficiency. Larger inductor value normally means smaller second term can be neglected. ripple current. However if the inductance is chosen too For this example, POSCAP are chosen as output large, it brings slow response and lower efficiency. Usu- capacitors, the ESR and inductor current typically de- ally the ripple current ranges from 20% to 40% of the termines the output voltage ripple. output current. This is a design freedom which can be decided by design engineer according to various appli- ESR desire = cation requirements. The inductor value can be calcu- IRIPPLE =k × IOUTPUT tiple capacitors in parallel are better than a big capacitor. For example, for 20mV output ripple, POSCAP ...(1) where k is between 0.2 to 0.4. Select k=0.3, then 5V-1.8V 1.8V 1 × × 0.3 × 9A 5V 300kHz L OUT =1.4uH L OUT = Choose inductor from COILCRAFT DO5010P152HC with L=1.5uH is a good choice. Current Ripple is recalculated as ...(4) If low ESR is required, for most applications, mul- lated by using the following equations: V -V V 1 L OUT = IN OUT × OUT × ∆IRIPPLE VIN FS ∆VRIPPLE 20mV = = 7.8m Ω ∆IRIPPLE 2.56A 2R5TPE220MC with 12mΩ are chosen. N = E S R E × ∆ IR I P P L E ∆ VR IPPLE ...(5) Number of Capacitor is calculated as N= 12mΩ× 2.56A 20mV N =1.5 The number of capacitor has to be round up to a integer. Choose N =2. If ceramic capacitors are chosen as output ca Rev.3.2 04/10/08 6 NX2119/2119A pacitors, both terms in equation (3) need to be evalu- of output capacitor. For low frequency capacitor such ated to determine the overall ripple. Usually when this as electrolytic capacitor, the product of ESR and ca- type of capacitors are selected, the amount of capaci- pacitance is high and L ≤ L crit is true. In that case, the tance per single unit is not sufficient to meet the tran- transient spec is dependent on the ESR of capacitor. sient specification, which results in parallel configuration of multiple capacitors . For example, one 100uF, X5R ceramic capacitor with 2mΩ ESR is used. The amount of output ripple is ∆VRIPPLE is specified as: ∆VDROOP <∆VTRAN @ step load DISTEP During the transient, the voltage droop during the transient is composed of two sections. One Section is dependent on the ESR of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. For example, for the overshoot, when load from high load to light load with a DISTEP transient load, if assuming the bandwidth of system is high enough, the overshoot can be estimated as the following equation. ...(6) where τ is the a function of capacitor, etc. 0 if L ≤ L crit τ = L × ∆Istep − ESR × COUT V OUT L ≥ L crit ESR × COUT × VOUT ESR E × C E × VOUT = ∆Istep ∆Istep VOUT × τ2 2 × L × C E × ∆Vtran ...(9) tance of each capacitor if multiple capacitors are used in parallel. ...(10) If the POSCAP 2R5TPE220MC(220uF, 12mΩ ) is used, the critical inductance is given as L crit = ESR E × C E × VOUT = ∆Istep 12mΩ × 220µF × 1.9V = 0.56µH 9A The selected inductor is 1.5uH which is bigger than critical inductance. In that case, the output voltage transient not only dependent on the ESR, but also capacitance. number of capacitors is L × ∆Istep VOUT − ESR E × C E 1.5µH × 9A − 12mΩ × 220µF = 4.86us 1.8V N= where ESRE and CE represents ESR and capaci- L ≥ L crit sient is 100mV for 9A load step. ...(7) ...(8) if For example, assume voltage droop during tran- τ= where L crit = ∆Vtran + 0 if L ≤ L crit τ = L × ∆Istep − ESR E × CE V OUT = if ESR E × ∆Istep where Although this meets DC ripple spec, however it needs to be studied for transient requirement. Based On Transient Requirement Typically, the output voltage droop during transient VOUT × τ2 2 × L × COUT calculated by the following N= 2.56A = 2mΩ× 2.56A + 8 × 300kHz × 100uF = 15mV ∆Vovershoot = ESR × ∆Istep + In most cases, the output capacitors are multiple capacitors in parallel. The number of capacitors can be ESR E × ∆Istep ∆Vtran + VOUT × τ2 2 × L × CE × ∆Vtran 12mΩ × 9A + 100mV 1.8V × (4.86us) 2 2 ×1.5µH × 220µF × 100mV = 1.7 = The above equation shows that if the selected output inductor is smaller than the critical inductance, the The number of capacitors has to satisfied both ripple voltage droop or overshoot is only dependent on the ESR and transient requirement. Overall, we can choose N=2. Rev.3.2 04/10/08 7 NX2119/2119A It should be considered that the proposed equation is based on ideal case, in reality, the droop or over- FZ1 = 1 2 × π × R 4 × C2 ...(11) FZ2 = 1 2 × π × (R 2 + R3 ) × C3 ...(12) FP1 = 1 2 × π × R3 × C3 ...(13) shoot is typically more than the calculation. The equation gives a good start. For more margin, more capacitors have to be chosen after the test. Typically, for high frequency capacitor such as high quality POSCAP especially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the ESR of 1 FP2 = 2 × π × R4 × capacitors is so low that the PCB parasitic can affect the results tremendously. More capacitors have to be selected to compensate these parasitic parameters. Compensator Design Due to the double pole generated by LC filter of the power stage, the power system has 180o phase shift , and therefore, is unstable by itself. In order to achieve accurate output voltage and fast transient response,compensator is employed to provide highest possible bandwidth and enough phase margin.Ideally,the Bode plot of the closed loop system has crossover frequency between1/10 and 1/5 of the switching frequency, phase margin greater than 50o and the gain crossing 0dB with -20dB/decade. Power stage output capacitors usually decide the compensator type. If electrolytic capacitors are chosen as output capacitors, type II compensator can be used to compensate the system, be- ...(14) C1 × C2 C1 + C2 where FZ1,FZ2,FP1 and FP2 are poles and zeros in the compensator. Their locations are shown in figure 4. The transfer function of type III compensator for transconductance amplifier is given by: Ve 1 − gm × Z f = VOUT 1 + gm × Zin + Z in / R1 For the voltage amplifier, the transfer function of compensator is Ve −Z f = VOUT Zin To achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: R 4>>2/gm. And it would be desirable if R 1||R2||R3>>1/gm can be met at the same time. cause the zero caused by output capacitor ESR is lower than crossover frequency. Otherwise type III compensator should be chosen. A. Type III compensator design Zin R3 R2 For low ESR output capacitors, typically such as Sanyo oscap and poscap, the frequency of ESR zero C3 sate the system with type III compensator. The following figures and equations show how to realize the type III C2 R4 Fb caused by output capacitors is higher than the crossover frequency. In this case, it is necessary to compen- Zf C1 Vout gm Ve R1 Vref compensator by transconductance amplifier. Figure 3 - Type III compensator using transconductance amplifier Rev.3.2 04/10/08 8 NX2119/2119A Case 1: Choose R1=8kΩ. FLC<FO<FESR 3. Set zero FZ2 = FLC and Fp1 =FESR . Gain(db) 4. Calculate R4 and C3 with the crossover frequency at 1/10~ 1/5 of the switching frequency. Set power stage FO=30kHz. FLC 40dB/decade C3 = 1 1 1 ) ×( 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 10kΩ 6.2kHz 60.3kHz =2.3nF = loop gain FESR 20dB/decade VOSC 2 × π × FO × L × × Cout Vin C3 R4 = 1.5V 2 × π × 30kHz × 1.5uH × × 440uF 5V 2.2nF =16.9kΩ = compensator Choose C3=2.2nF, R 4=16.9kΩ. FZ1 FZ2 FO FP1 FP2 5. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). 1 2 × π × FZ1 × R 4 C2 = Figure 4 - Bode plot of Type III compensator 1 2 × π × 0.75 × 6.2kHz × 16.9kΩ = 2nF = Design example for type III compensator are in order. The crossover frequency has to be selected as FLC<FO<FESR, and FO<=1/10~1/5Fs. 1.Calculate the location of LC double pole F LC = 1 2 × π × L OUT × COUT 1 2 × π × 1.5uH × 440uF = 6.2kHz FESR 1 = 2 × π × ESR × C OUT 1 2 × π × 6m Ω × 440uF = 60.3kHz = 2. Set R2 equal to 10kΩ. R1 = Rev.3.2 04/10/08 6. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. and ESR zero FESR. FLC = Choose C2=2.2nF. R 2 × VREF 10k Ω × 0.8V = = 8k Ω VOUT -VREF 1.8V-0.8V 1 2 × π × R 4 × FP2 C1 = 1 2 × π × 16.9kΩ × 150kHz = 63pF = Choose C1=68pF. 7. Calculate R 3 by equation (13). R3 = 1 2 × π × FP1 × C3 1 2 × π × 60.3kHz × 2.2nF = 1.2kΩ = Choose R3=1.2kΩ. 9 NX2119/2119A Case 2: 2. Set R2 equal to 10kΩ. FLC<FESR<FO Gain(db) R1 = R 2 × VREF 10kΩ × 0.8V = = 8kΩ VOUT -VREF 1.8V-0.8V Choose R1=8.06kΩ. 3. Set zero FZ2 = FLC and Fp1 =FESR . 4. Calculate C3 . power stage FLC 40dB/decade C3 = FESR 1 1 1 ×( ) 2 × π × R2 Fz2 Fp1 1 1 1 ×( ) 2 × π × 10kΩ 2.3kHz 8.2kHz =4.76nF = loop gain 20dB/decade Choose C3=4.7nF. 5. Calculate R3 . R3 = compensator 1 2 × π × FP1 × C3 1 2 × π × 8.2kHz × 4.7nF = 4.1kΩ = FZ1 FZ2 FP1 FO FP2 Choose R3 =4kΩ. 6. Calculate R4 with FO=30kHz. R4 = Figure 5 - Bode plot of Type III compensator (FLC<FESR<FO) If electrolytic capacitors are used as output capacitors, typical design example of type III compensator in which the crossover frequency is selected as FLC<FESR<FO and F O<=1/10~1/5Fs is shown as the following steps. Here two SANYO MV-WG1500 with 13 mΩ is chosen as output capacitor. 1. Calculate the location of LC double pole F LC and ESR zero FESR. FLC = = 1 2 × π × LOUT × COUT 1 2 × π × 1.5uH × 3000uF = 2.3kHz FESR = 1 2 × π × ESR × COUT 1 2 × π × 6.5mΩ × 3000uF = 8.2kHz = Rev.3.2 04/10/08 VOSC 2 × π × FO × L R2 × R3 × × Vin ESR R 2 + R3 1.5V 2 × π × 30kHz × 1.5uH 10kΩ × 4kΩ × × 5V 6.5mΩ 10kΩ + 4kΩ =37.3kΩ = Choose R4=37.4kΩ. 7. Calculate C2 with zero Fz1 at 75% of the LC double pole by equation (11). C2 = 1 2 × π × FZ1 × R 4 1 2 × π × 0.75 × 2.3kHz × 37.4k Ω = 2.4nF = Choose C2=2.2nF. 8. Calculate C 1 by equation (14) with pole F p2 at half the switching frequency. C1 = 1 2 × π × R 4 × FP2 1 2 × π × 37.4kΩ × 150kHz = 28pF = Choose C1=27pF. 10 NX2119/2119A B. Type II compensator design If the electrolytic capacitors are chosen as power Vout stage output capacitors, usually the Type II compensator can be used to compensate the system. R2 Fb Type II compensator can be realized by simple RC circuit without feedback as shown in figure 6. R3 and C1 introduce a zero to cancel the double pole effect. C2 Ve gm R1 R3 Vref C2 introduces a pole to suppress the switching noise. The following equations show the compensator pole zero lo- C1 cation and constant gain. Gain=gm × R1 × R3 R1+R2 ... (15) Figure 7 - Type II compensator with 1 Fz = 2 × π × R3 × C1 Fp ≈ transconductance amplifier ... (16) 1 2 × π × R3 × C2 ... (17) For this type of compensator, FO has to satisfy FLC<FESR<<FO<=1/10~1/5Fs. The following is parameters for type II compensator design. Input voltage is 5V, output voltage is 1.8V, output inductor is 1.5uH, output capacitors are two Gain(db) power stage 1500uF with 13mΩ electrolytic capacitors. 40dB/decade 1.Calculate the location of LC double pole F LC and ESR zero FESR. FLC = loop gain Gain 1 = 20dB/decade compensator 1 2 × π × L OUT × COUT 2 × π × 1.5uH × 3000uF = 2.3kHz FESR = 1 2 × π × ESR × C OUT 1 2 × π × 6.5m Ω × 3000uF = 8.2kHz = FZ FLC FESR FO FP 2.Set R2 equal to 1kΩ. Figure 6 - Bode plot of Type II compensator R1 = R 2 × VREF 1kΩ × 0.8V = = 800Ω VOUT -VREF 1.8V-0.8V Choose R1=800Ω. 3. Set crossover frequency at 1/10~ 1/5 of the swithing frequency, here FO=30kHz. 4.Calculate R3 value by the following equation. Rev.3.2 04/10/08 11 NX2119/2119A Vout 4.Calculate R3 value by the following equation. V 2 × π × FO × L 1 VOUT × × R3 = OSC × Vin RESR gm VREF 1.5V 2 × π × 30kHz × 1.5uH 1 × × 5V 6.5mΩ 2.0mA/V 1.8V × 0.8V =14.6kΩ R2 Fb R1 = Vref Voltage divider Figure 8 - Voltage divider Choose R 3 =14.7kΩ. 5. Calculate C1 by setting compensator zero FZ at 75% of the LC double pole. 1 C1= 2 × π × R 3 × Fz Input Capacitor Selection Input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. Ceramic capacitors bypass the high frequency noise, and bulk ca- 1 = 2 × π × 14.7kΩ × 0.75 × 2.3kHz =6.3nF pacitors supply switching current to the MOSFETs. Usually 1uF ceramic capacitor is chosen to decouple the high frequency noise.The bulk input capacitors are de- Choose C1=6.8nF. cided by voltage rating and RMS current rating. The RMS 6. Calculate C 2 by setting compensator pole Fp current in the input capacitors can be calculated as: at half the swithing frequency. IRMS = IOUT × D × 1- D 1 C2= π × R 3 × Fs D= 1 p × 1 4 .7k Ω × 3 0 0 k H z =72pF = VOUT VIN ...(19) VIN = 5V, VOUT=1.8V, IOUT=9A, using equation (19), the result of input RMS current is 4.3A. For higher efficiency, low ESR capacitors are rec- Choose C1=68pF. ommended. One Sanyo OS-CON 16SP270M 16V 270uF Output Voltage Calculation 18mΩ with 4.4A RMS rating are chosen as input bulk capacitors. Output voltage is set by reference voltage and external voltage divider. The reference voltage is fixed at 0.8V. The divider consists of two ratioed resistors Power MOSFETs Selection The power stage requires two N-Channel power so that the output voltage applied at the Fb pin is 0.8V MOSFETs. The selection of MOSFETs is based on when the output voltage is at the desired value. The maximum drain source voltage, gate source voltage, following equation and picture show the relationship maximum current rating, MOSFET on resistance and between VOUT , VREF and voltage divider.. R 1= R 2 × VR E F V O U T -V R E F power dissipation. The main consideration is the power loss contribution of MOSFETs to the overall converter ...(18) where R 2 is part of the compensator, and the value of R1 value can be set by voltage divider. See compensator design for R1 and R2 selection. efficiency. In this design example, two IRFR3706 are used. They have the following parameters: V DS=30V, ID =75A,RDSON =9mΩ,QGATE =23nC. There are two factors causing the MOSFET power loss:conduction loss, switching loss. Conduction loss is simply defined as: Rev.3.2 04/10/08 12 NX2119/2119A PHCON =IOUT 2 × D × RDS(ON) × K PLCON =IOUT 2 × (1 − D) × RDS(ON) × K PTOTAL =PHCON + PLCON ISET = ...(20) 320mV K × RDSON If MOSFET RDSON=9mΩ, the worst case thermal consideration K=1.5, then where the RDS(ON) will increases as MOSFET junc- ISET = tion temperature increases, K is RDS(ON) temperature 320mV 320mV = = 23.7A K × RDSON 1.5 × 9mΩ dependency. As a result, RDS(ON) should be selected for the worst case, in which K approximately equals to 1.4 at 125oC according to IRFR3706 datasheet. Conduction loss should not exceed package rating or overall system thermal budget. Switching loss is mainly caused by crossover conduction at the switching transition. The total switching loss can be approximated. The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled ar- 1 PSW = × VIN × IOUT × TSW × FS ...(21) 2 where IOUT is output current, TSW is the sum of TR and TF which can be found in mosfet datasheet, and FS is switching frequency. Switching loss PSW is frequency dependent. Also MOSFET gate driver loss should be considered when choosing the proper power MOSFET. MOSFET gate driver loss is the loss generated by discharging the gate capacitor and is dissipated in driver circuits.It is proportional to frequency and is defined as: Pgate = (QHGATE × VHGS + QLGATE × VLGS ) × FS Layout Considerations ...(22) eas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources,and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. where QHGATE is the high side MOSFETs gate The goal is to localize the high current path to a charge,QLGATE is the low side MOSFETs gate charge,VHGS separate loop that does not interfere with the more sen- is the high side gate source voltage, and VLGS is the low sitive analog control function. These two grounds must side gate source voltage. This power dissipation should not exceed maximum power dissipation of the driver device. be connected together on the PC board layout at a single point. Over Current Limit Protection Over current Limit for step down converter is achieved by sensing current through the low side MOSFET. For NX2119, the current limit is decided by the RDSON of the low side mosfet. When synchronous FET is on, and the voltage on SW pin is below 320mV, the over current occurs. The over current limit can be calculated by the following equation. Rev.3.2 04/10/08 13 NX2119/2119A SOIC8 PACKAGE OUTLINE DIMENSIONS Rev.3.2 04/10/08 14 NX2119/2119A Rev.3.2 04/10/08 15 NX2119/2119A MSOP8 PACKAGE OUTLINE DIMENSIONS Rev.3.2 04/10/08 16

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