AKM AK5367

[AK5367]
AK5367
96kHz 24-Bit ΔΣ ADC with 0V Bias Selector
GENERAL DESCRIPTION
AK5367 is a high-performance 24-bit, 96kHz sampling ADC for consumer audio and digital recording
applications. The AK5367 uses an Enhanced Dual-Bit modulator architecture, this analog-to-digital
converter has an impressive dynamic range of 102dB with a high level of integration. The AK5367 has a
4-channel stereo input selector, an input Programmable Gain Amplifier with resistance. All this integration
with high-performance makes the AK5367 well suited for CD and DVD recording systems. The integrated
charge pump circuit can generate the negative power supply and remove the output coupling capacitor.
FEATURES
1. 24bit Stereo ADC
• 4:1 0V Bias Stereo input Selector
• Digital HPF for offset cancellation ([email protected]=48kHz)
• Decimation LPF: -0.2dB@ 20kHz, [email protected] (fs=48kHz)
• Soft Mute
• Single-end Inputs
• S/(N+D): 90dB
• DR, S/N: 102dB
• Audio I/F Format: 24bit MSB justified, I2S
2. Control Interface: I2C-Bus
3. Master Mode / Slave Mode
4. Master Clock:
• 256fs/384fs (32kHz ∼ 96kHz)
• 512fs/768fs (32kHz ∼ 48kHz)
5. Sampling Rate: 32kHz to 96kHz
6. Power Supply
• Analog Supply: 4.5 ∼ 5.5V
• Digital Supply: 3.0 ∼ 3.6V
7. Ta = −20 ∼ 85°C
8. Package: 30pin VSOP
MS0694-E-00
2007/12
-1-
[AK5367]
■ Block Diagram
24K
10μ
+
LOPIN LOUT
0V
2Vrms
47K
LIN1
47K
LIN2
47K
LIN3
47K
LIN4
0V
2Vrms
RIN1
47K
RIN2
47K
RIN3
47K
RIN4
PDN
AVDD
VSS1
DVDD
VCOM
HPF
ADC
Vcom=0V
47K
LISEL
ADC
Audio
I/F
0V
1Vrms
LRCK
BICK
SDTO
ADC
MCLK
HPF
SCL
SDA
Charge
Pump
ROPIN ROUT
24K
+
10μ
RISEL
CP
CN
0.1μ
CVEE VSS2 CVDD
1μ
Figure 1. AK5367 Block Diagram
MS0694-E-00
2007/12
-2-
[AK5367]
■ Ordering Guide
−20 ∼ +85°C
30pin VSOP (0.65mm pitch)
Evaluation Board for AK5367
AK5367EF
AKD5367
■ Pin Layout
VCOM
1
30
AVDD
LIN1
2
29
VSS1
RIN1
3
28
DVDD
LIN2
4
27
LRCK
RIN2
5
26
MCLK
LIN3
6
25
BICK
RIN3
7
24
SDTO
LIN4
8
23
SCL
RIN4
9
22
SDA
RISEL
10
21
PDN
ROUT
11
20
CP
ROPIN
12
19
CN
LOPIN
13
18
CVDD
LOUT
14
17
VSS2
LISEL
15
16
CVEE
AK5367EF
Top View
MS0694-E-00
2007/12
-3-
[AK5367]
PIN/FUNCTION
No.
Pin Name
I/O
1
VCOM
O
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LIN1
RIN1
LIN2
RIN2
LIN3
RIN3
LIN4
RIN4
RISEL
ROUT
ROPIN
LOPIN
LOUT
I
I
I
I
I
I
I
I
I
O
O
O
O
LISEL
I
16
CVEE
O
17
VSS2
-
18
CVDD
-
19
CN
I
20
CP
O
21
PDN
I
22
23
SDA
SCL
I/O
I
24
SDTO
O
25
BICK
I/O
26
MCLK
I
Function
Common Voltage Output Pin, AVDD/2
Bias voltage of ADC input.
Lch Analog Input 1 Pin
Rch Analog Input 1 Pin
Lch Analog Input 2 Pin
Rch Analog Input 2 Pin
Lch Analog Input 3 Pin
Rch Analog Input 3 Pin
Lch Analog Input 4 Pin
Rch Analog Input 4 Pin
Rch Analog Input Pin
Rch Feedback Resistor Output Pin
Rch Feedback Resistor Input Pin
Lch Feedback Resistor Intput Pin
Lch Feedback Resistor Output Pin
Lch Analog Input Pin
Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF capacitor that should have the low ESR
(Equivalent Series Resistance) over all temperature range. When this capacitor
has the polarity, the positive polarity pin should be connected to the VSS2 pin.
Non polarity capacitors can also be used.
Charge Pump Ground Pin, 0V
Connect to CVEE with a 1.0μF capacitor that should have the low ESR
(Equivalent Series Resistance) over all temperature range. When this capacitor
has the polarity, the positive polarity pin should be connected to the VSS2 pin.
Non polarity capacitors can also be used.
Charge Pump Power Supply Pin, 3.0V∼3.6V
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 0.1μF capacitor that should have the low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the
polarity, the positive polarity pin should be connected to the CP pin. Non polarity
capacitors can also be used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 0.1μF capacitor that should have the low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the
polarity, the positive polarity pin should be connected to the CP pin. Non polarity
capacitors can also be used.
Power Down Mode & Reset Pin
“H”: Power up, “L”: Power down & Reset
The AK5367 must be reset once upon power-up.
Control Data Input / Output Pin in I2C Control
Control Data Clock Pin in I2C Control
Audio Serial Data Output Pin
“L” Output at Power-down mode.
Audio Serial Data Clock Pin
“L” Output in Master Mode at PWN bit= “0”.
Master Clock Input Pin
MS0694-E-00
2007/12
-4-
[AK5367]
No.
Pin Name
I/O
27
LRCK
I/O
28
29
30
DVDD
VSS1
AVDD
-
Function
Channel Clock Pin
“L” Output in Master Mode at PWN bit= “0”.
Digital Power Supply Pin, 3.0∼ 3.6V
Analog Ground Pin
Analog Power Supply Pin, 4.5 ∼ 5.5V
Note: All input pins except analog input pins (RISEL, LISEL, LIN1-4, RIN1-4) should not be left floating.
■ Handling of Unused Pin
The unused input pins should be processed appropriately as below.
Classification
Analog
Pin Name
LIN1-4,RIN1-4,LISEL,RISEL
LOPIN,LOUT,ROPIN,ROUT
Setting
These pins should be open.
MS0694-E-00
2007/12
-5-
[AK5367]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 1, Note 2)
Parameter
Symbol
Power Supplies:
Analog
AVDD
Digital
DVDD
Charge Pump
CVDD
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage(LISEL,RISEL,LIN1-4, RIN1-4 pins)
VINA
Digital Input Voltage
(Note 3)
VIND
Ambient Temperature (Powered applied)
Ta
Storage Temperature
Tstg
Note 1. All voltages with respect to ground.
Note 2. VSS1 and VSS2 must be connected to the same analog ground plane.
Note 3. PDN,SCL,SDA,MCLK,BICK,LRCK pins
min
−0.3
−0.3
−0.3
−0.3
−0.3
−20
−65
max
6.0
6.0
4.0
±10
AVDD+0.3
DVDD+0.3
85
150
Units
V
V
V
mA
V
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V;Note 1)
Parameter
Symbol
min
typ
max
Units
Analog
AVDD
4.5
5.0
5.5
V
Power Supplies
Digital
DVDD
3.0
3.3
3.6
V
(Note 4)
Charge Pump
CVDD
3.0
3.3
3.6
V
DVDD-CVDD
ΔVDD
-0.3
0
+0.3
V
Note 4. The power up sequence between AVDD, DVDD and CVDD is not critical.
In slave mode, the AK5367 must be power up at the PDN pin = “L”.
In master mode, the AK5367 must be power up at the PDN pin = “L”, or when DVDD is powered up, MCLK
clock must input and the AK5367 must be reset by the PDN pin=“L”. The internal register data is unknown until
PDN pin=“L”. The power on/off sequence between AVDD, DVDD and CVDD is not critical, however when
DVDD is powered off, all digital input pins must be left floating or held to VSS.
The power off is means that AVDD, CVDD and DVDD are floating or short to VSS.
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0694-E-00
2007/12
-6-
[AK5367]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=5.0V, DVDD=CVDD=3.3V; VSS1=VSS2=0V; fs=48kHz,96kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz;
unless otherwise specified)
Parameter
min
typ
max
Units
Pre-Amp Characteristics:
Feedback Resistance
10
50
kΩ
S/(N+D)
(Note 5)
100
dB
S/N (A-weighted)
(Note 5)
108
dB
Load Resistance
RL
(Note 6)
15
kΩ
Load Capacitance CL
(Note 6)
20
pF
ADC Analog Input Characteristics: (Note 7)
Resolution
24
Bits
Input Voltage
(Note 8)
2.7
3.0
3.3
Vpp
S/(N+D)
fs=48kHz
−1dBFS
82
90
dB
BW=20kHz
−60dBFS
39
dB
fs=96kHz
−1dBFS
90
dB
BW=40kHz
−60dBFS
37
dB
DR
(−60dBFS, A-weighted)
94
102
dB
S/N
(A-weighted)
94
102
dB
Interchannel Isolation (fs=48kHz)
(Note 9)
85
96
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
100
ppm/°C
Power Supply Rejection
(Note 10)
50
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
mA
23
15.5
AVDD
mA
4
2.5
CVDD
mA
3
2
DVDD
(fs=48kHz)
mA
6
4
DVDD
(fs=96kHz)
Power down mode (PDN pin = “L”)
(Note 11)
μA
100
10
AVDD+DVDD
Note 5. This value is measured at LOUT and ROUT pins using Ri= 47kΩ, Rf= 24 kΩ when the input signal voltage is
2Vrms.
Note 6. This value of RL and CL are load resistance and capacitance that the LOUT and ROUT pins can drive. RL does not
include the feedback resistor (Rf) and the input impedance of the LISEL/RISEL pins. The value of CL does not
include the internal impedance of the AK5367.
Note 7. This value is measured via the following path. Pre-Amp → ADC.(Ri= 47kΩ, Rf= 24 kΩ)
Note 8. Input voltage to LISEL and RISEL pins is proportional to AVDD voltage. typ. Vin = 0.6 x AVDD (Vpp)
Note 9. 93dB(typ.) at fs=96kHz.
Note 10. PSR is applied to AVDD and DVDD with 1kHz, 50mVpp Sine wave.
Note 11. All digital input pins are held DVDD or VSS2.
MS0694-E-00
2007/12
-7-
[AK5367]
RL
Rf
C1=10μF
LOPIN LOUT
0V
CL
LISEL
R i LIN1
R i LIN2
R i LIN3
-
ADC
+
0V
R i LIN4
AK5367
Figure 2. Pre-Amp Circuit
MS0694-E-00
2007/12
-8-
[AK5367]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta=−20 ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 12) ±0.1dB
PB
0
−0.2dB
20.0
−3.0dB
23.0
Stopband
SB
28
Passband Ripple
PR
Stopband Attenuation
SA
68
Group Delay Distortion
ΔGD
0
Group Delay
(Note 13)
GD
20
ADC Digital Filter (HPF):
Frequency Response (Note 12) −3dB
FR
1.0
−0.1dB
6.5
max
Units
18.9
-
kHz
kHz
kHz
kHz
dB
dB
μs
1/fs
±0.04
Hz
Hz
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=−20 ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband
(Note 12) ±0.1dB
PB
0
37.8
kHz
−0.2dB
40.0
kHz
−3.0dB
46.0
kHz
Stopband
SB
56
kHz
Passband Ripple
PR
±0.04
dB
Stopband Attenuation
SA
68
dB
Group Delay Distortion
ΔGD
0
μs
Group Delay
(Note 13)
GD
20
1/fs
ADC Digital Filter (HPF):
Frequency Response (Note 12) −3dB
FR
2.0
Hz
−0.1dB
13.0
Hz
Note 12. The passband and stopband frequencies scale with fs. For example, PB= 18.9kHz@±0.1dB is 0.39375 x fs,
(fs=48kHz).
Note 13. The calculated delay time induced by digital filtering. This time is from the input of an analog signal
to the setting of 24bit data both channels to the ADC output register for ADC.
DC CHARACTERISTICS
(Ta=-20°C ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage
(Iout=−1mA)
VOH
DVDD−0.5
Low-Level Output Voltage
(Except SDA pin: Iout=1mA)
VOL
(SDA pin: Iout=3mA)
VOL
Input Leakage Current
Iin
-
MS0694-E-00
typ
-
max
30%DVDD
-
Units
V
V
V
-
0.5
0.4
±10
V
V
μA
2007/12
-9-
[AK5367]
SWITCHING CHARACTERISTICS
(Ta=-20°C ∼ 85°C; AVDD=4.5 ∼ 5.5V; DVDD=CVDD=3.0 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
8.192
fCLK
512fs, 256fs Frequency
16
tCLKL
Pulse Width Low
16
tCLKH
Pulse Width High
12.288
fCLK
768fs, 384fs Frequency
10.5
tCLKL
Pulse Width Low
10.5
tCLKH
Pulse Width High
LRCK Frequency
fs
32
Duty Cycle
Slave mode
45
Master mode
Audio Interface Timing
Slave mode
160
tSCK
BICK Period
65
tSCKL
BICK Pulse Width Low
65
tSCKH
Pulse Width High
30
tLRSH
LRCK Edge to BICK “↑”
(Note 14)
30
tSHLR
BICK “↑” to LRCK Edge
(Note 14)
tLRS
LRCK to SDTO (MSB) (Except I2S mode)
tSSD
BICK “↓” to SDTO
Master mode
BICK Frequency
fSCK
BICK Duty
dSCK
BICK “↓” to LRCK
tMSLR
−20
BICK “↓” to SDTO
tSSD
−20
2
Control Interface Timing (I C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 15)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
Capacitive load on bus
typ
max
Units
24.576
MHz
ns
ns
MHz
ns
ns
36.864
96
55
50
kHz
%
%
35
35
ns
ns
ns
ns
ns
ns
ns
20
35
Hz
%
ns
ns
64fs
50
fSCL
tBUF
tHD:STA
1.3
0.6
400
-
kHz
μs
μs
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
1.3
0.6
0.6
0
0.1
0.6
0
0.3
0.3
50
μs
μs
μs
μs
μs
μs
μs
μs
ns
Cb
-
400
pF
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. Data must be held long enough to bridge the 300ns-transition time of SCL.
MS0694-E-00
2007/12
- 10 -
[AK5367]
Parameter
Symbol
min
Reset Timing
tPD
150
PDN Pulse Width
(Note 16)
tPDV
PDN “↑” to SDTO valid at Slave Mode (Note 17)
tPDV
PDN “↑” to SDTO valid at Master Mode (Note 17)
Note 16. The AK5367 can be reset by bringing the PDN pin = “L”.
Note 17. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
MS0694-E-00
typ
4388
4385
max
Units
ns
1/fs
1/fs
2007/12
- 11 -
[AK5367]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tSCK
VIH
BICK
VIL
tSCKH
tSCKL
Figure 3. Clock Timing
VIH
LRCK
VIL
tSHLR
tLRSH
VIH
BICK
VIL
tLRS
tSSD
SDTO
50%DVDD
Figure 4. Audio Interface Timing (Slave mode)
MS0694-E-00
2007/12
- 12 -
[AK5367]
50%DVDD
LRCK
tMSLR
dSCK
BICK
50%DVDD
tSSD
SDTO
50%DVDD
Figure 5. Audio Interface Timing (Master mode)
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
Start
tSU:STA
tSU:STO
Start
Stop
Figure 6. I2C Bus mode Timing
VIH
PDN
VIL
tPDV
SDTO
50%DVDD
tPD
PDN
VIL
Figure 7. Power Down & Reset Timing
MS0694-E-00
2007/12
- 13 -
[AK5367]
OPERATION OVERVIEW
■ System Clock
MCLK, BICK and LRCK clocks are required. The LRCK clock input must be synchronized with MCLK, however the
phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. The
MCLK, BICK and master/slave mode setting are selected by CKS2-0 bits(Table 2).
In slave mode, all external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L”. If these clocks are
not provided, the AK5367 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5367 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless PDN pin = “L”. It is not necessary to reset by bringing PDN pin “L” when clocks and
fs are changed. They should be changed after soft mute (SMUTE bit = “1”) to avoids the switching noise.
fs
32kHz
44.1kHz
48kHz
96kHz
MCLK
256fs
384fs
512fs
768fs
8.192MHz
12.288MHz
16.384MHz
24.576MHz
11.2896MHz
16.9344MHz
22.5792MHz
33.8688MHz
12.288MHz
18.432MHz
24.576MHz
36.864MHz
24.576MHz
36.864MHz
N/A
N/A
Table 1. System Clock Example (N/A: Not available)
Mode
CKS2
CKS1
CKS0
0
0
0
0
1
2
3
4
5
6
7
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Master/Slave
MCLK
256/384fs (32k≤fs≤96k)
Slave
512/768fs (32k≤fs≤48k)
Reserved
Master
256fs (32k≤fs≤96k)
Master
512fs (32k≤fs≤48k)
Reserved
Reserved
Master
384fs (32k≤fs≤96k)
Master
768fs (32k≤fs≤48k)
Table 2. Operation Mode Select
BICK
≥ 48fs or 32fs
(Note 18)
(default)
64fs
64fs
64fs
64fs
Note 18. The SDTO output is 16bit when BICK=32fs input.
MS0694-E-00
2007/12
- 14 -
[AK5367]
■ Audio Interface Format
Two kinds of data formats can be chosen with the DIF bit (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of BICK. The audio interface supports both master and
slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF bit
0
1
SDTO
LRCK
BICK(Slave) BICK(Master)
64fs
24bit, MSB justified
H/L
≥ 48fs or 32fs
64fs
24bit, I2S Compatible
L/H
≥ 48fs or 32fs
Table 3. Audio Interface Format
Figure
Figure 8
Figure 9
(default)
LRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 8. Mode 0 Timing
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 9. Mode 1 Timing
■ Master Mode and Slave Mode
The AK5367 becomes slave mode when it is in the power-down mode (PDN pin = “L”) or exiting power-down. After
exiting the power-down mode, master mode should be set by CKS0-2 bits.
In master mode, LRCK and BICK pins are floating until CKS0-2 bits fixed. Therefore BICK and LRCK pins must be
connected with 100 kΩ pull-up or pull-down resistance.
MS0694-E-00
2007/12
- 15 -
[AK5367]
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz) and scales with sampling rate (fs).
■ Power-down
The AK5367 is placed in the power-down mode by bringing PDN pin = “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. At the power-down mode, the VCOM voltage is become VSS1.
After exiting the power-down mode, the Charge pump circuit is powered up, and then Pre-Amp circuit is auto powered up
and an analog initialization cycle starts(Figure 10). Therefore, the output data SDTO becomes available after 4388 x
LRCK cycles at slave mode, and 4385 x LRCK cycles at master mode. In the initialization, the both channel of ADC
output is “0” of 2’s complement. After the initialization, the ADC output is settled to the data equal to analog input
signal.(the setting time is same as group delay)
Power Supply
(1)
(AVDD, DVDD, CVDD)
(1)
PDN
Charge Pump
Internal State
Power-down
0V
CVEE Pin
ADC
Internal State
power-up
Power-down
Normal Operation
(5)
0V
power-up
-CVDD
Power-down
Pre-amp In
(Analog)
ADC OUT
(Digital)
power-up
Normal Operation
(5)
-CVDD
Initialize
Power-down
Normal Operation
power-up
Initialize
Normal Operation
(2)
(2)
(2)
GD
GD
GD
(3)
(3)
“0”data
Idle Noise
“0”data
Idle Noise
Idle Noise
(4)
Clock In
MCLK,LRCK,BICK
Notes:
(1) 4388/fs at slave mode, 4385/fs at master mode.
(2) Analog output corresponding to digital input has group delay (GD).
(3) ADC output is “0” data at the power-down mode.
(4) Place the AK5367 in power-down mode if MCLK, BICK and LRCK are not present.
(5) Power-up time of Charge Pump Circuit. 260/fs (slave mode), 257/fs (master mode).
Figure 10. Power-down/up sequence example
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[AK5367]
■ System Reset
The AK5367 should be reset once by bringing PDN pin “L” after power-up. At the slave mode, the internal timing starts
clocking by the rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.
The AK5367 is in power-down states until the LRCK is input. At the master mode, bringing PDN pin “H” and exiting
from reset and power down state by MCLK input.
■ Soft Mute Operation
Soft mute operation is performed in the digital domain of the ADC output. When SMUTE bit goes “1”, the ADC output
data is attenuated to −∞ within 1024 LRCK cycles. When the SMUTE bit returned “0”, the mute is cancelled and the
output attenuation gradually changes to 0dB within 1024 LRCK cycles. If the soft mute is cancelled before mute state
after starting of the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for changing
the signal source without stopping the signal transmission.
SM U T E bit
1024/fs
1024/fs
(1)
0dB
(2)
Attenuation
-∞
SD T O O utput D ata
“0” data
Figure 11. Soft Mute Function
Notes:
(1) The output signal is attenuated by −∞ within 1024 LRCK cycles (1024/fs).
(2) If the soft mute is cancelled before the mute, the attenuation is discontinued and returned to 0dB by the same cycle.
■ Input Selector
The AK5367 includes 4ch stereo input selectors. The input selector is 4 to 1 selector and set by SEL2-0 bits (Table 4).
SEL2 bit
0
0
0
0
1
SEL1 bit
0
0
1
1
0
SEL0 bit
Input Selector
0
LIN1 / RIN1
1
LIN2 / RIN2
0
LIN3 / RIN3
1
LIN4 / RIN4
0
All off (Note)
Table 4. Input Selector
(default)
Note: The LOUT, ROUT pin are 0V.
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[AK5367]
[Input selector switching sequence]
The input selector should be changed after soft mute to avoid the switching noise of the input selector (Figure 12).
1. Enable the soft mute before changing channel.
2. Change channel.
3. Disable the soft mute.
S M U T E bit
0dB
(1)
(1)
(2)
A ttenuation
-∞
C hannel
LIN 1/R IN 1
LIN 2/R IN 2
Figure 12. Input channel switching sequence example
Note:
(1) The output signal is attenuated by −∞ within 1024 LRCK cycles (1024/fs).
(2) When changing channels, the input channel should be changed during (2). The period of (2) should be around
200ms because there is some DC difference between the channels.
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[AK5367]
■ Pre-Amp and Input Attenuator
The input ATTs are constructed by adding the input resistor (Ri) for LIN1-4/RIN1-4 pins and the feedback resistor (Rf)
between LOPIN/ROPIN pin and LOUT/ROUT pin (Figure 13). The input voltage range of the LISEL/RISEL pin is
typically 0.6 x AVDD (Vpp). If the input voltage of the input selector exceeds typ. 0.6 x AVDD, the input voltage of the
LISEL/RISEL pins must be attenuated to 0.6 x AVDD by the input ATTs. Table 5 shows the example of Ri and Rf.
Rf
LOPIN
Ri
LIN1
Ri
LIN2
Ri
LIN3
Ri
LIN4
Ri
RIN1
Ri
RIN2
Ri
RIN3
Ri
RIN4
C1=10μF
LOUT
LISEL
ADC
Pre-Amp
Pre-Amp
ADC
ROPIN
ROUT
Rf
RISEL
C1=10μF
Figure 13. Pre-Amp and Input ATT
• Example for input range
Input Range
4Vrms
2Vrms
1Vrms
Ri [kΩ]
47
47
47
ATT Gain [dB]
Rf [kΩ]
12
−11.86
24
−5.84
47
0
Table 5. Input ATT example
LISEL/RISEL pin
1.02Vrms
1.02Vrms
1Vrms
Note: The value of Ri is over 10kΩ.
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[AK5367]
■ Charge Pump Circuit
The internal charge pump circuit generates negative voltage(CVEE) from CVDD voltage. The generated voltage is used
for Pre-Amp.
AK5367
To Pre-Amp
Charge
Pump
CVDD
CP
CN
Negative Voltage
VSS2
CVEE
Cout=1μF
Cp=0.1μF
Figure 14. Charge Pump Circuit
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[AK5367]
■ Serial Control Interface
The AK5367 supports the first-mode I2C-bus system (max: 400kHz).
The pull-up resistance of SDA,SCL pins should be connected below the voltage of DVDD+0.3V.
1. WRITE Operations
Figure 15 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 21). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant 7 bits of the slave address are fixed as “0110001”. If the slave address matches that of the
AK5367, the AK5367 generates an acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 22). A
R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK5367. The format is MSB first, and those most
significant 6-bits are fixed to zeros (Figure 17). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 18). The AK5367 generates an acknowledge after each byte is received. A data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 21).
The AK5367 can perform more than one byte write operation per sequence. The master can transmit more than one byte
instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal
2-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 02H prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will
be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 23) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
P
A
C
K
A
C
K
Figure 15. Data Transfer Sequence at the I2C-Bus Mode
0
1
1
0
0
0
1
R/W
0
A1
A0
D2
D1
D0
Figure 16. The First Byte
0
0
0
0
0
Figure 17. The Second Byte
D7
D6
D5
D4
D3
Figure 18. Byte Structure after the second byte
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[AK5367]
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK5367. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 2-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 02H prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK5367 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
2-1. CURRENT ADDRESS READ
The AK5367 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK5367 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but generates a stop condition, the
AK5367 ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 19. CURRENT ADDRESS READ
2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit “1”, the master must first perform a “dummy” write operation. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit “1”. The AK5367 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but generates a stop condition, the AK5367 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 20. RANDOM ADDRESS READ
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[AK5367]
SDA
SCL
S
P
start condition
stop condition
Figure 21. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 22. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 23. Bit Transfer on the I2C-Bus
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[AK5367]
■ Register Map
Addr
00H
01H
02H
Register Name
Power Down Control
Input Selector Control
Clock & Format Control
D7
0
0
0
D6
0
0
0
D5
0
0
0
D4
0
0
DIF
D3
0
0
CKS2
D2
0
SEL2
CKS1
D1
0
SEL1
CKS0
D0
PWN
SEL0
SMUTE
D4
0
RD
0
D3
0
RD
0
D2
0
RD
0
D1
0
RD
0
D0
PWN
R/W
1
PDN pin = “L” resets the registers to their default values.
Note: Unused bits must contain a “0” value.
Only write to address 00H to 02H.
■ Register Definitions
Addr
00H
Register Name
Power Down Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
PWN: Power down control
0: Power down. All registers are not initialized.
1: Normal Operation (default)
“0” powers down all sections and then ADC do not operate. The contents of all register are not initialized
and enabled to write to the registers.
Addr
01H
Register Name
Input Selector Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
SEL2
RD
1
D1
SEL1
R/W
0
D0
SEL0
R/W
0
D6
0
RD
0
D5
0
RD
0
D4
DIF
R/W
0
D3
CKS2
R/W
0
D2
CKS1
R/W
0
D1
CKS0
R/W
0
D0
SMUTE
R/W
0
SEL2-0: Input selector (Table 4)
Initial values are “100”.
Addr
02H
Register Name
Clock & Format Control
R/W
Default
D7
0
RD
0
SMUTE: Soft Mute control
0: Normal Operation (default)
1: SDTO outputs soft-muted.
CKS2-0: Operation mode select (Table 2)
Initial values are “000”.
DIF: Audio interface format (Table 3)
Initial values are “0” (24bit, MSB justified).
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[AK5367]
SYSTEM DESIGN
Figure 24 shows the system connection diagram. The evaluation board (AKD5367) demonstrates application circuits, the
optimum layout, power supply arrangements and measurement results.
+
2.2u
0.1u
47K
47K
47K
47K
Analog In
47K
47K
47K
47K
+
10u
24K
24K
+
10u
1
VCOM
AVDD
30
2
LIN1
VSS1
29
3
RIN1
DVDD
28
4
LIN2
LRCK
27
5
RIN2
MCLK
26
6
LIN3
7
RIN3
8
9
BICK
25
SDTO
24
LIN4
SCL
23
RIN4
SDA
22
10
RISEL
PDN
21
11
ROUT
CP
20
12
ROPIN
CN
19
13
LOPIN
CVDD
18
AK5367
14
LOUT
VSS2
17
15
LISEL
CVEE
16
Analog 5V
+
10u
0.1u
0.1u
Digital 3.3V
+ 10u
DSP or μP
Digital 3.3V
+
0.1u
0.1u
+
+
10u
Analog
Ground
Digital
Ground
1u
Figure 24. Typical Connection Diagram
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[AK5367]
1. Grounding and Power Supply Decoupling
The AK5367 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and CVDD are
usually supplied from the analog supply in the system. Alternatively if AVDD, DVDD and CVDD are supplied
separately, the power up sequence is not critical. VSS1 and VSS2 of the AK5367 must be connected to analog ground
plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto
the printed circuit board. Decoupling capacitors should be as near to the AK5367 as possible, with the small value
ceramic capacitor being the closest.
2. Voltage Reference Inputs
The differential voltage between AVDD and VSS1 sets the analog input range. VCOM is a signal common of this chip.
An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of
high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept
away from VCOM pins in order to avoid unwanted coupling into the AK5367.
3. Analog Inputs
An analog input of AK5367 is single-ended input to Pre-Amp through the external resistor. For input signal range, adjust
feedback resistor so that Pre-Amp output may become the input range (typ. 0.6 x AVDD Vpp) of ADC (LISEL,RISEL
pin). Between the Pre-Amp output (LOUT, ROUT pin) and the ADC input (LISEL,RISEL pin) is AC coupled with
capacitor. When the impedance of LISEL/RISEL pins is “R” and the capacitor of between the Pre-Amp output and the
ADC input is “C”, the cut-off frequency is fc = 1/(2πRC). The ADC output data format is 2’s compliment. The internal
HPF removes the DC offset. The AK5367 samples the analog inputs at 64fs. The digital filter rejects noise above the stop
band except for multiples of 64fs. The AK5367 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Attention to the PCB Wiring
LIN1-4 and RIN1-4 pins are the summing nodes of the Pre-Amp. Attention should be given to avoid coupling with other
signals on those nodes. This can be accomplished by making the wire length of the input resistors as short as possible. The
same theory also applies to the LOPIN/ROPIN pins and feedback resistors; keep the wire length to a minimum. Unused
input pins among LIN1-4 and RIN1-4 pins should be left open. When external devices are connected to LOUT and ROUT
pin, the input impedance is min. 15kΩ.
4. I2C bus Connection
SCL and SDA pins should be connected to DVDD through the resistor based on I2C standard. As there is a protection
between each pin and DVDD, the pulled up voltage mast be DVDD or lower(Figure 25).
+3.3V
DVDD
AK5367
SDA pin
VSS2
Figure 25. SDA pin output
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[AK5367]
PACKAGE
30pin VSOP (Unit: mm)
1.5MAX
*9.7±0.1
0.3
30
16
15
1
0.22±0.1
7.6±0.2
5.6±0.1
A
0.65
0.12 M
0.15 +0.10
-0.05
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
■ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0694-E-00
2007/12
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[AK5367]
MARKING
AKM
AK5367EF
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB : Lot number (X : Digit number, B : Alpha character)
YYYYC : Assembly date (Y : Digit number, C : Alpha character)
REVISION HISTORY
Date (YY/MM/DD)
07/12/27
Revision
00
Reason
First Edition
Page
Contents
MPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
MS0694-E-00
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