AK5366 English Datasheet

[AK5366]
AK5366
24-Bit 48kHz ΔΣ ADC with Selector/PGA/ALC
GENERAL DESCRIPTION
AK5366 is a high-performance 24-bit, 48kHz sampling ADC for consumer audio and digital recording
applications. Thanks to AKM’s Enhanced Dual-Bit modulator architecture, this analog-to-digital converter
has an impressive dynamic range of 103dB with a high level of integration. The AK5366 has a 5-channel
stereo input selector, an input Programmable Gain Amplifier with an ALC function. All this integration with
high-performance makes the AK5366 well suited for CD and DVD recording systems.
FEATURES
1. 24bit Stereo ADC
• 5ch Stereo Inputs Selector
• Input PGA from +18dB to 0dB, 0.5dB Step
• Peak Hold Function
• Auto Level Control (ALC) Circuit
• Digital HPF for offset cancellation ([email protected]=48kHz)
• Digital Attenuator from +8dB to −63dB, Mute
• Soft Mute
• Single-end Inputs
• S/(N+D) : 94dB
• DR, S/N : 103dB
• Audio I/F Format : 24bit MSB justified, I2S
2. 3-wire Serial μP Interface / I2C-Bus
3. Master / Slave Mode
4. Master Clock : 256fs/384fs/512fs
5. Sampling Rate : 32kHz to 48kHz
6. Power Supply
• AVDD: 4.75 ∼ 5.25V (typ. 5.0V)
• DVDD: 3.0 ∼ 5.25V (typ. 3.3V)
• TVDD: 3.0 ∼ 5.25V for input tolerant (typ. 5.0V)
7. Ta = −40 ∼ 85°C
8. Package : 44pin LQFP
9. AK5365 Semi-Pin Compatible
MS0309-E-01
2012/11
-1-
[AK5366]
„ Block Diagram
M/S
LOPIN
LOUT
SEL2 SEL1 SEL0
PDN
I2C
IPGAL
LIN1
AVDD
LIN2
AVSS
LIN3
DVDD
DVSS
LIN4
Pre-Amp
IPGA
(ALC)
LIN5
LRCK
HPF
DATT
RIN1
Audio I/F
Controller
ADC
BICK
MCLK
RIN2
Peak
Hold
Pre-Amp
RIN3
SDTO
TVDD
RIN4
Control Register
I/F
IPGA
(ALC)
VCOM
RIN5
ROPIN
ROUT
IPGAR
SMUTE
CSN CCLK CDTI
CAD1 SCL SDA
Block diagram
MS0309-E-01
2012/11
-2-
[AK5366]
„ Ordering Guide
−40 ∼ +85°C
44pin LQFP (0.8mm pitch)
Evaluation Board for AK5366
AK5366VQ
AKD5366
I2C
M/S
RIN1
TEST5
RIN2
TEST6
RIN3
TEST7
RIN4
TEST8
RIN5
„ Pin Layout
44 43 42 41 40 39 38 37 36 35 34
LIN5
1
33
CSN/CAD1
TEST1
2
32
CCLK/SCL
LIN4
3
31
CDTI/SDA
TEST2
4
30
SEL2
LIN3
5
29
SEL1
TEST3
6
28
SEL0
LIN2
7
27
SMUTE
TEST4
8
26
TVDD
LIN1
9
25
PDN
LOPIN
10
24
MCLK
LOUT
11
23
LRCK
AK5366VQ
Top View
MS0309-E-01
BICK
SDTO
DVDD
DVSS
VCOM
AVSS
AVDD
ROPIN
ROUT
IPGAR
IPGAL
12 13 14 15 16 17 18 19 20 21 22
2012/11
-3-
[AK5366]
„ Compatibility with AK5365
AK5365
ALC
CTRL
max. 96kHz
“0” : ALC=OFF
“89H” : +4.5dB
0dB ∼ +12dB
−72dB ∼ 0dB
No
No
100kHz
No
Pin 26
Pin 34
fs
ALC bit default value
REF7-0 bit default value
IPGA Gain
DATT Volume
MCLK AC Coupling Input
Peak Hold Circuit
I2C Speed
5V tolerant
AK5366
TVDD
I2C
max. 48kHz
“1” : ALC=ON
“8EH” : +7.0dB
0dB ∼ +18dB
−63dB ∼ +8dB
Yes
Yes
400kHz
Yes
(1) Pin Compatibility
Pin 26
Pin 34
AK5365
ALC
CTRL
AK5366
TVDD
I2C
(2) Software Compatibility
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
Register Name
Power Down & Reset Control
Input Selector Control
Clock & Format Control
Timer Select
Lch IPGA Control
Rch IPGA Control
ALC Mode Control 1
ALC Mode Control 2
Lch DATT Control
Rch DATT Control
Lch Peak Hold Low Byte
Lch Peak Hold High Byte
Rch Peak Hold Low Byte
Rch Peak Hold High Byte
D7
0
0
0
0
IPGL7
IPGR7
0
REF7
ATTL7
ATTR7
PHL7
PHL15
PHR7
PHR15
D6
0
0
0
0
IPGL6
IPGR6
0
REF6
ATTL6
ATTR6
PHL6
PHL14
PHR6
PHR14
D5
0
0
0
LTM1
IPGL5
IPGR5
ZELMN
REF5
ATTL5
ATTR5
PHL5
PHL13
PHR5
PHR13
D4
0
0
0
LTM0
IPGL4
IPGR4
ALC
REF4
ATTL7
ATTR4
PHL4
PHL12
PHR4
PHR12
D3
0
0
DIF
ZTM1
IPGL3
IPGR3
FR
REF3
ATTL7
ATTR3
PHL3
PHL11
PHR3
PHR11
D2
MCKPD
SEL2
CKS1
ZTM0
IPGL2
IPGR2
LMTH
REF2
ATTL7
ATTR2
PHL2
PHL10
PHR2
PHR10
D1
MCKAC
SEL1
CKS0
WTM1
IPGL1
IPGR1
RATT
REF1
ATTL7
ATTR1
PHL1
PHL9
PHR1
PHR9
D0
PWN
SEL0
SMUTE
WTM0
IPGL0
IPGR0
LMAT
REF0
ATTL0
ATTR0
PHL0
PHL8
PHR0
PHR8
: Changing points from AK5365’s register.
MS0309-E-01
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[AK5366]
PIN/FUNCTION
No.
1
Pin Name
LIN5
I/O
I
2
TEST1
I
3
LIN4
I
4
TEST2
I
5
LIN3
I
6
TEST3
I
7
LIN2
I
8
TEST4
I
9
10
11
12
13
14
15
16
17
LIN1
LOPIN
LOUT
IPGAL
IPGAR
ROUT
ROPIN
AVDD
AVSS
I
I
O
I
I
O
I
-
18
VCOM
O
19
20
21
22
DVSS
DVDD
SDTO
BICK
O
I/O
Function
Lch Analog Input 5 Pin
Test 1 Pin
This pin should be connected to AVSS.
Lch Analog Input 4 Pin
Test 2 Pin
This pin should be connected to AVSS.
Lch Analog Input 3 Pin
Test 3 Pin
This pin should be connected to AVSS.
Lch Analog Input 2 Pin
Test 4 Pin
This pin should be connected to AVSS.
Lch Analog Input 1 Pin
Lch Feedback Resistor Input Pin
Lch Feedback Resistor Output Pin
Lch IPGA Input Pin
Rch IPGA Input Pin
Rch Feedback Resistor Output Pin
Rch Feedback Resistor Input Pin
Analog Power Supply Pin, 4.75 ∼ 5.25V
Analog Ground Pin
Common Voltage Output Pin, AVDD/2
Bias voltage of ADC input.
Digital Ground Pin
Digital Power Supply Pin, 3.0 ∼ 5.25V
Audio Serial Data Output Pin
Audio Serial Data Clock Pin
Note: All digital input pins except pull-down pins should not be left floating.
Note: TEST1, TEST2, TEST3 and TEST4 pins should be connected to AVSS.
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[AK5366]
No.
23
24
Pin Name
LRCK
MCLK
25
PDN
I
26
TVDD
-
27
SMUTE
I
28
29
30
SEL0
SEL1
SEL2
CDTI
SDA
CCLK
SCL
CSN
CAD1
31
32
33
I/O
I/O
I
I
I
I
I
I/O
I
I
I
I
34
I2C
I
35
M/S
I
36
RIN1
I
37
TEST5
I
38
RIN2
I
39
TEST6
I
40
RIN3
I
41
TEST7
I
42
RIN4
I
43
TEST8
I
44
RIN5
I
Function
Output Channel Clock Pin
Master Clock Input Pin
Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
Input Buffer Power Supply Pin, 3.0 ∼ 5.25V
Soft Mute Pin
(Internal Pull-down Pin, typ. 100kΩ)
“H” : Soft Mute, “L” : Normal Operation
Input Selector 0 Pin
Input Selector 1 Pin
Input Selector 2 Pin
Control Data Input Pin in 3-wire Control
(I2C pin = “L”)
(I2C pin = “H”)
Control Data Input / Output Pin in I2C Control
Control Data Clock Pin in 3-wire Control
(I2C pin = “L”)
2
(I2C pin = “H”)
Control Data Clock Pin in I C Control
Chip Select Pin in 3-wire Control
(I2C pin = “L”)
(I2C pin = “H”)
Chip Address 1 Select Pin in I2C Control
Control Mode Pin
“H” : I2C Control , “L” : 3-wire Control
Master / Slave Mode Pin
“H” : Master Mode, “L” : Slave Mode
Rch Analog Input 1 Pin
Test 5 Pin
This pin should be connected to AVSS.
Rch Analog Input 2 Pin
Test 6 Pin
This pin should be connected to AVSS.
Rch Analog Input 3 Pin
Test 7 Pin
This pin should be connected to AVSS.
Rch Analog Input 4 Pin
Test 8 Pin
This pin should be connected to AVSS.
Rch Analog Input 5 Pin
Note: All digital input pins except pull-down pins should not be left floating.
Note: TEST5, TEST6, TEST7 and TEST8 pins should be connected to AVSS.
MS0309-E-01
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[AK5366]
„ Handling of Unused Pin
The unused input pins should be processed appropriately as below.
Classification
Analog
Digital
Pin Name
LIN1-5
RIN1-5
IPGAL
IPGAR
LOPIN/LOUT
ROPIN/ROUT
SMUTE
SEL2-0
CSN
CCLK/SCL
CDTI/SDA
I2C
Setting
These pins should be open.
Connected 10kΩ resistor between LOPIN pin and LOUT pin.
Connected 10kΩ resistor between ROPIN pin and ROUT pin.
These pins should be connected to DVSS.
MS0309-E-01
2012/11
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[AK5366]
ABSOLUTE MAXIMUM RATINGS
(AVSS=DVSS=0V; Note 1
Parameter
Analog
Power Supplies:
Digital
Input Buffer
(Note 2)
|AVSS – DVSS|
(Note 3)
Input Current, Any Pin Except Supplies
Analog Input Voltage
(Note 4)
(LIN1-5, RIN1-5, LOPIN, ROPIN, IPGAL, IPGAR, M/S pins)
Digital Input Voltage 1
(MCLK, BICK, LRCK, PDN pins)
Digital Input Voltage 2
(SMUTE, SEL2-0, CSN/CAD1, CCLK/SCL, CDTI/SDA,
I2C pins)
Ambient Temperature (Powered applied)
Storage Temperature
Symbol
AVDD
DVDD
TVDD
ΔGND
IIN
min
−0.3
−0.3
−0.3
-
max
6.0
6.0
6.0
0.3
±10
Unit
V
V
V
V
mA
VINA
−0.3
AVDD+0.3
V
VIND1
−0.3
DVDD+0.3
V
VIND2
−0.3
TVDD+0.3
V
Ta
Tstg
−40
−65
85
150
°C
°C
Note 1. All voltages with respect to ground.
Note 2. SMUTE, SEL2-0, CSN/CAD1, CCLK/SCL, CDTI/SDA and I2C pins correspond to 5V tolerant.
Note 3. AVSS and DVSS must be connected to the same analog ground plane.
Note 4. M/S pin is the digital input pin. However, M/S pin should be connected to AVDD or AVSS to prevent the noise
to the analog input pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS=DVSS=0V; Note 1)
Parameter
Symbol
min
typ
5.0
4.75
AVDD
Analog
Power Supplies
3.3
3.0
DVDD
Digital
(Note 5)
5.0
DVDD
TVDD
Input Buffer
max
5.25
AVDD
AVDD
Unit
V
V
V
Note 1. All voltages with respect to ground.
Note 5. The power up sequence between AVDD, DVDD and TVDD is not critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0309-E-01
2012/11
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[AK5366]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=TVDD=5.0V, DVDD=3.3V; AVSS=DVSS=0V; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=48kHz; unless otherwise specified)
Parameter
min
typ
max
Unit
Pre-Amp Characteristics:
Feedback Resistance
10
50
kΩ
S/(N+D)
(Note 6)
100
dB
S/N (A-weighted)
(Note 6)
108
dB
Load Resistance
(Note 7)
6.3
kΩ
Load Capacitance
20
pF
Input PGA Characteristics:
Input Voltage
(Note 8)
0.9
1
1.1
Vrms
Input Resistance
(Note 9)
6.3
10
15
kΩ
Step Size
0.2
0.5
0.8
dB
Gain Control Range
ALC = OFF
0
+18
dB
ALC = ON
−9.5
+18
dB
ADC Analog Input Characteristics: IPGA=0dB, ALC = OFF
(Note 10)
Resolution
24
Bits
S/(N+D)
(−0.5dBFS)
84
94
dB
DR
(−60dBFS, A-weighted)
96
103
dB
S/N
(A-weighted)
96
103
dB
Interchannel Isolation
(Note 11)
90
110
dB
Interchannel Gain Mismatch
0.2
0.5
dB
Gain Drift
100
ppm/°C
Power Supply Rejection
(Note 12)
50
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
mA
35
23
AVDD
mA
8
4
DVDD+TVDD
Power-down mode (PDN pin = “L”)
(Note 13)
μA
100
10
AVDD
μA
100
10
DVDD+TVDD
Note 6. This value is measured at LOUT and ROUT pins using the circuit as shown in Figure 25.
The input signal voltage is 2Vrms.
Note 7. This value is the input impedance of an external device that the LOUT and ROUT pins can drive, when a device
is
connected with LOUT and ROUT pin externally. The feedback resistor (min. 10kΩ) that it is usually connected
with the LOUT/ROUT pins, and the value of input impedance (min. 6.3kΩ) of the IPGAL/R pins are not
included.
Note 8. Full scale (0dB) of the input voltage at ALC=OFF and IPGA=0dB.
Input voltage to IPGAL and IPGAR pins is proportional to AVDD voltage. typ. Vin = 0.2 x AVDD (Vrms).
Note 9. This value is input impedance of the IPGAL and IPGAR pins.
Note 10. This value is measured via the following path. Pre-Amp → IPGA (Gain : 0dB) → ADC.
The measurement circuit is Figure 25.
Note 11. This value is the interchannel isolation between all the channels of the LIN1-5 and RIN1-5 when the applied
input
signal causes the Pre-Amp output to equal IPGA input.
Note 12. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp.
Note 13. All digital input pins are held DVSS.
MS0309-E-01
2012/11
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[AK5366]
FILTER CHARACTERISTICS
(Ta=−40 ∼ 85°C; AVDD=4.75 ∼ 5.25V; DVDD=TVDD=3.0 ∼ 5.25V; fs=48kHz)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 14) −0.005dB
PB
0
−0.02dB
21.768
−0.06dB
22.0
−6.0dB
24.0
Stopband
SB
26.5
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay
(Note 15)
GD
31
Group Delay Distortion
ΔGD
0
ADC Digital Filter (HPF):
Frequency Response (Note 14) −3dB
FR
1.0
−0.5dB
2.9
−0.1dB
6.5
max
Unit
21.5
-
kHz
kHz
kHz
kHz
kHz
dB
dB
1/fs
μs
±0.005
Hz
Hz
Hz
Note 14. The passband and stopband frequencies scale with fs. For example, 21.768kHz at −0.02dB is 0.454 x fs.
Note 15. The calculated delay time induced by digital filtering. This time is from the input of an analog signal
to the setting of 24bit data both channels to the ADC output register for ADC.
DC CHARACTERISTICS
(Ta=−40 ∼ 85°C; AVDD=4.75 ∼ 5.25V; DVDD=TVDD=3.0 ∼ 5.25V)
Parameter
Symbol
min
70%DVDD
VIH
High-Level Input Voltage
(Note 16)
VIL
Low-Level Input Voltage
(Note 16)
50%DVDD
VAC
Input Voltage at AC Coupling
(Note 17)
DVDD−0.5
VOH
High-Level Output Voltage
(Iout=−400μA)
Low-Level Output Voltage
VOL
(Except SDA pin : Iout=400μA)
VOL
(SDA pin : Iout=3mA)
Input Leakage Current
(Note 18)
Iin
-
typ
-
max
30%DVDD
-
Unit
V
V
V
V
-
0.5
0.4
±10
V
V
μA
Note 16. SMUTE, SEL2-0, CSN/CAD1, CCLK/SCL, CDTI/SDA and I2C pins correspond to 5V tolerant.
Note 17. When AC coupled capacitor is connected to MCLK pin.
Note 18. SMUTE pin is internally connected to a pull-down resistor. (typ. 100kΩ)
MS0309-E-01
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[AK5366]
SWITCHING CHARACTERISTICS
(Ta=−40 ∼ 85°C; AVDD=4.75 ∼ 5.25V; DVDD=TVDD=3.0 ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
8.192
fCLK
Frequency
0.3/fCLK
tCLKL
Pulse Width Low
0.3/fCLK
tCLKH
Pulse Width High
0.4/fCLK
tACW
AC Pulse Width
(Note 19)
LRCK Frequency
Frequency
fsn
32
Duty Cycle
Slave mode
45
Master mode
Audio Interface Timing
Slave mode
160
tBCK
BICK Period
65
tBCKL
BICK Pulse Width Low
65
tBCKH
Pulse Width High
30
tLRB
LRCK Edge to BICK “↑”
(Note 20)
30
tBLR
BICK “↑” to LRCK Edge
(Note 20)
2
tLRS
LRCK to SDTO (MSB) (Except I S mode)
tBSD
BICK “↓” to SDTO
Master mode
fBCK
BICK Frequency
dBCK
BICK Duty
−20
tMBLR
BICK “↓” to LRCK
−20
tBSD
BICK “↓” to SDTO
typ
max
Unit
24.576
MHz
ns
ns
ns
48
55
kHz
%
%
50
35
35
ns
ns
ns
ns
ns
ns
ns
20
35
Hz
%
ns
ns
64fs
50
Note 19. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
ground.
Note 20. BICK rising edge must not occur at the same time as LRCK edge.
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[AK5366]
Parameter
Control Interface Timing (3-wire Serial mode):
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 21)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width
PDN “↑” to SDTO valid
CSN “↑” to SDTO valid
(Note 22)
(Note 23)
(Note 24)
Symbol
min
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
tPD
tPDV
tPDV
150
typ
max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
400
0.3
0.3
50
516
516
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
ns
1/fs
1/fs
Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 22. The AK5366 can be reset by bringing the PDN pin = “L”.
Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Note 24. This cycle is the number of LRCK rising edges from the CSN = “H”.
MS0309-E-01
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[AK5366]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
1/fCLK
tACW
1000pF
MCLK Input
tACW
Measurement Point
100kΩ
AGND
VAC
AGND
MCLK AC Coupling Timing (Measurement condition)
*Refer to Figure 2 for input circuit example.
MS0309-E-01
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[AK5366]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
SDTO
50%DVDD
Audio Interface Timing (Slave mode)
50%DVDD
LRCK
tMBLR
dBCK
BICK
50%DVDD
tBSD
SDTO
50%DVDD
Audio Interface Timing (Master mode)
VIH
CSN
VIL
tCCKL
tCSS
tCCKH
VIH
CCLK
VIL
tCDS
tCDH
VIH
CDTI
C1
C0
R/W
VIL
WRITE Command Input Timing
MS0309-E-01
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[AK5366]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D2
D1
D0
VIL
WRITE Data Input Timing
VIH
SDA
VIL
tBUF
tLOW
tHIGH
tR
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
Start
tSU:STO
Start
Stop
2
I C Bus Mode Timing
VIH
CSN
VIL
tPDV
SDTO
50%DVDD
VIH
PDN
VIL
tPDV
SDTO
50%DVDD
tPD
PDN
VIL
Power Down & Reset Timing
MS0309-E-01
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[AK5366]
OPERATION OVERVIEW
„ System Clock
MCLK (256fs/384fs/512fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must
be synchronized with MCLK, however the phase is not critical. MCLK frequency is automatically detected in slave mode.
Table 1 shows the relationship of typical sampling frequency and the system clock frequency. Setting of CKS 1-0 bit is
ignored.
MCLK (256fs/384fs/512fs) is required in master mode. MCLK frequency is selected by CKS1-0 bits as shown in Table 2.
In master mode, after setting CKS1-0 bits, there is a possibility the frequency and duty of LRCK and BICK outputs
become an abnormal state.
All external clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L” and PWN bit = “1”. If these clocks
are not provided, the AK5366 may draw excess current due to its use of internal dynamically refreshed logic. If the
external clocks are not present, place the AK5366 in power-down mode (PDN pin = “L” or PWN bit = “0”). In master
mode, the master clock (MCLK) must be provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
MCLK
256fs
384fs
512fs
8.192MHz
12.288MHz
16.384MHz
11.2896MHz
16.9344MHz
22.5792MHz
12.288MHz
18.432MHz
24.576MHz
Table 1. System clock example (Slave mode)
CKS1
CKS0
MCLK
0
0
256fs
Default
0
1
512fs
1
0
384fs
1
1
N/A
Table 2. Master clock frequency select (Master mode)
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[AK5366]
[MCLK AC Coupling input]
MCLK AC coupling input becomes possible by controlling MCKPD bit and MCKAC bit.
Master Clock
External Clock Direct Input
Status
MCKAC bit
Clock is input to MCLK pin.
0
Clock isn’t input to MCLK pin.
0
AC Coupling Input
(Figure 2)
Clock is input to MCLK pin.
1
Clock isn’t input to MCLK pin.
1
Table 3. MCKPD bit and MCKAC bit setting for Master Clock Status
(Figure 1)
MCKPD bit
0
Don’t care
0
1
(1) External clock direct input
MCLK
MCKAC = "0"
MCKPD = "0"
External
Clock
AK5366
Figure 1. External Master Clock Input Block
(2) AC coupling input
C
MCLK
MCKAC = "1"
MCKPD = "0"
External
Clock
AK5366
Figure 2. External Clock mode (Input : ≥ 50%DVDD, Input circuit example)
- Note: This clock level must not exceed DVDD level. (C : 0.1μF)
„ Audio Interface Format
Two kinds of data formats can be chosen with the DIF bit (Table 4). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of BICK. The audio interface supports both master and
slave modes. In master mode, BICK and LRCK are output with the BICK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
DIF bit
0
0
1
1
SDTO
LRCK
BICK
≥ 48fs (Slave)
24bit, MSB justified
H/L
64fs (Master)
≥ 48fs (Slave)
2
24bit, I S Compatible
L/H
64fs (Master)
Table 4. Audio Interface Format
MS0309-E-01
Figure
Figure 3
Default
Figure 4
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[AK5366]
LRCK
0 1 2
20 21 22 23 24
31 0 1 2
20 21 22 23 24
31 0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 0 Timing
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 1 Timing
„ Master Mode and Slave Mode
The M/S pin selects either master or slave mode. M/S pin = “H” selects master mode and “L” selects slave mode. The
AK5366 outputs BICK and LRCK in master mode. In slave mode, MCLK, BICK and LRCK are input externally.
BICK, LRCK
BICK = Input
Slave Mode
LRCK = Input
BICK = Output
Master Mode
LRCK = Output
Table 5. Master mode/Slave mode
„ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz) and scales with sampling rate (fs).
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[AK5366]
„ Power-up/down
The AK5366 is placed in the power-down mode by bringing PDN pin = “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down
mode. Therefore, the output data SDTO becomes available after 516 cycles of LRCK.
Power Supply
PDN pin
ADC Internal State
150ns
PDN
INITA
Normal
ALC bit
“1”
“0”
ALC Function
ON
OFF
Unknown
(1)
IPGA
SDTO
External clocks
in slave mode
Output
“0”
MCLK, BICK, LRCK Input
The clocks can be stopped.
External clocks
MCLK Input
in master mode
BICK, LRCK
in master mode
BICK, LRCK Output
Fixed to “L”
• PDN : Power down state.
• INITA : Initializing period of ADC analog section (516/fs).
• (1) : After ALC operation is disabled, the IPGA changes to the last written data during or before ALC operation.
Figure 5. Power-up Sequence
„ Peak Hold Circuit
The AK5366 includes the peak hold circuit. The peak is held L/R audio data independently. These registers are reset by
reading 8bit of MSB, reading 8bit of both MSB and LSB should be continuity controlled by reading in order of 8bit of
MSB from LSB. After reading 8bit of LSB the last, 8bit of MSB is lost by reading 8bit of LSB the last. The output value
is the absolute value. Full scale is “FFFFH”.
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[AK5366]
„ Input Selector
The AK5366 includes 5ch stereo input selectors (Figure 6). The input selector is 5 to 1 selector. The input channel is set
by the SEL2-0 bits (Table 6) and the SEL2-0 pins (Table 7). The SEL2-0 pins should be fixed to “LLL” if the AK5366 is
controlled by the SEL 2-0 bits, because the setting of the SEL2-0 pins are prior to the SEL2-0 bits setting.
SEL2 bit
0
0
0
0
1
SEL1 bit
SEL0 bit
Input Channel
0
0
LIN1 / RIN1
0
1
LIN2 / RIN2
1
0
LIN3 / RIN3
1
1
LIN4 / RIN4
0
0
LIN5 / RIN5
Table 6. Input Selector (SEL2-0 pin = “LLL”)
SEL2 pin
L
L
L
L
H
SEL1 pin
SEL0 pin
Input Channel
L
L
LIN1 / RIN1
L
H
LIN2 / RIN2
H
L
LIN3 / RIN3
H
H
LIN4 / RIN4
L
L
LIN5 / RIN5
Table 7. Input Selector (SEL2-0 bit = “000”)
Default
LIN1
LIN2
LIN3
LIN4
Pre-Amp
LIN5
RIN1
RIN2
Pre-Amp
RIN3
RIN4
RIN5
Figure 6. Input Selector
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[AK5366]
[Input selector switching sequence]
The input selector should be changed after soft mute to avoid the switching noise of the input selector (Figure 7).
1. Enable the soft mute before changing channel.
2. Change channel.
3. Disable the soft mute.
SMUTE
D AT T Level
(1)
(1)
A ttenuation
(2)
-∞
C hannel
LIN 1/R IN 1
LIN 2/R IN 2
Figure 7. Input channel switching sequence example
The period of (1) varies in the setting value of DATT. It takes 1028/fs to mute when DATT value is +8dB.
When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms
because there is some DC difference between the channels.
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[AK5366]
„ Input Attenuator
The input ATTs are constructed by adding the input resistor (Ri) for LIN1-5/RIN1-5 pins and the feedback resistor (Rf)
between LOPIN (ROPIN) pin and LOUT (ROUT) pin (Figure 8). The input voltage range of the IPGAL/IPGAR pin is
typically typ. 0.2 x AVDD (Vrms). If the input voltage of the input selector exceeds typ. 0.2 x AVDD, the input voltage of
the IPGAL/IPGAR pins must be attenuated to 0.2 x AVDD by the input ATTs. Table 8 shows the example of Ri and Rf.
Rf
LOPIN
Ri
LIN1
Ri
LIN2
Ri
LIN3
Ri
LIN4
Ri
LIN5
Ri
RIN1
Ri
RIN2
Ri
RIN3
Ri
RIN4
Ri
RIN5
LOUT
IPGAL
To IPGA
Pre-Amp
Pre-Amp
To IPGA
ROPIN
ROUT
IPGAR
Rf
Figure 8. Input ATT
• Example for input range
Input Range
4Vrms
2Vrms
1Vrms
Ri [kΩ]
47
47
47
ATT Gain [dB]
Rf [kΩ]
12
−11.86
24
−5.84
47
0
Table 8. Input ATT example
MS0309-E-01
IPGAL/R pin
1.02Vrms
1.02Vrms
1Vrms
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[AK5366]
„ Input Volume
The AK5366 includes two independent channel analog volumes (IPGA) with 37 levels at 0.5dB steps located in front of
the ADC.
The IPGA is a true analog volume control that improves the S/N ratio as seen in Table 9. Independent zero-crossing
detection is used to ensure level changes only occur during zero-crossings. If there are no zero-crossings, the level will
then change after a time-out period (Table 10); the time-out period scales with fs. If a new value is written to the IPGA
register before the IPGA changes at the zero crossing or time-out, the previous value becomes invalid. The timer (channel
independent) for time-out is reset and the timer restarts for new IPGA value.
Input Gain Setting
0dB
+6dB
fs=48kHz, A-weight
103dB
100dB
Table 9. PGA+ADC S/N
ZTM1
0
0
1
1
ZTM0
0
1
0
1
+18dB
89dB
Zero crossing timeout period
@fs=48kHz
288/fs
6ms
1152/fs
24ms
2304/fs
48ms
4608/fs
96ms
Table 10. Zero crossing timeout period
Default
[Writing operation at ALC Enable]
Writing to the area over 7FH (Table 17) of IPGL/R registers (04H, 05H) is ignored during ALC operation. After ALC
is disabled, the IPGA changes to the last written data by zero-crossing or time-out. In case of writing to the DATT area
(08H, 09H), the DATT changes even if ALC is enabled.
„ Output Volume
The AK5366 includes two independent channel digital volumes (DATT) with 144 levels at 0.5dB steps located behind
the ADC. When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these
transitions. The data must not be written over 90H.
ATTL/R7-0 Attenuation
8FH
+8.0dB
8EH
+7.5dB
:
:
81H
+1.0dB
80H
+0.5dB
7FH
0dB
Default
7EH
−0.5dB
7DH
−1.0dB
:
:
02H
−62.5dB
01H
−63dB
00H
Mute (−∝)
Table 11. DATT Code Table
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[AK5366]
„ ALC Operation
[1] ALC Limiter Operation
When the ALC limiter is enabled, and either Lch or Rch exceed the ALC limiter detection level (LMTH bit), the IPGA
value is attenuated by the amount defined in the ALC limiter ATT step (LMAT bit) automatically. Then the IPGA value
is changed commonly for L/R channels.
When the ZELMN bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done
continuously until the input signal level becomes the ALC limiter detection level (LMTH bit) or less. If the ALC bit does
not change into “0” or the ALC pin does not change into “L” after completing the attenuation, the attenuation operation
repeats until the input signal level equals or exceeds the ALC limiter detection level (LMTH bit).
When the ZELMN bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation
function so that the IPGA value is attenuated at the zero-detect points of the waveform.
When FR bit = “1”, the ALC operation corresponds to the impulse noise in additional to the normal ALC operation. Then
if the impulse noise is supplied at ZELMN bit = “0”, the ALC operation becomes the faster period than a set of ZTM1-0
bits. In case of ZELMN bit = “1”, it becomes the same period as LTM1-0 bits. When FR bit = “0”, the ALC operation is
the normal ALC operation.
[2] ALC Recovery Operation
The ALC recovery refers to the amount of time that the AK5366 will allow a signal to exceed a predetermined limiting
value prior to enabling the limiting function. The ALC recovery operation uses the WTM1-0 bits to define the wait period
used after completing an ALC limiter operation. If the input signal does not exceed the “ALC Recovery Waiting Counter
Reset Level”, the ALC recovery operation starts. The IPGA value increases automatically during this operation up to the
reference level (REF7-0 bits). The ALC recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is
detected during WTM1-0, the ALC recovery operation waits WTM1-0 period and the next recovery operation starts.
During the ALC recovery operation, when input signal level exceeds the ALC limiter detection level (LMTH bit), the
ALC recovery operation changes immediately into an ALC limiter operation.
In the case of “(Recovery waiting counter reset level) ≤ Input Signal < Limiter detection level” during the ALC recovery
operation, the wait timer for the ALC recovery operation is reset. Therefore, in the case of “(Recovery waiting counter
reset level) > Input Signal”, the wait timer for the ALC recovery operation starts.
When the impulse noise is input at FR bit = “1”, the ALC recovery operation becomes faster than a normal recovery
operation. When the FR bit = “0”, the ALC recovery operation is done by normal period.
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[AK5366]
[3] ALC Level Diagram
(1) ALC=OFF
Figure 9 and 10 show the level diagram example at ALC=OFF. In Figure 9, Input ATT is −12dB.
Input
ATT
IPGA
ADC
-12dB
4Vrms
-12dB
2Vrms
-12dB
1Vrms
0dBFS
+6dB
-12dB
+12dB
Figure 9. ALC Level diagram example (ALC=OFF)
In Figure 10, Input ATT is −6dB.
Input
ATT
IPGA
ADC
-6dB
2Vrms
-6dB
1Vrms
0dBFS
-6dB
+6dB
0.5Vrms
-6dB
+12dB
Figure 10. ALC Level diagram example (ALC=OFF)
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[AK5366]
(2) ALC=ON
Figure 11 and 12 show the level diagram example at ALC=ON. In Figure 11, Input ATT is −12dB and REF7-0 bits are
“8CH”.
Input
ATT
ALC
ADC
-12dB
4Vrms
-12dB
2Vrms
-12dB
1Vrms
0dBFS
-0.5dBFS
-0.5dB
+5.5dB
0.5Vrms
-6dBFS
-12dB
+6dB
0.25Vrms
-12dBFS
Figure 11. ALC Level diagram example (ALC=ON, LMTH bit=“0”)
In Figure 12, Input ATT is −6dB and REF7-0 bits are “8CH”.
Input
ATT
ALC
ADC
-6dB
2Vrms
-6dB
1Vrms
0dBFS
-0.5dBFS
-0.5dB
-6dB
+5.5dB
0.5Vrms
-6dBFS
-6dB
+6dB
0.25Vrms
-12dBFS
Figure 12. ALC Level diagram example (ALC=ON, LMTH=“0”)
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[AK5366]
[4] Example of ALC Operation
The following registers should not be changed during the ALC operation.
• LTM1-0, LMTH, LMAT, WTM1-0, ZTM1-0, RATT, REF7-0, ZELMN bits
• The IPGA value of Lch becomes the start value if the IPGA value is different with Lch and Rch when the ALC starts.
• Writing to the area over 80H (Table 17) of IPGL/R registers (04H, 05H) is ignored during ALC operation.
After ALC is disabled, the IPGA changes to the last written data by zero-crossing or time-out. In case of writing to
the
DATT area (Table 11) of DATT registers (08H, 09H), the DATT changes even if ALC is enabled.
PDN = “L” → “H”
ALC Operation
ALC OFF (WR: ALC = “0”)
Manual Mode
Set (SEL2-0 bits or SEL2-0 pins)
WR (ZTM1-0, WTM1-0, LTM1-0)
WR (LMAT, RATT, LMTH)
WR (REF7-0)
WR (IPGA7-0)
(1)
WR (ALC = “1”)
(2)
ALC Operation
No
Finish ALC mode?
(1)
Yes
WR (ALC = “0”)
(2)
Finish ALC mode and return to manual mode
Note : WR : Write
Figure 13. Registers set-up sequence at ALC operation
(1): Enable soft mute
(2): Disable soft mute
Note : After ALC operation is disabled, the IPGA changes to the last written data during or before ALC operation.
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[AK5366]
[5] IPGA value before and after ALC operation
After ALC operation is disabled, the IPGA changes to the last written data during or before ALC operation.
[Operation Example 1]
1. Set IPGA = +12dB at ALC=OFF. DATT portion is set to 0dB internally.
2. ALC=ON after soft mute is enabled.
3. Disable the soft mute.
4. During ALC operation. The IPGA changes from −9.5dB to the value set by REF7-0 bits.
5. ALC=OFF after soft mute is enabled.
6. Disable the soft mute. The IPGA return to +12dB automatically.
[Operation Example 2]
1. Set IPGA = +12dB at ALC=OFF. DATT portion is set to 0dB internally.
2. ALC=ON after soft mute is enabled.
3. Disable the soft mute.
4. During ALC operation. When the DATT portion is set to −10dB, the IPGA changes from −19.5dB to the value set
by REF7-0 bits.
5. ALC=OFF after soft mute is enabled.
6. Disable the soft mute. The IPGA setting is −10dB.
„ Soft Mute Operation
Soft mute operation is performed in the digital domain of the ADC output.
Soft mute can be controlled by SMUTE bit or SMUTE pin. The SMUTE bit and SMUTE pin are ORed between pin and
register. When SMUTE bit goes “1” or SMUTE pin goes “H”, the ADC output data is attenuated by −∞ within 1028
LRCK cycles. When the SMUTE bit returned “0” and SMUTE pin goes “L” the mute is cancelled and the output
attenuation gradually changes to DATT value within 1028 LRCK cycles. If the soft mute is cancelled before mute state
after starting of the operation, the attenuation is discontinued and returned to DATT value.
Soft mute function and digital volume are common.
SMUTE
D AT T Level
(1)
(3)
A ttenuation
-∞
GD
(2)
GD
SDTO
Figure 14. Soft Mute Function
(1) The output signal is attenuated by −∞ within 1028 LRCK cycles (1028/fs).
(2) Digital output delay from the analog input is called the group delay (GD).
(3) If the soft mute is cancelled before the mute, the attenuation is discontinued and returned to DATT value.
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[AK5366]
„ Chip Address
In case of 3-wire control mode, the chip address is fixed to C1 bit = “1” and C0 bit = “0”. Table 12 shows the relationship
between chip address (C1-0 bits) and CAD1 pin in I2C-bus control mode.
CAD1 pin
C1 bit
C0 bit
L
0
Fixed to “1”
H
1
Fixed to “1”
2
Table 12. Chip address in I C-bus control
Note : C1 bit should match with the input level of CAD1 pin.
„ Serial Control Interface
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of a Chip address (2bits, Fixed to “10”), Read/Write (1bit, Fixed to “1”, Write only), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. After a low-to-high transition of CSN, data is latched for write operations. The clock speed of
CCLK is 5MHz (max). The value of internal registers is initialized at PDN pin = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C1
C0
R/W
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CCLK
CDTI
C1 - C0 : Chip Address (C1="1", C0="0")
R/W :
READ / WRITE (Fixed to "1" : WRITE only)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 15. Serial Control I/F Timing
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[AK5366]
(2) I2C-bus Control Mode (CTRL pin = “H”)
The AK5366 supports the standard-mode and the first-mode I2C-bus system (max: 400kHz).
(2)-1. WRITE Operations
Figure 16 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 22). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next one bit are CAD1 (device
address bits). This one bit identify the specific device on the bus. The hard-wired input pin (CAD1 pin) set these device
address bits (Figure 17). If the slave address matches that of the AK5366, the AK5366 generates an acknowledge and the
operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH)
during the acknowledge clock pulse (Figure 23). A R/W bit value of “1” indicates that the read operation is to be
executed. A “0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK5366. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 18). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 19). The AK5366 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 22).
The AK5366 can perform more than one byte write operation per sequence. After receipt of the third byte the AK5366
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 5-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 0DH prior to
generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 24) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 16. Data Transfer Sequence at the I2C-Bus Mode
0
0
1
0
0
CAD1
1
R/W
A2
A1
A0
D2
D1
D0
(CAD1 should match with CAD1 pin.)
Figure 17. The First Byte
0
0
0
A4
A3
Figure 18. The Second Byte
D7
D6
D5
D4
D3
Figure 19. Byte Structure after the second byte
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[AK5366]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK5366. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 5-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 0DH prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The AK5366 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK5366 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) were to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK5366 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge to the data but instead generates a stop condition,
the AK5366 ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
A
C
K
Data(n+1)
Data(n+2)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 20. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation. The master issues a start request, a
slave address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit set to “1”. The AK5366 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge to the data but instead generates a stop condition, the AK5366 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Slave
S Address
Slave
S Address
Sub
Address(n)
A
C
K
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 21. RANDOM ADDRESS READ
MS0309-E-01
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[AK5366]
SDA
SCL
S
P
start condition
stop condition
Figure 22. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 23. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 24. Bit Transfer on the I2C-Bus
MS0309-E-01
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[AK5366]
„ Control by Pin and Bit
Function
Input Selector
Soft Mute
Pin
bit
SEL2-0 Pin
“LLL” : LIN1/RIN1
“LLH” : LIN2/RIN2
“LHL” : LIN3/RIN3
“LHH” : LIN4/RIN4
“HLL” : LIN5/RIN5
SMUTE Pin
(Internal Pull-down)
“L” : Normal operation
“H” : Soft muted
Table 13. Pin and Bit control
SEL2-0 bit
“000” : LIN1/RIN1
“001” : LIN2/RIN2
“010” : LIN3/RIN3
“011” : LIN4/RIN4
“100” : LIN5/RIN5
SMUTE bit
“0” : Normal operation
“1” : Soft muted
Note : The SEL2-0 pins should be fixed to “LLL” if the AK5366 is controlled by the SEL2-0 bits, because the setting of
the
SEL2-0 pins are prior to the SEL2-0 bits setting. Soft Mute is ORed between pin and register.
„ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
Register Name
Power Down & Reset Control
Input Selector Control
Clock & Format Control
Timer Select
Lch IPGA Control
Rch IPGA Control
ALC Mode Control 1
ALC Mode Control 2
Lch DATT Control
Rch DATT Control
Lch Peak Hold Low Byte
Lch Peak Hold High Byte
Rch Peak Hold Low Byte
Rch Peak Hold High Byte
D7
0
0
0
0
IPGL7
IPGR7
0
REF7
ATTL7
ATTR7
PHL7
PHL15
PHR7
PHR15
D6
0
0
0
0
IPGL6
IPGR6
0
REF6
ATTL6
ATTR6
PHL6
PHL14
PHR6
PHR14
D5
0
0
0
LTM1
IPGL5
IPGR5
ZELMN
REF5
ATTL5
ATTR5
PHL5
PHL13
PHR5
PHR13
D4
0
0
0
LTM0
IPGL4
IPGR4
ALC
REF4
ATTL7
ATTR4
PHL4
PHL12
PHR4
PHR12
D3
0
0
DIF
ZTM1
IPGL3
IPGR3
FR
REF3
ATTL7
ATTR3
PHL3
PHL11
PHR3
PHR11
D2
MCKPD
SEL2
CKS1
ZTM0
IPGL2
IPGR2
LMTH
REF2
ATTL7
ATTR2
PHL2
PHL10
PHR2
PHR10
D1
MCKAC
SEL1
CKS0
WTM1
IPGL1
IPGR1
RATT
REF1
ATTL7
ATTR1
PHL1
PHL9
PHR1
PHR9
D0
PWN
SEL0
SMUTE
WTM0
IPGL0
IPGR0
LMAT
REF0
ATTL0
ATTR0
PHL0
PHL8
PHR0
PHR8
PDN pin = “L” resets the registers to their default values.
Note: Unused bits must contain a “0” value.
Note: Only write to address 00H to 09H.
Note: 3-wire serial control does not support Read function. I2C control supports Read function.
MS0309-E-01
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[AK5366]
„ Register Definitions
Addr
00H
Register Name
Power Down & Reset Control
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
MCKPD
R/W
0
D1
MCKAC
R/W
0
D0
PWN
R/W
1
PWN: Power down control
0 : Power down. All registers are not initialized.
1 : Normal Operation (Default)
“0” powers down all sections and then both IPGA and ADC do not operate. The contents of all register
are not initialized and enabled to write to the registers.
When MCLK and LRCK are changed, it is not necessary to reset by the PDN pin or PWN bit because the
AK5366 builds in reset-free circuit. However, it can be reduced the noise by reset.
MCKAC: Master Clock input Mode Select
0 : CMOS input (Default)
1 : AC coupling input
MCKPD: MCLK Input Buffer Control
0 : Enable (Default)
1 : Disable
When MCLK input with AC coupling is stopped, MCKPD bit should be set to “1”.
Addr
01H
Register Name
Input Selector Control
R/W
Default
SEL2-0:
Addr
02H
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
SEL2
R/W
0
D1
SEL1
R/W
0
D0
SEL0
R/W
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
DIF
R/W
0
D2
CKS1
R/W
0
D1
CKS0
R/W
0
D0
SMUTE
R/W
0
Input selector (see Table 6)
Initial values are “000”.
Register Name
Clock & Format Control
R/W
Default
D7
0
RD
0
SMUTE: Soft Mute control
0 : Normal Operation (Default)
1 : SDTO outputs soft-muted.
CKS1-0: Master clock frequency select (see Table 2)
Initial values are “00”.
DIF:
Audio interface format (see Table 4)
Initial values are “0” (24bit, MSB first).
MS0309-E-01
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[AK5366]
Addr
03H
Register Name
Timer Select
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
LTM1
R/W
1
D4
LTM0
R/W
0
D3
ZTM1
R/W
1
D2
ZTM0
R/W
0
D1
WTM1
R/W
1
D0
WTM0
R/W
1
WTM1-0: ALC Recovery waiting time (see Table 14)
A period of recovery operation when any limiter operation does not occur during the ALC operation.
WTM1
0
0
1
1
WTM0
0
1
0
1
ALC recovery operation waiting period
288/fs
1152/fs
2304/fs
4608/fs
Table 14. ALC recovery waiting time
@fs=48kHz
6ms
24ms
48ms
96ms
Default
ZTM1-0: Zero crossing timeout (see Table 15)
When the IPGA of each L/R channels perform zero crossing or timeout independently, the IPGA value is
changed by the μP WRITE operation, ALC recovery operation or ALC limiter operation (ZELMN bit = “0”).
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero crossing timeout period
@fs=48kHz
288/fs
6ms
1152/fs
24ms
2304/fs
48ms
4608/fs
96ms
Table 15. Zero crossing timeout
Default
LTM1-0: ALC Limiter period (see Table 16)
When ZELMN bit = “1”, the IPGA value is changed immediately. When the IPGA value is changed
continuously, the change is done by the period set by the LTM1-0 bits.
LTM1
0
0
1
1
LTM0
0
1
0
1
ALC limiter operation period
3/fs
6/fs
12/fs
24/fs
Table 16. ALC limiter period
MS0309-E-01
@fs=48kHz
63μs
125μs
Default
250μs
500μs
2012/11
- 35 -
[AK5366]
Addr
04H
05H
Register Name
Lch IPGA Control
Rch IPGA Control
R/W
Default
D7
IPGL7
IPGR7
R/W
1
D6
IPGL6
IPGR6
R/W
0
D5
IPGL5
IPGR5
R/W
0
D4
IPGL4
IPGR4
R/W
0
D3
IPGL3
IPGR3
R/W
0
D2
IPGL2
IPGR2
R/W
0
D1
IPGL1
IPGR1
R/W
0
D0
IPGL0
IPGR0
R/W
0
IPGL/R7-0: Input PGA & Digital volume control (see Table 17)
Initial values are “80H”.
The data must not be written under 80H.
Writing to the area over 7FH (Table 17) of IPGL/R registers (04H, 05H) is ignored during ALC operation. After
ALC is disabled, the IPGA changes to the last written data by zero-crossing or time-out. In case of writing to the
DATT area (Table 11) of DATT registers (08H, 09H), the DATT changes even if ALC is enabled.
Data (hex)
A4H
:
9EH
:
98H
97H
96H
:
82H
81H
80H
Gain (dB)
+18
:
+15
:
+12
+11.5
+11
:
+1.0
+0.5
0
Step width (dB)
0.5
0.5
0.5
0.5
IPGA
0.5
0.5
Analog volume with 0.5dB step
0.5
0.5
0.5
0.5
Table 17. IPGA Code Table
MS0309-E-01
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[AK5366]
Addr
06H
Register Name
ALC Mode Control 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
ZELMN
R/W
1
D4
ALC
R/W
0
D3
FR
R/W
1
D2
LMTH
R/W
0
D1
RATT
R/W
0
D0
LMAT
R/W
0
LMAT: ALC Limiter ATT step (see Table 18)
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level set by LMTH
bit, the number of steps attenuated from the current IPGA value is set. For example, when the current IPGA value
is 94H and the LMAT bit = “1”, the IPGA transition to 92H when the ALC limiter operation starts, resulting in
the input signal level being attenuated by 1dB (=0.5dB x 2).
LMAT
ATT Step
0
1
Default
1
2
Table 18. ALC limiter ATT step
RATT: ALC Recovery gain step (see Table 19)
During the ALC recovery operation, the number of steps changed from the current IPGA value is set. For
example, when the current IPGA value is 82H and RATT bit = “1” is set, the IPGA changes to 84H by the ALC
recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value exceeds
the reference level (REF7-0 bits), the IPGA value does not increase.
RATT
Gain Step
0
1
Default
1
2
Table 19. ALC recovery gain step
LMTH: ALC Limiter detection level / Recovery waiting counter reset level (see Table 20)
The ALC limiter detection level and the ALC recovery counter reset level may be offset by about ±2dB.
LMTH
0
1
ALC Limiter Detection Level
ALC Recovery Waiting Counter Reset Level
ALC Output ≥ −0.5dBFS
−0.5dBFS > ALC Output ≥ −2.5dBFS
ALC Output ≥ −2.0dBFS
−2.0dBFS > ALC Output ≥ −4.0dBFS
Table 20. ALC Limiter detection level / Recovery waiting counter reset level
Default
FR: ALC fast recovery
0 : Disable
1 : Enable (Default)
When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation.
ALC:
ALC enable flag
0 : ALC Disable (Default)
1 : ALC Enable
ZELMN: Zero crossing enable flag at ALC limiter operation
0 : Enable
1 : Disable (Default)
When the ZELMN bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently.
The zero crossing timeout is the same as the ALC recovery operation. When the ZELMN bit = “1”, the IPGA
value is changed immediately. The ALC Limiter period can be set up by a ZTM 1-0 bits when ZELMN bit = “0”,
it can be set up by a LTM1-0 bits when ZELMN bit = “1”
MS0309-E-01
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[AK5366]
Addr
07H
Register Name
ALC Mode Control 2
R/W
Default
D7
REF7
R/W
1
D6
REF6
R/W
0
D5
REF5
R/W
0
D4
REF4
R/W
0
D3
REF3
R/W
1
D2
REF2
R/W
1
D1
REF1
R/W
1
D0
REF0
R/W
0
REF7-0: Reference value at ALC recovery operation (see Table 21)
During the ALC recovery operation, if the IPGA value exceeds the setting reference value by gain operation,
then the IPGA does not become larger than the reference value.
The REF7-0 bits should not be set up except for Table 21.
DATA (hex)
Gain (dB)
A4H
+18.0
:
:
90H
+8.0
8FH
+7.5
8EH
+7.0
Default
8DH
+6.5
:
:
89H
+4.5
:
:
81H
+0.5
80H
0
Table 21. Reference value at ALC recovery operation
Addr
08H
09H
Register Name
Lch DATT Control
Rch DATT Control
R/W
Default
D7
ATTL7
ATTR7
R/W
0
D6
ATTL6
ATTR6
R/W
1
D5
ATTL5
ATTR5
R/W
1
D4
ATTL4
ATTR4
R/W
1
D3
ATTL3
ATTR3
R/W
1
D2
ATTL2
ATTR2
R/W
1
D1
ATTL1
ATTR1
R/W
1
D0
ATTL0
ATTR0
R/W
1
D3
PHL3
PHL11
PHR3
PHR11
D2
PHL2
PHL10
PHR2
PHR10
D1
PHL1
PHL9
PHR1
PHR9
D0
PHL0
PHL8
PHR0
PHR8
0
0
0
0
ATTL/R7-0: Digital output volume control (see Table 11)
Initial value is “7FH”.
The data must not be written over 90H.
When PDN pin = “L”, ATTL/R7-0 bits are initialized “7FH”.
When PWN bit = “0”, the DATT holds the last setting value.
Addr
0AH
0BH
0CH
0DH
Register Name
Lch Peak Hold Low Byte
Lch Peak Hold High Byte
Rch Peak Hold Low Byte
Rch Peak Hold High Byte
R/W
Default
D7
PHL7
PHL15
PHR7
PHR15
D6
PHL6
PHL14
PHR6
PHR14
D5
PHL5
PHL13
PHR5
PHR13
0
0
0
D4
PHL4
PHL12
PHR4
PHR12
RD
0
PHL15-0: Lch Peak Hold Low/High Byte
PHR15-0: Rch Peak Hold Low/High Byte
The AK5366 includes the peak hold circuit. The peak is held L/R audio data independently. These
registers are reset by reading 8bit of MSB, reading 8bit of both MSB and LSB should be continuity
controlled by reading in order of 8bit of MSB from LSB. After reading 8bit of LSB the last, 8bit of MSB
is lost by reading 8bit of LSB the last. The output value is the absolute value. Full scale is “FFFFH”.
These registers are reset by PDN pin = “L” or PWN bit = “0”.
MS0309-E-01
2012/11
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[AK5366]
SYSTEM DESIGN
Figure 25 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
• Master Mode, 3-wire control (I2C pin = “L”)
43
42
41
40
39
38
37
36
35
TEST6
RIN2
TEST5
RIN1
M/S
47k
1μ
34
I2C
44
RIN3
1μ
47k
TEST7
1μ
47k
RIN4
1μ
47k
TEST8
1μ
47k
RIN5
1μ
1μ
47k
1 LIN5
CSN/CAD1 33
2 TEST1
CCLK/SCL 32
3 LIN4
CDTI/SDA 31
47k
4 TEST2
1μ
SEL2 30
47k
Top View
5 LIN3
6 TEST3
1μ
47k
SEL1 29
DSP and uP
SEL0 28
7 LIN2
SMUTE 27
10
8 TEST4
1μ
TVDD 26
47k
9 LIN1
PDN 25
10 LOPIN
MCLK 24
11 LOUT
LRCK 23
0.1μ
Reset
IPGAR
ROUT
ROPIN
AVDD
AVSS
VCOM
DVSS
DVDD
SDTO
BICK
4.7μ
IPGAL
24k
12
13
14
15
16
17
18
19
20
21
22
4.7μ
24k
0.1μ 0.1μ
0.1μ
10μ
10μ
Analog Supply
4.75 ~ 5.25V
2.2μ
Digital Supply
3.0 ~ 5.25V
Note:
- AVSS and DVSS of the AK5366 should be distributed separately from the ground of external digital devices
(MPU, DSP etc.).
- When LOUT/ROUT drives a capacitive load, resistors should be added in series between LOUT/ROUT
and capacitive load.
- All digital input pins should not be left floating.
- M/S pin should be connected to AVDD or AVSS.
Figure 25. Typical Connection Diagram
MS0309-E-01
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[AK5366]
1. Grounding and Power Supply Decoupling
The AK5366 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and TVDD are
usually supplied from the analog supply in the system. Alternatively if AVDD, DVDD and TVDD are supplied
separately, the power up sequence is not critical. AVSS and DVSS of the AK5366 must be connected to analog
ground plane. System analog ground and digital ground should be connected together near to where the supplies are
brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5366 as possible, with the small
value ceramic capacitor being the closest.
2. Voltage Reference Inputs
The differential voltage between AVDD and AVSS sets the analog input range. VCOM is a signal ground of this chip. An
electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high
frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away
from the VREF and VCOM pins in order to avoid unwanted coupling into the AK5366.
3. Analog Inputs
An analog input of AK5366 is single-ended input to Pre-Amp through the external resistor. For input signal range, adjust
feedback resistor so that Pre-Amp output may become the input range (typ. 0.2 x AVDD Vrms) of IPGA (IPGAL, IPGAR
pin). Between the Pre-Amp output (LOUT, ROUT pin) and the IPGA input (IPGAL, IPGAR pin) is AC coupled with
capacitor. When the impedance of IPGAL/R pins is “R” and the capacitor of between the Pre-Amp output and the IPGA
input is “C”, the cut-off frequency is fc = 1/(2πRC).
The ADC output data format 2’s compliment. The internal HPF removes the DC offset.
The AK5366 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK5366 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
4. Attention to the PCB Wiring
LIN1-5 and RIN1-5 pins are the summing nodes of the Pre-Amp. Attention should be given to avoid coupling with other
signals on those nodes. This can be accomplished by making the wire length of the input resistors as short as possible. The
same theory also applies to the LOPIN/ROPIN pins and feedback resistors; keep the wire length to a minimum. Unused
input pins among LIN1-5 and RIN1-5 pins should be left open.
When external devices are connected to LOUT and ROUT pin, the input impedance of an external device which the
LOUT and ROUT pins can drive is min 6.3kΩ.
MS0309-E-01
2012/11
- 40 -
[AK5366]
PACKAGE
44pin LQFP (Unit: mm)
1.70max
12.0
0 ~ 0.2
10.0
23
33
0.80
12.0
22
10.0
34
12
44
1
11
0.09 ~ 0.20
0.37±0.10
0°∼10°
0.60±0.20
0.15
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0309-E-01
2012/11
- 41 -
[AK5366]
MARKING
AKM
AK5366VQ
XXXXXXX
1
XXXXXXX :
Date Code Identifier (7 digits)
REVISION HISTORY
Date (YY/MM/DD)
04/05/25
12/11/20
Revision
00
01
Reason
First Edition
Specification
Change
Page
Contents
41
PACKAGE
Package dimensions were changed.
MS0309-E-01
2012/11
- 42 -
[AK5366]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
MS0309-E-01
2012/11
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