AKM AK4686EQ

[AK4686]
AK4686
Multi-channel CODEC with Capless Stereo Selector
GENERAL DESCRIPTION
The AK4686 is a single chip audio CODEC that includes one stereo ADC and two stereo DACs in addition
to the input selector and the line drivers. The interfaces of ADC/DAC can accept up to 24bit input data and
support asynchronous operation. Both the input stereo selector and output drivers support ground
reference I/O to remove AC-coupling capacitors and reducing external parts. The AK4686 has a dynamic
range of 96dB for ADC, 100dB for DAC, and it is well suitable for digital TV and Home theater systems.
FEATURES
† Asynchronous Operation between Port 1(ADC and DAC1) and Port 2 (DAC2)
† 6:1 Capless Stereo Line Input Selector
† 24bit Stereo ADC
- 64x Oversampling
- Sampling Rate up to 48kHz
- Linear Phase Digital Anti-Alias Filter
- S/(N+D): 88dB
- Dynamic Range, S/N: 96dB
- Digital HPF for Offset Cancellation
† 24bit Two Stereo DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- S/(N+D): 88dB
- Dynamic Range, S/N: 100dB
- De-emphasis Filter
- Analog Soft Mute
† High Jitter Tolerance
† TTL Level Digital I/F
† External Master Clock Input:
256fs, 384fs, 512fs 768fs (fs=32kHz ∼ 48kHz)
128fs, 192fs, 256fs 384fs (fs=64kHz ∼ 96kHz)
128fs, 192fs (fs=128kHz ~ 192kHz)
† 2 Audio Serial I/F (PORT1, PORT2)
- Master/Slave mode (PORT1)
- I/F format
PORT2: MSB, LSB justified (16/24 bit), I2S
PORT1: MSB, LSB justified (16/24 bit), I2S
2
† I C Bus μP I/F for mode setting
† Operating Voltage:
- Digital I/O: 3.0V ∼ 3.6V
- Charge Pump: 3.0V ∼ 3.6V
- Analog: 3.0V ∼ 3.6V
† Package: 48pinLQFP
MS1243-E-01
2010/10
-1-
[AK4686]
2Vrms
PWAD bit
LIN1
LIN2
LIN3
LIN4
LIN5
LIN6
PORT1
2ch
ADC
MCLK1
BICK1
LRCK1
SDTO1
SDTI1
MS1
HPF
RIN1
RIN2
RIN3
RIN4
RIN5
RIN6
Serial
I/F
PWDA1 bit
2Vrms
2ch
DAC
LOUT1
ROUT1
PWAD bit or PWDA1 bit
CVEE
CP
CN
Control
Charge
Pump
I/F
PDN pin
Analog Soft Mute
SDA
SCL
MT1N
MT2N
PDN
Analog Soft Mute
PWDA2 bit
PORT2
LOUT2
2ch
DAC
Serial
I/F
ROUT2
AVDD1
VSS1
CVDD
VSS2
AVDD2
VSS3
DVDD
VSS4
CAD1
MCLK2
BICK2
LRCK2
SDTI2
CAD0
AK4686 Block Diagram
MS1243-E-01
2010/10
-2-
[AK4686]
■ Ordering Guide
AK4686EQ
AKD4686
-20 ∼ +85°C
48pin LQFP (0.5mm pitch)
Evaluation Board for the AK4686
MT2N
MS1
SDTI1
MCLK1
MT1N
DVD D
VSS4
SDTO
LRCK1
BICK1
SD A
SCL
■ Pin Layout
36 3 5 34 33 32 31 30 29 2 8 27 2 6 2 5
LIN1
37
24
NC
RIN1
38
23
BICK2
NC
39
22
MCL K2
LIN2
40
21
LRC K2
RIN2
41
20
SDTI2
NC
42
19
PDN
LIN3
43
18
CVDD
RIN3
44
17
CP
NC
45
16
VSS3
LIN4
46
15
CN
RIN4
47
14
CVEE
NC
48
13
VSS2
AK4686EQ
RIN5
NC
LIN6
RIN6
AVDD1
7
8
9
1 0 11 12
MS1243-E-01
AVDD2
6
ROUT2
5
LOUT2
4
ROUT1
3
LOUT1
2
VSS1
1
LIN5
Top Vie w
2010/10
-3-
[AK4686]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Pin Name
LIN5
RIN5
NC
LIN6
RIN6
AVDD1
VSS1
LOUT1
ROUT1
LOUT2
ROUT2
AVDD2
VSS2
CVEE
CN
VSS3
CP
CVDD
I/O
I
I
I
I
O
O
O
O
O
I
I
-
19
PDN
I
20
21
22
23
24
SDTI2
LRCK2
MCLK2
BICK2
NC
I
I
I
I
-
25
MT2N
I
26
MS1
I
27
28
SDTI1
MCLK1
I
I
29
MT1N
I
30
31
32
33
34
35
36
37
38
39
40
41
42
DVDD
VSS4
SDTO
LRCK1
BICK1
SDA
SCL
LIN1
RIN1
NC
LIN2
RIN2
NC
O
I/O
I/O
I/O
I
I
I
I
I
-
Function
Lch Input 5 Pin
Rch Input 5 Pin
This pin must be connected to the ground.
Lch Input 6 Pin
Rch Input 6 Pin
ADC&DAC1 Analog Power Supply Pin, 3.0V∼3.6V
ADC&DAC1 Analog Ground Pin, 0V
Lch Analog Output Pin1
Rch Analog Output Pin1
Lch Analog Output Pin2
Rch Analog Output Pin2
DAC2 Analog Power Supply Pin, 3.3V∼3.6V
DAC2 Analog Ground Pin, 0V
Charge Pump Circuit Negative Voltage Output Pin (for Analog Input/Output)
Negative Charge Pump Capacitor Terminal Pin (for Analog Input/Output)
Charge Pump Circuit Analog Ground Pin, 0V (for Analog Input/Output)
Positive Charge Pump Capacitor Terminal Pin (for Analog Input/Output)
Charge Pump Circuit Positive Power Supply Pin 3.0V∼3.6V (for Analog Input/Output)
Power-Down Mode & Reset Pin
When “L”, the AK4686 is powered-down, all registers are reset. And then all digital
output pins go “L”. The AK4686 must be reset once upon power-up.
Audio Serial Data Input Pin (for PORT2)
Input Channel Clock Pin (for PORT2)
DAC2 Master Clock Input Pin (for PORT2)
Audio Serial Data Clock Pin (for PORT2)
This pin must be connected to the ground.
DAC2 Mute Pin
“H”: Normal Operation
“L”: Mute
PORT1 Master Mode Select Pin.
“L”(connected to the ground): Slave mode.
“H”(connected to DVDD) : Master mode.
Audio Serial Data Input Pin (for PORT1)
ADC&DAC1 Master Clock Input Pin (for PORT1)
DAC1 Mute Pin
“H”: Normal Operation
“L”: Mute
Digital Power Supply Pin, 3.0V∼3.6V
Digital Ground Pin, 0V
Audio Serial Data Output 1 Pin (for PORT1)
Channel Clock 1 Pin (for PORT1)
Audio Serial Data Clock 1 Pin (for PORT1)
Control Data Pin
Control Data Clock Pin
Lch Input 1 Pin
Rch Input 1 Pin
This pin must be connected to the ground.
Lch Input 2 Pin
Rch Input 2 Pin
This pin must be connected to the ground.
MS1243-E-01
2010/10
-4-
[AK4686]
PIN/FUNCTION (Continued)
No.
Pin Name I/O
Function
43
LIN3
I
Lch Input 3 Pin
44
RIN3
I
Rch Input 3 Pin
45
NC
This pin must be connected to the ground.
46
LIN4
I
Lch Input 4 Pin
47
RIN4
I
Rch Input 4 Pin
48
NC
This pin must be connected to the ground.
Note: All digital input pins must not be left floating.
■ Handling of Unused Pin
The unused I/O pins must be processed appropriately as below.
Classification
Analog
Digital
-
Pin Name
LOUT1-2, ROUT1-2, LIN1-6, RIN1-6
SDTO1, LRCK1(Master), BICK1(Master)
MCLK1-2, LRCK1(Slave), LRCK2, BICK1(Slave),
BICK2, SDTI1-2, MS1, CAD0
Setting
These pins must be open.
These pins must be open.
These pins must be connected to VSS4.
SDA, SCL, MT1N, MT2N
These pins must be pulled-up to DVDD.
NC
These pins should be connected to the ground.
MS1243-E-01
2010/10
-5-
[AK4686]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=VSS3=VSS4 =0V; Note 1)
Parameter
Symbol
min
Power Supply
DVDD
-0.3
AVDD1
-0.3
AVDD2
-0.3
CVDD
-0.3
Input Current (any pins except for supplies)
IIN
Digital Input Voltage
VIND
-0.3
(MCLK1-2, PDN, LRCK1-2, BICK1-2,
SDTI1-2, SDA, SCL, MS1, CAD0, MT1N and
MT2N pins)
Analog Input Voltage
VINA
-0.3
(LIN1-6, RIN1-6 pins)
Ambient Operating Temperature
Ta
-20
Storage Temperature
Tstg
-65
Note 1. VSS1, VSS2, VSS3 and VSS4 must be connected to the same analog ground plane.
max
4.0
4.0
4.0
4.0
±10
DVDD+0.3
Units
V
V
V
V
mA
V
AVDD1+0.3
V
85
150
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=VSS3=VSS4= 0V; Note 1)
Parameter
Symbol
min
typ
max
Units
Power Supply (Note 2)
DVDD
3.0
3.3
3.6
V
AVDD1
3.0
3.3
3.6
V
AVDD2
3.0
3.3
3.6
V
CVDD
3.0
3.3
3.6
V
Note 2. The AVDD1, AVDD2 and CVDD must be the same voltage.
The voltage difference between DVDD and other voltages (AVDD1, AVDD2 and CVDD) must be less than 0.3V.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1243-E-01
2010/10
-6-
[AK4686]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD1=AVDD2= CVDD = DVDD= 3.3V; VSS1=VSS2= VSS3=VSS4=0V; fs=48kHz; BICK=64fs; Signal
Frequency=1kHz; 24bit Data; Measurement Frequency = 20Hz∼ 20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz;
20Hz~40kHz at fs=192kHz, all blocks are synchronized, unless otherwise specified)
Parameter
min
typ
max
Units
Input Impedance
12
16.4
kΩ
Analog Input (LIN1-6, RIN1-6pin) to ADC Analog Input Characteristics
Resolution
24
Bits
S/(N+D)
(-1dBFS)
fs=48kHz
75
88
dB
DR
(-60dBFS)
fs=48kHz, A-weighted
88
96
dB
S/N
(input off)
fs=48kHz, A-weighted
88
96
dB
Interchannel Isolation
(Note 3)
90
100
dB
Interchannel Gain Mismatch
0
0.6
dB
Gain Drift
50
ppm/°C
Input Voltage
AIN= 2.2 x AVDD1/3.3
2
2.2
2.4
Vrms
Power Supply Rejection
(Note 4)
50
dB
DAC to Analog Output (LOUT1-2, ROUT1-2 pin) Characteristics
Resolution
24
Bits
S/(N+D)
(0dBFS)
fs=48kHz
76
88
dB
fs=96kHz
84
dB
fs=192kHz
84
dB
DR
(-60dBFS)
fs=48kHz, A-weighted
94
100
dB
fs=96kHz
96
dB
fs=96kHz, A-weighted
100
dB
fs=192kHz
96
dB
fs=192kHz, A-weighted
100
dB
S/N
(“0” data)
fs=48kHz, A-weighted
94
100
dB
fs=96kHz
96
dB
fs=96kHz, A-weighted
100
dB
fs=192kHz
96
dB
fs=192kHz, A-weighted
100
dB
Interchannel Isolation
90
100
dB
Interchannel Gain Mismatch
0
0.5
dB
Gain Drift
50
ppm/°C
Output Voltage
AOUT= 2 x AVDD1(AVDD2)/3.3
1.90
2
2.15
Vrms
Load Resistance
(AC Load)
5
kΩ
Load Capacitance
(C1)
30
pF
Load Resistance
(R1)
446.5
470
Ω
Load Capacitance
(C2)
1
1.5
nF
Power Supply Rejection
(Note 4)
50
dB
Note 3. This value is the channel isolation for all other channels when inputting full scale signal to one channel.
Note 4. PSR is applied to AVDD1, AVDD2, DVDD and CVDD with 1kHz, 50mVpp.
LOUT/ROUT1,2 pin
R1
C1
Analog
Out
C2
Figure 1. Lineout Circuit Example
MS1243-E-01
2010/10
-7-
[AK4686]
Power Supplies
Parameter
Power Supply Current
Normal Operation (PDN pin = “H”)
DVDD+AVDD1+AVDD2
CVDD
Power-Down Mode (PDN pin = “L”; Note 5)
DVDD+AVDD1+AVDD2+CVDD
min
typ
max
Units
26
8
34
13
mA
mA
10
100
μA
Note 5. All digital inputs including clock pins (MCLK1-2, BICK1-2, LRCK1-2 and SDTI1-2) are held at DVDD or
VSS4.
FILTER CHARACTERISTICS
(Ta=-20°C ~+85°C; AVDD1=AVDD2= CVDD = DVDD= 3.3V; fs=48kHz)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
Passband
(Note 6)
PB
0
18.5
kHz
±0.1dB
19.9
kHz
-0.2dB
22.9
kHz
-3.0dB
Stopband
SB
27.9
kHz
Stopband Attenuation
SA
61
dB
Group Delay
(Note 7)
GD
15.7
1/fs
Group Delay Distortion
0
µs
ΔGD
ADC Digital Filter (HPF):
Frequency Response (Note 6)
-3dB
FR
1.0
Hz
-0.1dB
6.5
Hz
DAC Digital Filter:
Passband
(Note 6)
-0.1dB
PB
0
21.8
kHz
-6.0dB
24.0
kHz
Stopband
SB
26.2
kHz
Passband Ripple
PR
dB
±0.02
Stopband Attenuation
SA
54
dB
Group Delay
(Note 7)
GD
19
1/fs
DAC Digital Filter + Analog Filter:
FR
dB
Frequency Response: 0 ∼ 20.0kHz
±0.2
FR
dB
40.0kHz (Note 8)
±0.3
FR
dB
80.0kHz (Note 8)
±1.0
Note 6. The passband and stopband frequencies scale with fs.
For example, 21.8kHz at –0.1dB is 0.454 x fs (DAC). The reference frequency of these responses is 1kHz.
Note 7. The calculating delay time occurred at digital filtering. This time is from setting the input of analog signal to
setting the 24bit data of both channels to the output register of PORT1.
For DAC, this time is from setting the 20/24bit data of both channels on input register of PORT2 to the output of
analog signal.
Note 8. [email protected]=96kHz, [email protected]=192kHz.
MS1243-E-01
2010/10
-8-
[AK4686]
DC CHARACTERISTICS
(Ta=-20°C ~+85°C; AVDD1=AVDD2=CVDD = DVDD= 3.3V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage ( Iout=-400μA)
VOH
DVDD-0.4
Low-Level Output Voltage
VOL
(Iout= -400μA(except SDA pin), 3mA(SDA pin))
Iin
Input Leakage Current
-
typ
-
max
30%DVDD
0.4
Units
V
V
V
V
-
±10
μA
SWITCHING CHARACTERISTICS
(Ta=-20°C ~+85°C; AVDD1=AVDD2=CVDD = DVDD= 3.3V; CL= 20pF (except for SDA pin), Cb=400pF(SDA pin))
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fECLK
8.192
36.864
MHz
Duty
dECLK
40
50
60
%
Master Clock
256fsn, 128fsd:
fCLK
8.192
12.288
MHz
Pulse Width Low
tCLKL
27
ns
Pulse Width High
tCLKH
27
ns
384fsn, 192fsd:
fCLK
12.288
18.432
MHz
Pulse Width Low
tCLKL
20
ns
Pulse Width High
tCLKH
20
ns
512fsn, 256fsd, 128fsq:
fCLK
16.384
24.576
MHz
Pulse Width Low
tCLKL
15
ns
Pulse Width High
tCLKH
15
ns
768fsn, 384fsd, 192fsq:
fCLK
24.576
36.864
MHz
Pulse Width Low
tCLKL
10
ns
Pulse Width High
tCLKH
10
ns
LRCK1/2Timing (Slave Mode)
Normal mode
Normal Speed Mode
fsn
32
48
kHz
Double Speed Mode
fsd
64
96
kHz
Quad Speed Mode
fsq
128
192
kHz
Duty Cycle
Duty
45
55
%
LRCK1 Timing (Master Mode)
Normal mode
Normal Speed Mode
fsn
32
48
kHz
Double Speed Mode
fsd
64
96
kHz
Quad Speed Mode
fsq
128
192
kHz
Duty Cycle
Duty
50
%
Power-down & Reset Timing
PDN Pulse Width
(Note 9)
tPD
150
ns
PDN “↑” to SDTO1 valid (Note 10)
tPDV
296
1/fs
Note 9. The AK4686 can be reset by bringing the PDN pin = “L”.
Note 10. After a rising edge of PDN, the internal counter starts by divided clock of MCLK and ADC power down is
released by a falling edge of CVEE after 256/fs on LRCK, then SDTO1 is output 40/fs later.
MS1243-E-01
2010/10
-9-
[AK4686]
Parameter
Symbol
min
Audio Interface Timing (Slave Mode)
PORT1(DAC1), PORT2 (DAC2)
BICK1, 2 Period
tBCK
81
BICK1, 2 Pulse Width Low
tBCKL
32
Pulse Width High
tBCKH
32
LRCK1, 2 Edge to BICK1, 2 “↑” (Note 11)
tLRB
20
BICK1, 2 “↑” to LRCK1, 2 Edge (Note 11)
tBLR
20
SDTI1, 2 Hold Time
tSDH
10
SDTI1, 2 Setup Time
tSDS
10
PORT1 (ADC)
BICK1 Period
tBCK
324
BICK1 Pulse Width Low
tBCKL
128
Pulse Width High
tBCKH
128
LRCK1 Edge to BICK1 “↑” (Note 11)
tLRB
80
BICK1 “↑” to LRCK1 Edge (Note 11)
tBLR
80
LRCK1 to SDTO1 (MSB)
tLRS
BICK1 “↓” to SDTO1
tBSD
Audio Interface Timing (Master Mode)
BICK1 Frequency
fBCK
BICK1 Duty
dBCK
BICK1 “↓” to LRCK1 Edge
tMBLR
-20
BICK1 “↓” to SDTO1
tBSD
SDTI1 Hold Time
tSDH
25
SDTI1 Setup Time
tSDS
10
2
Control Interface Timing (I C Bus):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time
tHD:STA
0.6
(prior to first clock pulse)
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 12)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
Capacitive load on bus
Cb
0
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 13. I2C-bus is a trademark of NXP B.V.
MS1243-E-01
typ
max
Units
ns
ns
ns
ns
ns
ns
ns
80
80
64fs
50
ns
ns
ns
ns
ns
ns
ns
20
20
Hz
%
ns
ns
ns
ns
400
-
kHz
μs
μs
0.3
0.3
50
400
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
2010/10
- 10 -
[AK4686]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fsn, 1/fsd, 1/fsq
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing (Normal mode)
VIH
LRCK
VIL
tBLR
tLRB
tLRS
VIH
BICK
VIL
tBSD
50% TVDD
SDTO
tSDS
tSDH
VIH
SDTI
VIL
Audio Interface Timing
LRCK= LRCK1, LRCK2
BICK= BICK1, BICK2
SDTI= SDTI1/2
SDTO= SDTO1.
MS1243-E-01
2010/10
- 11 -
[AK4686]
LRCK
50% TVDD
tMBLR
50% TVDD
BICK
tBSD
50% TVDD
SDTO
Audio Interface timing (Master Mode)
tPD
VIH
PDN
VIL
tPDV
50% TVDD
SDTO
Power Down & Reset Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
I2C Bus mode Timing
MS1243-E-01
2010/10
- 12 -
[AK4686]
OPERATION OVERVIEW
■ System Clock
The AK4686 has two audio serial interfaces (PORT1 and PORT2) which can be operated asynchronously. At each PORT,
the external clocks, which are required to operate the AK4686, are MCLK1 (MCLK2), LRCK1 (LRCK2) and BICK1
(BICK2). The MCLK1 (MCLK2) must be synchronized with LRCK1 (LRCK2) but the phase is not critical. The PORT2
is an audio data interfaces for DAC2, the PORT1 is for ADC and DAC1.
The AK4686 is automatically powered down, then the ADC output becomes “0” data and DAC output is pulled down
(VSS) when MCLK1 (MCLK2) is stopped more than 2µs or BICK1 or LRCK1 (BICK2 or LRCK2) are stopped more
than 1024*MCLK cycles during an operation (PDN pin = “H”). The power down state is released when MCLK1, BICK1
and LRCK1 (MCLK2, BICK2 and LRCK2) are input and the AK4686 starts an operation. When reset is released (PDN
pin = “L” → “H”), such as when power up the device, the AK4686 is in power down state until MCLK1 (MCLK2) is
input.
The AK4686 is reset automatically and the phase is synchronized by a phase detection circuit when internal timings are
unsynchronized by clock change during an operation.
■ Master/Slave Mode
The MS1 pin controls master/slave mode of the PORT1. The PORT2 supports slave mode only. In master mode, LRCK1
pin and BICK1 pin are output pins. In slave mode, LRCK1, LRCK2 pins and BICK1, BICK2 pins are input pins (Table 1).
PDN pin
MS1 pin
L
L
H
PORT1 (ADC, DAC1)
BICK1, LRCK1
Input (slave mode)
Output “L”(master mode)
PORT2 (DAC2)
BICK2, LRCK2
Input (slave mode)
Input (slave mode)
Table 1. Master/Salve Mode
MS1243-E-01
2010/10
- 13 -
[AK4686]
■ PORT1 (ADC, DAC1) Clock Control
In master mode (MS1 pin = “H”), the CKS12-0 bits select the clock frequency (Table 2). The external clock (MCLK1)
must always be supplied except in power-down mode (PDN pin = “L” or PWAD bit, PWDA1 bit = “0”). The ADC is in
power-down mode until MCLK1 is supplied.
CKS12
CKS11
CKS10
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
Sampling Speed (fs)
Normal or Double
Normal or Double
Normal
Normal
Double or Quad
Double or Quad
32kHz~48kHz, 64kHz~96kHz
32kHz~48kHz, 64kHz~96kHz
32kHz~48kHz
32kHz~48kHz
64kHz~96kHz, 128kHz~192kHz
64kHz~96kHz, 128kHz~192kHz
X
Master Clock
Speed
256fs
384fs
512fs
768fs
128fs
192fs
N/A
(default)
Table 2. PORT1(ADC, DAC1) Master Clock Control (Master Mode)
In slave mode (MS1 pin = “L”), external clocks (MCLK1, BICK1, LRCK1) must always be present whenever the ADC is
in normal operation mode (PDN pin = “H” or PWAD bit = PWDA1 bit = “1”). The master clock (MCLK1) must be
synchronized with LRCK1 but the phase is not critical. If these clocks are not provided, the ADC may draw excess current
because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC and DAC1
must be in power-down mode (PDN pin = “L” or PWAD bit = PWDA1 bit = “0”) or in reset mode (RSTN bit = “0”). After
exiting reset at power-up and etc., ADC is in power-down mode until MCLK1 and LRCK1 are input.
There are two modes for controlling the sampling speed of ADC and DAC1. One is Manual Setting Mode (ACKS1 bit =
“0”) using the DFS11-10 bits, and the other is Auto Setting Mode (ACKS1 bit = “1”). The ADC only supports Normal
Speed Mode, and it is powered-down in Double Speed Mode and Quad Speed Mode.
1. Manual Setting Mode (ACKS1 bit = “0”)
When the ACKS1 bit = “0”, ADC and DAC1 is in Manual Setting Mode and the sampling speed is selected by DFS11-10
bits (Table 3).
DFS11
DFS10
ADC Sampling Speed (fs)
Normal Speed
32kHz~48kHz
Mode
0
0
0
1
Power down
1
0
Power down
1
1
DAC1 Sampling Speed (fs)
Normal Speed
32kHz~48kHz
Mode
Double Speed
64kHz~96kHz
Mode
Quad Speed
128kHz~192kHz
Mode
Not Available
(default)
Table 3. PORT1(ADC, DAC1) Sampling Speed (ACKS1bit = “0”, Manual Setting Mode)
LRCK1
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK1 (MHz)
384fs
512fs
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
768fs
24.5760
33.8688
36.8640
BICK1 (MHz)
64fs
2.0480
2.8224
3.0720
Table 4. ADC, DAC1 System Clock Example (ADC, DAC1 Normal Speed Mode @Manual Setting Mode)
MS1243-E-01
2010/10
- 14 -
[AK4686]
LRCK1
fs
88.2kHz
96.0kHz
128fs
11.2896
12.2880
MCLK1 (MHz)
192fs
256fs
16.9344
22.5792
18.4320
24.5760
384fs
33.8688
36.8640
BICK1 (MHz)
64fs
5.6448
6.1440
Table 5. DAC1 System Clock Example (DAC1 Double Speed Mode @Manual Setting Mode)
LRCK1
fs
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLK1 (MHz)
192fs
256fs
33.8688
36.8640
-
384fs
-
BICK1 (MHz)
64fs
11.2896
12.2880
Table 6. DAC1 System Clock Example (DAC1 Quad Speed Mode @Manual Setting Mode)
2. Auto Setting Mode (ACKS1 bit = “1”)
When the ACKS1 bit = “1”, ADC and DAC1 are in Auto Setting Mode and the sampling speed is selected automatically
by the ratio of MCLK1/LRCK1, as shown in the Table 7 and the internal master clock is set to the appropriate frequency
(Table 8). The ADC only supports Normal Speed Mode, and it is powered-down in Double Speed Mode and Quad Speed
Mode. In this mode, the settings of DFS11-10 bits are ignored. (Table 5, Table 6)
MCLK1
512fs, 768fs
256fs, 384fs
128fs, 192fs
LRCK1
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
ADC Sampling Speed
Normal Speed Mode
Power down
Power down
DAC Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Table 7. PORT1(ADC,DAC1) Sampling Speed (ACKS1 bit = “1”, Auto Setting Mode)
LRCK1
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
192fs
MCLK1 (MHz)
256fs
384fs
22.5792 33.8688
24.5760 36.8640
22.5792 33.8688
24.5760 36.8640
-
512fs
768fs
ADC
Sampling
Speed
DAC1
Sampling
Speed
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Normal
Normal
-
-
Power down
Double
Power down
Quad
Table 8. PORT1 (ADC, DAC1) System Clock Example (Auto Setting Mode)
MS1243-E-01
2010/10
- 15 -
[AK4686]
■ PORT2 (DAC2) Clock Control
External clocks (MCLK2, BICK2 and LRCK2) must always be present whenever the DAC is in normal operation mode
(PDN pin = “H” or PWDA2 bit= “1”). The master clock MCLK2 must be synchronized with LRCK2 but the phase is not
critical. If these clocks are not provided, the DAC may draw excess current because the device utilizes dynamic refreshed
logic internally. If the external clocks are not present, the DAC must be in power-down mode (PDN pin = “L” or PWDA2
bit = “0”) or in reset mode (RSTN bit = “0”). After exiting reset at power-up and etc., the DAC is in power-down mode
until MCLK2 and LRCK2 are input.
There are two modes for controlling the sampling speed of DAC2. One is the Manual Setting Mode (ACKS2 bit = “0”)
using the DFS21-20 bits, and the other is Auto Setting Mode (ACKS2 bit = “1”).
1. Manual Setting Mode (ACKS2 bit = “0”)
When the ACKS2 bit = “0”, DAC2 is in Manual Setting Mode and the sampling speed is selected by DFS21-20 bits
(Table 9).
DFS21
0
0
1
1
DFS20
0
1
0
1
DAC2 Sampling Speed (fs)
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
128kHz~192kHz
Not Available
-
(default)
Table 9. PORT2(DAC2) Sampling Speed (ACKS2 bit = “0”, Manual Setting Mode)
LRCK2
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920
11.2896
12.2880
MCLK2 (MHz)
384fs
512fs
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
768fs
24.5760
33.8688
36.8640
BICK2 (MHz)
64fs
2.0480
2.8224
3.0720
Table 10. DAC2 System Clock Example (DAC Normal Speed Mode @Manual Setting Mode)
LRCK2
fs
88.2kHz
96.0kHz
128fs
11.2896
12.2880
MCLK2 (MHz)
192fs
256fs
16.9344
22.5792
18.4320
24.5760
384fs
33.8688
36.8640
BICK2 (MHz)
64fs
5.6448
6.1440
Table 11. DAC2 System Clock Example (DAC Double Speed Mode @Manual Setting Mode)
LRCK2
Fs
176.4kHz
192.0kHz
128fs
22.5792
24.5760
MCLK2 (MHz)
192fs
256fs
33.8688
36.8640
-
384fs
-
BICK2 (MHz)
64fs
11.2896
12.2880
Table 12. DAC2 System Clock Example (DAC Quad Speed Mode @Manual Setting Mode)
MS1243-E-01
2010/10
- 16 -
[AK4686]
2. Auto Setting Mode (ACKS2 bit = “1”)
When the ACKS2 bit = “1”, DAC2 is in Auto Setting Mode and the sampling speed is selected automatically by the ratio
of MCLK2/LRCK2, as shown in the Table 13 and the internal master clock is set to the appropriate frequency (Table 14).
In this mode, the settings of DFS1-0 bits are ignored.
MCLK2
512fs, 768fs
256fs, 384fs
128fs, 192fs
DAC Sampling Speed (fs) LRCK2
Normal Speed Mode
32kHz~48kHz
Double Speed Mode
64kHz~96kHz
Quad Speed Mode
128kHz~192kHz
Table 13. PORT2(DAC2) Sampling Speed (ACKS2 bit = “1”, Auto Setting Mode)
LRCK2
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
MCLK2 (MHz)
256fs
384fs
22.5792
33.8688
24.5760
36.8640
-
512fs
16.3840
22.5792
24.5760
-
768fs
24.5760
33.8688
36.8640
-
Sampling
Speed
Normal
Double
Quad
Table 14. PORT2 (DAC2) System Clock Example (Auto Setting Mode)
■ De-emphasis Filter
The AK4686 includes a digital de-emphasis filter (tc=50/15μs) by IIR filter. This filter corresponds to three sampling
frequencies (32kHz, 44.1kHz, 48kHz). De-emphasis filter is off in Double speed mode and Quad speed mode. Deemphasis of each DAC can be set individually by registers.
Mode
0
1
2
3
DEM11
(DEM21)
0
0
1
1
DEM10
(DEM20)
0
1
0
1
DEM
44.1kHz
OFF
48kHz
32kHz
(default)
Table 15. De-emphasis Control
■ ADC Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz
and scales with sampling rate (fs).
MS1243-E-01
2010/10
- 17 -
[AK4686]
■ Audio Serial Interface Format
Each PORT1/2 can select independent audio interface format. The DIF11-10 bits control the audio format for PORT1.
The DIF21-20 bits control the audio format for PORT2. In all modes the serial data is MSB-first, 2’s complement format.
The SDTO1 pin is clocked out on the falling edge of BICK1 pin and the SDTI1-2 pins are latched on the rising edge of
BICK1-2 pins.
1. PORT1(ADC,DAC1) Setting
The MS1 pin and DIF11-10 bits select following four serial data formats (Table 16).
Mode
0
1
2
3
4
5
6
7
BICK1
speed
I/O
≥ 48fs or
0
0
0
24/16bit, L J
16bit, R J
H/L
I
I
32fs
0
0
1
24bit, L J
24bit, R J
H/L
I
I
≥ 48fs
0
1
0
24bit, L J
24bit, L J
H/L
I
I
≥ 48fs
2
2
0
1
1
24bit, I S
24bit, I S
L/H
I
I
(default)
≥ 48fs
1
0
0
24bit, L J
16bit, R J
H/L
O
64fs
O
1
0
1
24bit, L J
24bit, R J
H/L
O
64fs
O
1
1
0
24bit, L J
24bit, L J
H/L
O
64fs
O
1
1
1
24bit, I2S
24bit, I2S
L/H
O
64fs
O
(default)
Table 16. Audio Interface Format (Normal mode, x: Don’t care, L J: Left justified, R J: Right justified.)
MS1
pin
DIF11
bit
DIF10
bit
SDTO
LRCK1
L/R
I/O
SDTI1
2. PORT2(DAC2) Setting
The DIF21-20 bits select following four serial data formats (Table 17).
LRCK2
L/R
I/O
Mode
DIF21
bit
DIF20
bit
SDTI2
0
0
0
16bit, Right justified
1
2
3
0
1
1
1
0
1
24bit, Right justified
H/L
I
24bit, Left justified
H/L
I
24bit, I2S
L/H
I
Table 17. Audio Interface Format
MS1243-E-01
H/L
I
BICK2
speed
I/O
≥ 48fs
I
or 32fs
I
≥ 48fs
I
≥ 48fs
I
≥ 48fs
(default)
2010/10
- 18 -
[AK4686]
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
SDTI(i)
12 11 10
Don’t Care
0
15 14
23 22
8
7
1
12
11 10
Don’t Care
0
0
15 14
SDTO-23:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
23
8
7
1
0
Rch Data
Figure 2. Mode 0/4 Timing
LRCK
0
1
2
8
9
10
24
25
31
0
1
2
8
9
10
24
25
31
0
1
BICK (64fs)
SDTO(o)
23 22
16 15 14
Don’t Care
SDTI(i)
0
23 22
23:MSB, 0:LSB
23 22
8
7
1
16 15 14
Don’t Care
0
0
23 22
Lch Data
23
8
7
1
0
Rch Data
Figure 3. Mode 1/5 Timing
LRCK
0
1
2
21
22
23
24
28
29
30
31
0
1
2
22
23
24
28
29
30
31
0
1
BICK (64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
23
Don’t Care
23
Rch Data
Figure 4. Mode 2/6 Timing
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK (64fs)
SDTO(o)
23 22
2
1
0
SDTI(i)
23 22
2
1
0
23:MSB, 0:LSB
Don’t Care
23 22
2
1
0
23 22
2
1
0
Lch Data
Don’t Care
Rch Data
Figure 5. Mode 3/7 Timing
MS1243-E-01
2010/10
- 19 -
[AK4686]
■ Analog Soft Mute Function
LOUT1, ROUT1/LOUT2, ROUT2 are muted in soft transition when the MT1N/2N pins are set to “L” from “H”. After the
soft mute transition is finished, the DAC and Lineout are in powered-down mode and output ground level voltage
(VSS1/VSS3). The transition time is set by AMTS1-0 bits. Clocks and data must always be supplied until soft mute
transition is finished. The DAC and Lineout return to a normal operation and start digital to analog conversion when the
MT1N/2N pins are set to “H”. Mute is cancelled in soft transition after initializing time of DAC. When the MT1N/2N pin
= “L” or MT1N/2N bit = “0”, LOUT1, ROUT1/LOUT2, ROUT2 are muted.
Power(PDN pin)
MT1N/2N pin
(1)
MT1N/2N bit
DAC Internal State
Normal Operation
Init Cycle
512/fs
(2)
Normal Operation
GD
(3)
LOUT1,ROUT1/
LOUT2,ROUT2
(1) Click noise may occur if each power supply (DVDD, AVDD1/2 and CVDD) is OFF during mute period. Power
supplies should be ON longer than the soft mute time set by AMTS1-0 bits.
(2) Soft mute time is set by AMTS1-0 bits (2).
(3) Soft mute time is set by AMTS1-0 bits (3).
Figure 6. Mute Sequence Example
AMTS2 AMTS1 AMTS0
Soft Mute Time
(fs=48kHz)
(2)
MT1N/2N pin
MT1N/2N bit
16ms
16ms
32ms
32ms
64ms
64ms
128ms
128ms
256ms
256ms
8ms
16ms
2ms
16ms
(3)
MT1N/2N
0
0
0
16ms
0
0
1
32ms
(default)
0
1
0
64ms
0
1
1
128ms
1
0
0
256ms
1
0
1
16ms
1
1
X
16ms
(X: Don’t care)
Table 18. Soft Mute Time Select (@48kHz)
When AMTS2-0 bits = “101” or “11X”, the soft mute time by MT1N/2N pin and by MT1N/2N bit are different.
MS1243-E-01
2010/10
- 20 -
[AK4686]
■ Input Selector
The AK4686 has 6:1 stereo input selectors. ATIN3-0 bits control each input channel. (Table 19)
AIN3 bit
0
0
0
0
0
0
0
0
1
AIN2 bit
AIN1 bit
AIN0 bit
Input Selector
0
0
0
LIN1 / RIN1
0
0
1
LIN2 / RIN2
0
1
0
LIN3 / RIN3
0
1
1
LIN4 / RIN4
1
0
0
LIN5 / RIN5
1
0
1
LIN6 / RIN6
1
1
0
(reserved)
1
1
1
(reserved)
x
x
x
Mute
Table 19. Input Selector (for ADC, x: Don’t care)
MS1243-E-01
(default)
2010/10
- 21 -
[AK4686]
■ Charge Pump Circuit
The internal charge pump circuit generates negative voltage (CVEE) from CVDD voltage for analog input and output.
The power up time of charge pump circuit is [email protected] When PWAD and PWDA1/2 bits = “1”, the ADC and
DAC1/2 are powered-up after the charge pump circuit is powered-up.
■ Analog Input/Output (LIN1-6/RIN1-6, LOUT1-2/ROUT1-2 pins)
Power supply voltage for analog input/output is applied from a regulator for positive power and a charge-pump for
negative power. The Regulator is driven by AVDD2 and the charge-pump1 is driven by CVDD. The analog input/output
is single-ended and centered on 0V (VSS3). Therefore, the capacitor for AC-coupling can be removed. The minimum
load resistance is 5kΩ. When the DAC input signal level is 0dBFS, the output voltage is 2Vrms.
■ System Reset
When power-up the AK4686, the PDN pin should be “L” and changed to “H” after all power supplies (DVDD, AVDD1,
AVDD2 and CVDD) are supplied. After this reset is released (PDN pin = “L” → “H”), all blocks are in power-down
mode. This ensures that all internal registers reset to their initial values.
MS1243-E-01
2010/10
- 22 -
[AK4686]
■ Power ON/OFF Sequence
The each block of the AK4686 is placed in power-down mode by bringing the PDN pin to “L” and both digital filters are
reset at the same time. The PDN pin =“L” also reset the control registers to their default values. In power-down mode, the
DAC1/2 outputs 0V and the SDTO1 pin goes to “L”. This reset must always be executed after power-up.
In slave mode, after exiting reset at power-up and etc., the ADC/DAC1/DAC2 starts operation from the rising edge of
LRCK1/2 after MLCK1/2 inputs. The AK4686 is in power-down mode until MCLK1/2 and LRCK1/2 are input.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTO1
becomes available after 514/fs cycles of LRCK1 clock. In case of the DAC1/2 an analog initialization cycle starts after
exiting the power-down mode. The analog outputs are 0V during the initialization. Figure 7 shows the sequences of the
power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWAD and PWDA1/2 bits. These bits do not initialize the
internal register values. When PWAD bit = “0”, the SDTO1 pin goes to “L”. When PWDA bit = “0”, the DAC1/2 outputs
go to 0V. As some click noise occurs, the analog output should be muted externally if the click noise influences system
application.
Power
(1)
PDN
(2)
0V
CVEE pin
0V
CVEE
40/fs (3)
ADC Internal
State
(12)
Init Cycle
(4)
Normal Operation
Power-down
Normal Operation
Power-down
5/fs
DAC Internal
State
GD
(5)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
“0”data
(6)
(7)
“0”data
“0”data
(5)
GD
(8)
GD
(8)
DAC Out
(Internal Status)
(9)
Clock In
Don’t care
Don’t care
MCLK,LRCK,BICK
MT1N/2N pin or
MT1N/2N bit
LOUT1,ROUT1/LOUT2
Mute ON
Mute ON
(11)
0V
Mute
(11)
(10)
Normal
(10) Mute
0V
,ROUT2 pins
Figure 7. Power-up/down sequence example
Notes:
(1) The timing of the PDN pin “L”Æ“H” should be after the all powers (DVDD, AVDD1/2 and CVDD1) are supplied.
The AK4686 requires 150ns or longer “L” period for the reset. Supply the power during the PDN pin = “L”.
MS1243-E-01
2010/10
- 23 -
[AK4686]
(2) Power-on the charge pump circuit:
PDN pin = “L” Æ “H” & MCLK1 or MCLK2 is input.
CVEE pin becomes to the same voltage as CVEE1/2 within about 5.3ms(fs=48KHz).
Note: If the PWAD, PWDA1 and PWDA2 bits are set to “1” when the charge-pump is power-on, ADC, DAC1 and
DAC2 are initialized after the charge-pump1 circuit is powered-on.
(3) The analog block of ADC is initialized after exiting the power-down state.
(4) The analog block of DAC is initialized after exiting the power-down state.
(5) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay
(GD).
(6) ADC outputs “0” data in power-down state.
(7) Click noise occurs at the end of initialization of the analog block. Mute the digital outputs externally if the click
noise influences system application.
(8) Click noise occurs at the falling edge of PDN and 512/fs after the rising edge(after charge-pump is powered-on) of
PDN.
(9) The CVEE pin becomes 0V according to the time constant of the capacitor at the CVEE pin and the internal
resistor. The internal resistor is 17.5kΩ (typ.). Charge Pump Circuit can be powered-up during this period.
(10) AMTS1-0 bits control the soft mute transition time. When releasing the mute, the maximum DC offset is ±20mV
(at design value). This transition is a soft transition so that no clicking noise occurs.
(11) Maximum 5mV DC offset is generated when power up the lineout circuit. More than 5.3ms(fs=48KHz)+2msec
interval (after 2msec from falling edge of CVEE)is needed from a falling edge of PDN signal to a mute release to
prevent a click noise.
(12) Charge pump circuit power down:
PDN pin = “H” Æ “L”
The CVEE pin becomes 0V according to a flying capacitor and internal resistor. The internal resister is 50kΩ
(typ). Therefore, when the CVEE pin has a flying capacitor of 2.2µF, the time constant is 110ms (typ).
MS1243-E-01
2010/10
- 24 -
[AK4686]
■ Reset Function
When RSTN bit = “0”, ADC and DACs are powered-down but the internal register are not initialized. The DAC1/2
outputs become 0V and the SDTO1 pin outputs “L”. As some click noise occurs, the analog output should be muted
externally if the click noise influences system application. The Figure 8 shows the power-up sequence.
RSTN bit
1~2/fs
4~5/fs (7)
Internal
RSTN bit
516/fs
ADC Internal
State
Normal Operation
Digital Block Power-down
DAC Internal
State
Normal Operation
Digital Block Power-down
GD
Init Cycle
(1)
Normal Operation
Normal Operation
(2)
GD
ADC In
(Analog)
ADC Out
(Digital)
“0”data
DAC In
(Digital)
(4)
(3)
“0”data
(2)
GD
DAC Out
(Analog)
GD
(6)
(5)
(6)
Notes:
(1) The analog block of ADC is initialized after exiting the reset state.
(2) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group delay
(GD).
(3) ADC outputs “0” data in power-down state.
(4) Click noise occurs at the end of initialization cycle of ADC. Mute the digital output externally if the click noise
influences system application.
(5) When RSTN bit = “0”, the analog outputs become 0V.
(6) Click noise occurs in 4∼5/fs after RSTN bit becomes “0”, and occurs in 1∼2/fs after RSTN bit becomes “1”. This
noise is output even if “0” data is input.
(7) There is a delay about 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
Figure 8. Reset sequence example
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[AK4686]
■ Serial Control Interface
The AK4686 supports fast-mode I2C-bus system (max: 400kHz).
1. Data Transfer
In order to access any IC devices on the I2C BUS, input a start condition first, followed by a single Slave address which
includes the Device Address. IC devices on the BUS compare this Slave address with their own addresses and the IC
device which has an identical address with the Slave-address generates an acknowledgement. An IC device with the
identical address then executes either a read or write operation. After the command execution, input a stop condition.
1-1. Data Change
Change the data on the SDA line while SCL line is “L”. SDA line condition must be stable and fixed while the clock is
“H”. Change the Data line condition between “H” and “L” only when the clock signal on the SCL line is “L”. Change the
SDA line condition while SCL line is “H” only when the start condition or stop condition is input.
SCL
SDA
DATA LINE
STABLE :
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 9. Data Transfer
1-2. Start Condition and Stop Condition
A start condition is generated by the transition of “H” to “L” on the SDA line while the SCL line is “H”. All instructions
are initiated by a start condition. A stop condition is generated by the transition of “L” to “H” on SDA line while SCL line
is “H”. All instructions end by a stop condition.
SCL
SDA
START CONDITION
STOP CONDITION
Figure 10. START and STOP conditions
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[AK4686]
1-3. Acknowledge
An external device that is sending data to the AK4686 releases the SDA line (“H”) after receiving one-byte of data. An
external device that receives data from the AK4686 then sets the SDA line to “L” at the next clock. This operation is
called “acknowledgement”, and it enables verification that the data transfer has been properly executed. The AK4686
generates an acknowledgement upon receipt of a start condition and Slave address. For a write instruction, an
acknowledgement is generated whenever receipt of each byte is completed. For a read instruction, succeeded by
generation of an acknowledgement, the AK4686 releases the SDA line after outputting data at the designated address, and
it monitors the SDA line condition. When the master side generates an acknowledgement without sending a stop
condition, the AK4686 outputs data at the next address location. When no acknowledgement is generated, the AK4686
ends data output (not acknowledged).
Clock pulse
for acknowledge
SCL FROM
MASTER
1
8
9
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
START
CONDITION
acknowledge
Figure 11. Acknowledge on the I2C-bus
1-4. FIRST BYTE
The First Byte which includes the Slave-address is input after the Start condition is set, and a target IC device that will be
accessed on the bus is selected by the Slave-address. The Slave-address is configured with the upper 7-bits. Data of the
upper 5-bits is “00100”. The next 2 bits are address bits that select the desired IC, and these CAD1 and CAD0 bits are
fixed to “10”. When the Slave-address is inputted, an external device that has the identical device address generates an
acknowledgement and instructions are then executed. The 8th bit of the First Byte (lowest bit) is allocated as the R/W bit.
When the R/W bit is “1”, the read instruction is executed, and when it is “0”, the write instruction is executed.
0
0
1
0
0
CAD1
CAD0
R/W
Figure 12. The First Byte
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[AK4686]
2. WRITE Operations
Set R/W bit = “0” for the WRITE operation of the AK4686.
After receipt of the start condition and the first byte, the AK4684 generates an acknowledge, and awaits the second byte
(register address). The second byte consists of the address for control registers of AK4686. The format is MSB first, and
those most significant 3-bits are “Don’t care”.
*
*
*
A4
A3
A2
A1
A0
(*: Don’t care)
Figure 13. The Second Byte
After receipt of the second byte, the AK4686 generates an acknowledge, and awaits the third byte. Those data after the
second byte contain control data. The format is MSB first, 8bits.
D7
D6
D5
D4
D3
D2
D1
D0
Figure 14. Byte Structure after the Second Byte
The AK4686 is capable of more than one byte write operation by one sequence.
After receipt of the third byte, the AK4686 generates an acknowledge, and awaits the next data again. The master can
transmit more than one data word instead of terminating the write cycle after the first data word is transferred. After the
receipt of each data, the internal 5bits address counter is incremented by one, and the next data is taken into next address
automatically. If the address exceeds 05H prior to generating the stop condition, the address counter will “roll over” to
00H and the previous data will be overwritten.
S
T
A
R
T
SDA
Slave
Address
Register
Address(n)
Data(n)
S
T
Data(n+x) O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 15. WRITE Operation
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[AK4686]
3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4686.
The master can read next address’s data by generating the acknowledge instead of terminating the write cycle after the
receipt of the first data word. After the receipt of each data, the internal 5bits address counter is incremented by one, and
the next data is taken into next address automatically. If the address exceeds 0DH prior to generating stop condition, the
address counter will “roll over” to 00H and the previous data will be overwritten.
The AK4686 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
3-1. CURRENT ADDRESS READ
The AK4686 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”.
After receipt of the slave address with R/W bit set to “1”, the AK4686 generates an acknowledge, transmits 1byte data,
which address is set by the internal address counter, and increments the internal address counter by 1. If the master does
not generate an acknowledge but generate stop condition, the AK4686 discontinues transmission
S
T
A
R
T
SDA
Slave
Address
Data(n)
Data(n+1)
S
Data(n+x) T
O
P
Data(n+2)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
Figure 16. CURRENT ADDRESS READ
3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues start condition, slave address(R/W bit=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4686 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge but generate the stop condition, the AK4686 discontinues transmission.
S
T
A
R
T
SDA
S
T
A
R
T
Word
Address(n)
Slave
Address
S
Slave
Address
Data(n)
S
Data(n+x) T
O
P
Data(n+1)
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 17. RANDOM READ
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[AK4686]
■ Register Map
Addr
Register Name
D7
D6
D5
D4
00H
Powerdown 1
0
0
0
0
01H
Powerdown 2
0
PWDA2 PWDA1 PWAD
02H
Audio Data Format
0
0
0
0
03H De-emphasis/ ATT speed DEM21 DEM20 DEM11 DEM10
04H
Clock Control
0
ACKS1 DFS11 DFS10
Input Selector Control &
05H
0
AMTS2 AMTS1 AMTS0
Analog mute control
D3
0
0
DIF21
0
0
D2
MT2N
ACKS2
DIF20
0
CKS12
D1
MT1N
DFS21
DIF11
0
CKS11
D0
RSTN
DFS20
DIF10
0
CKS10
AIN3
AIN2
AIN1
AIN0
Note: For addresses from 06H to 1FH, data must not be written.
When the PDN pin is set to “L”, the registers are initialized to their default values.
When RSTN bit is set to “0”, the internal timing is reset, but registers are not initialized to their default values.
The bits defined as 0 must contain a "0" value.
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[AK4686]
■ Register Definitions
Addr
00H
Register Name
Powerdown 1
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
0
RD
0
D2
MT2N
R/W
0
D1
MT1N
R/W
0
D0
RSTN
R/W
1
RSTN: CODEC Initial Timing Reset
0: Reset. Registers are not initialized.
1: Normal operation (default)
MT1N: DAC1 Mute Control
0: Mute (default)
1: Normal Output
MT2N: DAC2 Mute Control
0: Mute (default)
1: Normal Output
MT1N: DAC1 Analog Soft Mute Control
MT1N
Pin
L
L
H
H
MT1N
bit
0
1
0
1
DAC1Analog Mute Status
Mute
Mute
Mute
Unmute
(default)
(default)
Table 20. DAC1 Analog Mute Control
MT2N: DAC2 Analog Soft Mute Control
MT2N
Pin
L
L
H
H
MT2N
bit
0
1
0
1
DAC2 Analog Mute Status
Mute
Mute
Mute
Unmute
(default)
(default)
Table 21. DAC1 Analog Mute Control
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[AK4686]
Addr
01H
Register Name
Powerdown 2
R/W
Default
D7
0
RD
0
D6
D5
PWDA2 PWDA1
R/W
R/W
1
1
D4
PWAD
R/W
1
D3
0
RD
0
D2
ACKS2
R/W
0
D1
DFS21
R/W
0
D0
DFS20
R/W
0
DFS21-20: PORT2(DAC2) Sampling Speed Control
These settings are ignored in Auto Setting Mode. Refer to Table 9.
ACKS2: PORT2(DAC2) Auto Setting Mode Control
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically when ACKS2 bit =“1”. In this case, the DFS21-20
bits are ignored. When this bit is “0”, DFS21-20 bits set the sampling speed mode.
PWAD: Power-down control of ADC
0: Power-down
1: Normal operation (default)
PWDA1: Full-Power-down control of DAC1
0: Power-down
1: Normal operation (default)
PWDA2: Full-Power-down control of DAC2
0: Power-down
1: Normal operation (default)
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[AK4686]
Addr
02H
Register Name
Audio Data Format
R/W
Default
D7
0
RD
0
D6
0
RD
0
D5
0
RD
0
D4
0
RD
0
D3
DIF21
R/W
1
D2
DIF20
R/W
1
D1
DIF11
R/W
1
D0
DIF10
R/W
1
D5
DEM11
R/W
0
D4
DEM10
R/W
1
D3
0
RD
0
D2
0
RD
0
D1
0
RD
0
D0
0
RD
0
D5
DFS11
R/W
0
D4
DFS10
R/W
0
D3
0
RD
0
D2
CKS12
R/W
0
D1
CKS11
R/W
0
D0
CKS10
R/W
0
DIF21-20: Audio format control for PORT2
Refer to Table 17.
DIF11-10: Audio format control for PORT1
Refer to Table 16.
Addr
03H
Register Name
D7
De-emphasis/ ATT speed DEM21
R/W
R/W
Default
0
D6
DEM20
R/W
1
DEM11-10: DAC1 De-emphasis filter control
DEM21-20: DAC2 De-emphasis filter control
Refer to Table 15.
Addr
04H
Register Name
Clock Control
R/W
Default
D7
0
RD
0
D6
ACKS1
R/W
0
CKS12-10: PORT1(ADC&DAC1) Clock control in Master mode.
Refer to Table 2.
DFS11-10: PORT1(ADC&DAC1) Sampling Speed Control
These settings are ignored in Auto Setting Mode. Refer to Table 3.
ACKS1: PORT1(ADC&DAC1) Auto Setting Mode
0: Disable, Manual Setting Mode (default)
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically when ACK1S bit =“1”. In this case, the DFS11-10
bits are ignored. When this bit is “0”, DFS11-10 bits set the sampling speed mode.
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[AK4686]
Addr
05H
Register Name
Input Selector Control &
Analog mute control
R/W
Default
D7
0
RD
0
D6
D5
D4
AMTS2 AMTS1 AMTS0
R/W
0
R/W
0
R/W
1
D3
D2
D1
D0
AIN3
AIN2
AIN1
AIN0
R/W
0
R/W
0
R/W
0
R/W
0
AIN3-0: ADC input selector control
0000: LIN1/RIN1 (default)
0001: LIN2/RIN2
0010: LIN3/RIN3
0011: LIN4/RIN4
0100: LIN5/RIN5
0101: LIN6/RIN6
1xxx: Mute (x: don’t care)
AMTS2-0: Analog Mute Clock Source Control
Default: “001”
Refer to Table 18.
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[AK4686]
SYSTEM DESIGN
Figure 18 shows the system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
Analog Ground
Digital Ground
Digital
Analog in
LIN1 37
NC 39
RIN1 38
LIN2 40
RIN2 41
NC 42
LIN3 43
RIN3 44
NC 45
LIN4 46
RIN4 47
NC 48
Micro
Controller
1 LIN5
SCL 36
2 RIN5
SDA 35
3 NC
BICK1 34
LRCK1 33
4 LIN6
SDTO 32
5 RIN6
VSS4 31
7 VSS1
DVDD 30
8 LOUT1
MT1N 29
9 ROUT1
MCLK1 28
10 LOUT2
SDTI1 27
10u
+
3.3V Digital
24 NC
23 BICK2
22 MCLK2
21 LRCK2
20 SDTI2
19 PDN
0.1u
Audio
DSP2
2.2u
18 CVDD
0.1u
17 CP
MT2N 25
16 VSS3
MS1 26
12 AVDD2
15 CN
11 ROUT2
14 CVEE
10u +
0.1u
13 VSS2
3.3V Analog
10u +
Audio
DSP1
3.3V Analog
AK4686
6 AVDD1
2.2u
0.1u
10u
+
3.3V Analog
Figure 18. Typical Connection Diagram (Slave mode)
Notes:
- VSS1, VSS2, VSS3, and VSS4 must be connected to the same analog ground plane.
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[AK4686]
1. Grounding and Power Supply Decoupling
The AK4686 requires careful attention to power supply and grounding arrangements. AVDD1, AVDD2, DVDD and
CVDD are usually supplied from analog supply in system. If AVDD1, AVDD2, DVDD, and CVDD are supplied
separately, it is recommended to power-up DVDD first to avoid a click noise. VSS1, VSS2, VSS3 and VSS4 of the
AK4686 must be connected to analog ground plane. System analog ground and digital ground must be connected
together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to
the AK4686 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference Inputs
The voltage of AVDD1 sets the ADC input range, and AVDD1 (AVDD2) sets the DAC1(DAC2) analog output range. A
0.1μF ceramic capacitor should be attached between the AVDD1/2 pin and VSS1/2 pin.
3. Analog Inputs
The AK4686 receives the analog input through the single-ended Pre-amp. The input range is 2.2 x AVDD1/3.3 Vrms (typ.
fs=48kHz) at each analog input pins. Each input pins are biased to 0V(typ) internally. The ADC output data format is 2’s
complement. The internal digital HPF removes the DC offset.
The AK4686 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK4686 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
AK4686
Analog In
LIN1-6,
RIN1-6
2.0Vrms
Figure 19. External Circuit Example1
4. Analog Outputs
The analog outputs are also single-ended and centered on 0V (typ). The output signal range scales with the supply voltage
and nominally 2 x AVDD2(AVDD3)/3.3 Vrms at each analog output pins. The DAC1(DAC2) input data format is 2’s
complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for
800000H(@24bit). The ideal output is 0V for 000000H(@24bit). The internal analog filters (SCF and CTF) remove most
of the noise generated by the delta-sigma modulator of DAC1(DAC2) beyond the audio passband.
The DC offsets on analog outputs are typically 0V.
AK4686
Analog
Out
470
LOUT1/2,
ROUT1/2
2.0Vrms (typ)
Figure 20. External Circuit Example1
5. Attention to the PCB Wiring
Attention should be given to avoid coupling with other signals on each analog input/output pins. Unused input pins among
LIN1-6 and RIN1-6 pins must be left open.
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[AK4686]
PACKAGE
48pin LQFP(Unit: mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
9.0 ± 0.2
25
12
0.09 ∼ 0.20
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.30 ~ 0.75
■ Material & Lead Finish
Package molding compound: Epoxy, Halogen (Bromine and Chlorine) free
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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[AK4686]
MARKING
AK4686EQ
XXXXXXX
1
1)
2)
3)
4)
Pin #1 indication
Asahi Kasei Logo
Marking Code: AK4686EQ
Date Code: XXXXXXX (7 digits)
REVISION HISTORY
Date (YY/MM/DD)
10/10/05
10/10/25
Revision
00
01
Reason
First Edition
Specification
Change
Page
Contents
7
Analog Characteristics
DAC to Analog Output
Output Voltage: 1.85 → 1.90Vrms (min)
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[AK4686]
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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