APW7067N Synchronous Buck PWM and Linear Controller Features General Description • The APW7067N integrates synchronous buck PWM Provided Two Regulated Voltages and linear controller, as well as monitoring and pro- - Synchronous Buck Converter tection functions into a single package. The synchro- - Linear Regulator • • nous PWM controller drives dual N-channel MOSFETs, Single 12V Power Supply Required which provides one controlled power output with under- Excellent Both Output Voltage Regulation voltage and over-current protections. Linear controller - 0.8V Internal Reference drives an external N-channel MOSFET with under-voltage protection. - ±1% Over Line Voltage and Temperature • • The APW7067N provides excellent regulation for output Integrated Soft-Start for PWM and Linear Outputs load variation. An internal 0.8V temperature-compensated Programmable Frequency Range reference voltage is designed to meet the requirement from 150 kHz to 1000kHz • of low output voltage applications. The switching Voltage Mode PWM Control Design and frequency is adjustable from 150kHz to 1000kHz. Up to 89% (Typ.) Duty Cycle • • The APW7067N with excellent protection functions: Under-Voltage Protection for PWM and Linear POR, OCP and UVP. The Power-On Reset (POR) Output circuit can monitor VCC12 supply voltage exceeds Over-Current Protection for PWM Output its threshold voltage while the controller is running, and a built-in digital soft-start provides both outputs - Sense Low-Side MOSFET’s RDS(ON) • • with controlled rising voltage. The Over-Current Protection SOP-14, QSOP-16 and QFN-16 packages (OCP) monitors the output current by using the voltage Lead Free Available (RoHS Compliant) drop across the lower MOSFET’s RDS(ON), comparing with internal VOCP (0.25V), eliminating the need for a current sensing resister. When the output current Applications reaches the trip point, the controller will shutdown the IC directly, and latch the converter’s output. The • Under-Voltage Protection (UVP) monitors the voltages Graphic Cards of FB and FBL pins for short-circuit protection. When the VFB or VFBL is less than 50% of VREF, the controller will shutdown the IC directly. ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 1 www.anpec.com.tw APW7067N COMP 3 FB 4 DRIVE 5 14 PGND 13 LGATE 10 NC 9 NC FBL 6 GND 7 8 VCC12 10 VCC12 9 VCC12 GND 8 1 FB 2 DRIVE 3 FBL 4 15 14 13 Metal GND Pad (Bottom) 5 SOP-14 TOP VIEW QSOP-16 TOP VIEW AGND FBL 6 GND 7 12 NC 11 NC COMP PHASE 12 PGND 11 LGATE 16 6 7 8 VCC12 COMP 3 FB 4 DRIVE 5 UGATE 16 UGATE 15 PHASE VCC12 BOOT 1 FS_DIS 2 BOOT 14 UGATE 13 PHASE DGND BOOT 1 FS_DIS 2 FS_DIS Pinouts 12 PGND 11 LGATE 10 NC 9 NC QFN-16 TOP VIEW Ordering and Marking Information Package Code K : SOP - 14 M : QSOP - 16 QA : QFN - 16 Temp. Range E : -20 to 70 °C Handling Code TU : Tube TR : Tape & Reel TY : Tray (for QFN only) Lead Free Code L : Lead Free Device Blank : Original Device APW7067N Lead Free Code Handling Code Temp. Range Package Code APW7067N K : APW7067N M : APW7067N Q : APW7067N XXXXX XXXXX - Date Code APW7067N XXXXX XXXXX - Date Code XXXXX - Date Code APW7067N XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 2 www.anpec.com.tw APW7067N Block Diagram VCC12 Power-On Reset Regulator BOOT GND Sense Low Side UGATE VREF 10V (0.8V) 50%VREF :2 U.V.P Comparator O.C.P Comparator PHASE Soft Start and Fault Logic VOCP 0.25V Gate Control LGATE Error Amp 1 PGND PWM Comparator U.V.P Comparator FBL 10V :2 50%VREF DRIVE VREF Oscillator FB COMP Sawtooth wave Error Amp 2 VREF FS_DIS Absolute Maximum Ratings Symbol Parameter Rating Unit VCC12 VCC12 to GND -0.3 to +16 V BOOT BOOT to PHASE -0.3 to +16 V UGATE UGATE to PHASE <400ns pulse width >400ns pulse width -5 to BOOT+5 -0.3 to BOOT+0.3 V LGATE to PGND <400ns pulse width >400ns pulse width -5 to VCC12+5 -0.3 to VCC12+0.3 V PHASE to GND <400ns pulse width >400ns pulse width -5 to +21 -0.3 to 16 V DRIVE to GND 12 V FB, FBL, COMP, FB, FBL, COMP, FS_DIS to GND FS_DIS -0.3 to 7 V LGATE PHASE DRIVE Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 3 www.anpec.com.tw APW7067N Absolute Maximum Ratings (Cont.) Symbol PGND TJ Parameter Rating Unit PGND to GND -0.3 to +0.3 V Junction Temperature Range -20 to +150 °C -65 ~ 150 °C TSTG Storage Temperature TSDR Soldering Temperature (10 Seconds) 300 °C VESD Minimum ESD Rating ±2 KV NOTE1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE2: The device is ESD sensitive. Handling precautions are recommended. Recommended Operating Conditions Symbol Parameter VCC12 VIN1 Rating Unit IC Supply Voltage 10.8 to 13.2 V Converter Input Voltage 2.9 to 13.2 V VOUT1 Converter Output Voltage 0.9 to 5 V IOUT1 Converter Output Current 0 to 30 A IOUT2 Linear Output Current 0 to 3 A TA Ambient Temperature Range -20 to 70 °C TJ Junction Temperature Range -20 to 125 °C Electrical Characteristics Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C. Symbol Parameter Test Conditions APW7067N Min Typ Max Unit INPUT SUPPLY CURRENT ICC12 VCC12 Supply Current (Shutdown mode) UGATE, LGATE and DRIVE open; FS_DIS = GND 4 6 mA VCC12 Supply Current UGATE, LGATE and DRIVE open; FOSC = 600kHz 16 24 mA POWER-ON RESET Rising VCC12 Threshold 7.7 7.9 8.1 V Falling VCC12 Threshold 7.2 7.4 7.6 V Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 4 www.anpec.com.tw APW7067N Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C. Symbol Parameter Test Conditions APW7067N Min Typ Max Unit OSCILLATOR Accuracy -15 +15 % FOSC Oscillator Frequency RFS_DIS = 110k ohms 255 300 345 kHz FOSC Oscillator Frequency RFS_DIS = 47k ohms 510 600 690 kHz VOSC Ramp Amplitude (nominal 1.2V to 2.7V) (NOTE3) Duty Maximum Duty Cycle 1.5 V 89 % REFERENCE VREF Reference Voltage for Error Amp1 and Amp2 Reference Voltage Tolerance PWM Load Regulation Linear Load Regulation 0.792 0.80 -1 IOUT1 = 0 to 10A IOUT2 = 0 to 3A PWM ERROR AMPLIFIER Gain Open Loop Gain V +1 % 1 % % 1 % % % RL = 10k, CL = 10pF (NOTE3) 93 dB RL = 10k, CL = 10pF (NOTE3) 20 MHz Slew Rate RL = 10k, CL = 10pF (NOTE3) 8 V/us FB Input Current VFB = 0.8V GBWP Open Loop Bandwidth SR 0.808 0.1 1 uA VCOMP COMP High Voltage 5 V VCOMP COMP Low Voltage 0 V ICOMP COMP Source Current COMP = 2V 12 mA ICOMP COMP Sink Current COMP = 2V 12 mA BOOT = 12V, UGATE-PHASE = 2V 2.5 A 2 A 2.5 A 3.5 A GATE DRIVERS IUGATE Upper Gate Source Current IUGATE Upper Gate Sink Current ILGATE Lower Gate Source Current ILGATE Lower Gate Sink Current VCC12 = 12V, LGATE = 2V RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A 2.25 3.375 Ω RUGATE Upper Gate Sink Impedance 0.7 1.05 Ω RLGATE Lower Gate Source Impedance VCC12 = 12V, ILGATE = 0.1A 2.25 3.375 Ω RLGATE Lower Gate Sink Impedance 0.4 0.6 Ω TD BOOT = 12V, IUGATE = 0.1A VCC12 = 12V, ILGATE = 0.1A Dead Time Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 20 5 nS www.anpec.com.tw APW7067N Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70°C. Typical values are at TA = 25°C. Symbol Parameter APW7067N Test Conditions Min Typ Max Unit LINEAR REGULATOR Open Loop Gain Gain RL = 10k, CL = 10pF (NOTE3) 70 dB RL = 10k, CL = 10pF (NOTE3) 19 MHz Slew Rate RL = 10k, CL = 10pF (NOTE3) 6 V/us FBL Input Current VFBL= 0.8V GBWP Open Loop Bandwidth SR 0.1 1 uA VDRIVE DRIVE High Voltage 10 V VDRIVE DRIVE Low Voltage 0 V IDRIVE DRIVE Source Current DRIVE = 5V 4 mA IDRIVE DRIVE Sink Current DRIVE = 5V 3 mA PROTECTION VFB-UV FB Under Voltage Protection Trip Point Percent of VREF 50 % VFBL-UV FBL Under Voltage Protection Trip Point Percent of VREF 50 % VOCP 230 OCP Voltage 250 270 mV SOFT START TSS Internal Soft-Start Interval (NOTE3) FOSC = 600kHz 2.1 ms FOSC = 300kHz 4.2 ms NOTE3: Guaranteed by design. Typical Application Circuit C1 VIN1 2.2nF Q3 12V ON/OFF CIN1 2N7002 R2 C2 3.9K 0.01uF 470uFx2 Q1 APM2509 VOUT1 R3 C4 0.1uF 22nF RFS_DIS RGND1 1 BOOT UGATE 14 2 FS_DIS PHASE 13 3 COMP PGND 12 4 FB LGATE 11 COUT1 470uFx2 C6 Q2 470uF 1.2V 3K 3.3V CIN2 VOUT1 1uH C3 22Ω VIN2 L R1 1.5K Q4 APM3055 C5 5 DRIVE NC 10 6 FBL NC 9 7 GND VCC12 8 R6 2.2Ω R5 R4 2.2nF APM2506 12V R7 2.2Ω VOUT2 2.5V APW7067N 2.5K COUT2 470uF RGND2 C7 1uF 1.17K * C5, R5 for specific application Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 6 www.anpec.com.tw APW7067N Function Pin Descriptions VCC12 - downed immediately. Power supply input pin. Connect a nominal 12V power UGATE supply to this pin. The power-on reset function monitors This pin is the gate driver for the upper MOSFET of the input voltage at this pin. It is recommended that a PWM output. decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling. LGATE BOOT This pin is the gate driver for the lower MOSFET of PWM output. This pin provides the bootstrap voltage to the upper DRIVE gate driver for driving the N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal This pin drives the gate of an external N-channel diode, and the power supply valtage VCC12, generates MOSFET for linear regulator. It is also used to set the the bootstrap voltage for the upper gate diver (UGATE). compensation for some specific applications, for PHASE example, with low values of output capacitance and ESR. This pin is the return path for the upper gate driver. FBL Connect this pin to the upper MOSFET source, and connect a capacitor to BOOT for the bootstrap voltage. This pin is the inverting input of the linear regulator This pin is also used to monitor the voltage drop across error amplifier. It is used to set the output voltage. the lower MOSFET for over-current protection. This pin is also monitored for under-voltage protection, GND when the FBL voltage is under 50% of reference voltage (0.4V), both outputs will be shutdown immediately. This pin is the signal ground pin. Connect the GND pin to a good ground plane. FS_DIS PGND This pin be allowed to adjust the switching frequency. Connect a resistor from FS_DIS pin to the ground to This pin is the power ground pin for the lower gate increase the switching frequency. This pin also provides driver. It should be tied to GND pin on the board. shutdown function, use an open drain logic signal to COMP pull this pin low to disable both outputs, leave open to enable both outputs. This pin is the output of PWM error amplifier. It is used to set the compensation components. FB This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for undervoltage protection, when the FB voltage is under 50% of reference voltage (0.4V), both outputs will be shut Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 7 www.anpec.com.tw APW7067N Typical Characteristics Power Off Power On VCC12=12V, Vin1=12V,Vin2=3.3V VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V, L=1uH Vo1=1.2V,Vo2=2.5V, L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Vo2 (2V/div) Time: 5ms/div CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Vo2 (2V/div) Time: 5ms/div EN Shutdown(FS_DIS=GND) VCC12=12V, Vin1=12V,Vin2=3.3V Vcc12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH Vo1=1.2V,Vo2=2.5V,L=1uH CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH4 CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: Vo1 (1V/div) CH4: Vo2 (2V/div) Time: 5ms/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: Vo1 (1V/div) CH4: Vo2 (2V/div) Time: 5ms/div 8 www.anpec.com.tw APW7067N Typical Characteristics (Cont.) UGATE Falling UGATE Rising Vcc12=12V, Vin1=12V, Vo1=1.2V Vcc12=12V, Vin1=12V, Vo1=1.2V CH1 CH1 CH2 CH2 CH3 CH3 CH1: Ug (20V/div) CH2: Phase (10V/div) CH3: Lg (10V/div) Time: 50ns/div CH1: Ug (20V/div) CH2: Phase (10V/div) CH3: Lg (10V/div) Time: 50ns/div UVP_PWM Controller(FB< 0.4V) UVP_Linear Regulator(FBL< 0.4V) VCC12=12V, Vin1=12V Vo1=1.2V, L=1uH, Io1=10A VCC12=12V, Vin2=3.3V Vo2=2.5V, Io2=3A CH1 CH1 CH2 CH2 CH3 CH4 CH3 CH1: FB (1V/div) CH2: Vo1 (1V/div) CH3: Ug (20V/div) CH4: COMP (5V/div) Time: 50us/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 CH1: FBL (1V/div) CH2: Drive (5V/div) CH3: Vo2 (2V/div) Time: 100us/div 9 www.anpec.com.tw APW7067N Typical Characteristics (Cont.) Load Transient Response(PWM Controller) - VCC12=12V, Vin1=12V, Vo1=2V, Fosc=300KHz - Io1 slew rate= ± 10 A/us Io1=0Aà10Aà0A Io1=0Aà10A Io1=10Aà0A CH1 CH1 CH1 CH2 CH2 CH2 CH3 CH3 CH3 CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) Time: 20us/div Time: 50us/div Time: 20us/div Load Transient Response(Linear Regulator) - VCC12=12V, Vin2=3.3V, Vo2=2.5V - Io2 slew rate= ± 3A/us Io2=0Aà3Aà0A Io2=0Aà3A Io2=3Aà0A CH1 CH1 CH1 CH2 CH2 CH2 CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) Time: 1us/div Time: 10us/div Time: 1us/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 10 www.anpec.com.tw APW7067N Typical Characteristics (Cont.) Short Test after Power Ready Over Current Protection VCC12=12V, Vin1=12V, Vo1=1.2V, L=1uH, Co=470uH*2, L_Side_Rds(on)=17mΩ VCC12=12V, Vin1=12V, Vo1=1.2V, L=1uH, Co=470uH*2, L_Side_Rds(on)=17mΩ CH1 CH1 CH2 CH2 CH3 CH3 CH4 CH4 CH1: Vo1 (1V/div) CH2: Drive (5V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 50us/div CH1: Vo1 (1V/div) CH2: Drive (5V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 50us/div Short Test before Power On VREF vs. Junction Temperature 0.804 VCC12=12V, Vin1=12V,Vo1=1.2V, L=1uH, Co=470uH*2, L_Side_Rds(on)=17mΩ 0.8035 Reference Voltage(V) CH1 CH2 CH3 0.803 0.8025 0.802 VREF 0.8015 0.801 0.8005 -40 CH4 CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 2ms/div Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 -20 0 20 40 60 80 100 120 Junction Temperature (°C) 11 www.anpec.com.tw APW7067N Typical Characteristics (Cont.) UGATE Sink Current vs. UGATE Voltage 3 3.5 2.5 3 UGATE Sink Current (A) UGATE Source Current (A) UGATE Source Current vs. UGATE Voltage VBOOT=12V 2 Phase=0V 1.5 1 0.5 VBOOT=12V 2.5 Phase=0V 2 1.5 1 0.5 0 0 0 2 4 6 8 10 0 12 0.5 1 2 2.5 3 UGATE Voltage (V) UGATE Voltage (V) LGATE Sink Current vs. LGATE Voltage LGATE Source Current vs. LGATE Voltage 7 3 6 2.5 VCC=12V VCC=12V LGATE Sink Current (A) LGATE Source Current (A) 1.5 2 1.5 1 0.5 0 0 2 4 6 8 10 4 3 2 1 0 12 0 LGATE Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 5 1 2 3 4 LGATE Voltage(V) 12 www.anpec.com.tw APW7067N Function Descriptions Voltage(V) Power On Reset (POR) The Power-On Reset (POR) function of APW7067N continually monitors the input supply voltage (VCC12), VCC12 ensures the supply voltage exceed its rising POR threshold voltage. The POR function initiates soft-start POR interval operation while VCC12 voltages exceed their POR threshold and inhibits operation under disabled status. VOUT1 VOUT2 Soft-Start Figure 1. shows the soft-start interval. When VCC12 reaches the rising POR threshold voltage, the internal t0 reference voltage is controlled to follow a voltage pro- t1 portional to the soft-start voltage. The soft-start inter- t2 Time Figure 1. Soft-Start Interval val is variable by the oscillator frequency. The formulation is given by: TSS = ∆( t 2 − t1) = 1 FOSC Voltage(V) × 1280 FB Figure 2. shows more detail of the FB and FBL voltage ramps. The FB and FBL voltage soft-start ramps are FBL 20mV 32/Fosc formed with many small steps of voltage. The voltage of one step is about 20mV in FB and FBL, and the 32/Fosc 20mV period of one step is about 32/FOSC. This method provides a controlled voltage rise and prevents the t3 large peak current to charge the output capacitors. t4 Time Figure 2. The Controlled Stepped FB and The FB voltage compares the FBL voltage to shift to an FBL Voltage during Soft-Start earlier time the establishment as Figure2. The voltage estabilishment time difference for FB and FBL is Over-Current Protection variable by the oscillator. The formulation is given by: The over-current protection monitors the output current by using the voltage drop across the lower MOSFET’s ∆(t 4 − t3) = 1 FOSC × 320 = RDS(ON) and this voltage drop will be compared with the 1 × TSS 4 internal 0.25V reference voltage. When the voltage drop across the lower MOSFET’s RDS(ON) is larger than 0.25V, an over-current condition is detected, the controller will shutdown the IC directly, and latch the converter's output. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 13 www.anpec.com.tw APW7067N Function Descriptions Over-Current Protection (Cont.) shutdown the APW7067N PWM controller. In shut- The threshold of the over current limit is given by: down mode, the UGATE and LGATE turn off and pull to PHASE and GND respectively. ILIMIT VOCP (0.25V) = R DS(ON) (Low _ Side ) Switching Frequency The APW7067N provides the adjustable oscillator For the over-current is never occurred in the normal switching frequency . The switching frequency is de- operating load range; the variation of all parameters in termined by the value of RFS_DIS (from FS_DIS pin to the above equation should be determined. GND), the adjustable range from150kHz to 1000kHz . Figure 3. shows how to select the resistor for the - The MOSFET’s RDS(ON) is varied by temperature and gate to source voltage, the user should deter desired frequency. If the IC is operated in higher mine the maximum RDS(ON) in manufacture’s frequencies (ex. 600 kHz or above), the slope of datasheet. the curve is steep, and a small change in resistance will have a big effect on the frequency. At - The minimum VOCP should be used in the above lower frequencies, the slope of the curve is much equation. less steep, even a large change in resistor value - Note that the ILIMIT is the current flow through the doesn’t change the frequency too much. Figure 4. lower MOSFET; ILIMIT must be greater than maximum shows more detail for the higher frequency and output current add the half of inductor ripple current. Figure5. shows the lower frequency. Under Voltage Protection 1600 1400 The FB and FBL pin are monitored during converter operation by their own Under Voltage (UV) comparator. 1200 If the FB or FBL voltage drop below 50% of the 1000 Fosc(KHz) reference voltage (50% of 0.8V = 0.4V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter’s 800 600 output is latched to be floating. 400 Shutdown and Enable 200 Pulling the FS_DIS voltage to GND by an open drain 0 0 100 200 300 400 500 600 700 800 R ( KΩ) transistor, shown in typical application circuit, Figure 3. Oscillator Frequency vs. R FS-DIS Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 14 www.anpec.com.tw APW7067N Function Descriptions (Conts) Switching Frequency (Cont.) 500 1200 450 400 1000 Fosc(KHz) Fosc(KHz) 350 800 300 250 200 600 150 100 400 0 10 20 30 40 50 60 70 50 80 150 250 350 450 550 650 750 R(KΩ) R(KΩ) Figure 4. Oscillator Frequency vs.R Figure 5. Oscillator Frequency vs.R FS-DIS FS-DIS (High Frequency) (Low Frequency) Application Information Where R4 is the resistor connected from VOUT2 to Output Voltage Selection FBL and RGND2 is the resistor connected from FBL to The output voltage of PWM converter can be programmed GND. with a resistive divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is Linear Regulator Input/Output Capacitor Selection the inverter input of the error amplifier, and the reference The input capacitor is chosen based on its voltage voltage is 0.8V. The output voltage is determined by: rating. Under load transient condition, the input R1 VOUT1 = 0.8 × 1 + R GND1 capacitor will momentarily supply the required transient Where R1 is the resistor connected from VOUT1 to FB condition. In addition, the capacitor is chosen based and RGND1 is the resistor connected from FB to GND. on its voltage rating. The linear regulator output voltage VOUT2 is also set by Linear Regulator Input/Output MOSFET Selection means of an external resistor divider. The FBL pin is The maximum DRIVE voltage is about 10V when the inverter input of the error amplifier, and the reference VCC12 is equal 12V. Since this pin drives an external voltage is 0.8V. The output voltage is determined by: N-channel MOSFET, therefore the maximum output R4 VOUT2 = 0.8 × 1 + R GND2 current. The output capacitor for the linear regulator is chosen to minimize any droop during load transient voltage of the linear regulator is dependent upon the VGS. VOUT2MAX = 10 - VGS Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 15 www.anpec.com.tw APW7067N Application Information (Conts) Another criterion is its efficiency of heat removal. The PHASE power dissipated by the MOSFET is given by: L OUTPUT1 Pd = IOUT2 x (VIN2 – VOUT2 ) COUT1 Where IOUT2 is the maximum load current, VOUT2 is the ESR nominal output voltage. In some applications, heatsink might be required to Figure 6. The Output LC Filter help maintain the junction temperature of the MOSFET below its maximum rating. FLC Linear Regulator Compensation Selection -40dB/dec GAIN (dB) The linear regulator is stable over all loads current. However, the transient response can be further enhanced by connecting a RC network between the FBL and DRIVE pin. Depending on the output capacitance and FESR -20dB/dec load current of the application, the value of this RC network is then varied. PWM Compensation Frequency(Hz) The output LC filter of a step down converter introduces Figure 7. The LC Filter GAIN and Frequency a double pole, which contributes with -40dB/decade The PWM modulator is shown in Figure 8. The input gain slope and 180 degrees phase shift in the control is the output of the error amplifier and the output is the loop. A compensation network among COMP, FB and PHASE node. The transfer function of the PWM VOUT1 should be added. The compensation network is modulator is given by: shown in Fig. 9. The output LC filter consists of the output inductor and output capacitors. The transfer GAINPWM = function of the LC filter is given by: GAINLC = 1 + s × ESR × COUT1 s2 × L × COUT1 + s × ESR × COUT1 + 1 ΔVOSC FESR VIN1 Driver OSC The poles and zero of this transfer functions are: FLC = VIN ∆VOSC PWM Comparator PHASE Output of Error Amplifier 1 2 × π × L × C OUT1 Driver 1 = 2 × π × ESR × C OUT1 Figure 8. The PWM Modulator The compensation network is shown in Figure 9. It The FLC is the double poles of the LC filter, and FESR is provides a close loop transfer function with the highest the zero introduced by the ESR of the output capacitor. zero crossover frequency and sufficient phase margin. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 16 www.anpec.com.tw APW7067N Application Information (Cont.) PWM Compensation (Cont.) 1.Choose a value for R1, usually between 1K and 5K. The transfer function of error amplifier is given by: GAINAMP 1 1 // R2 + VCOMP sC1 sC2 = = VOUT1 1 R1// R3 + sC3 2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2: 1 1 s + × s + ( ) R2 × C2 R1 + R3 × C3 R1 + R3 = × C1 + C2 1 R1 × R3 × C1 s s + × s + R2 × C1 × C2 R3 × C3 3.Place the first zero FZ1 before the output LC filter The poles and zeros of the transfer function are: double pole frequency FLC. F Z1 = FZ2 R2 = FZ1 = 0.75 X FLC 1 2 × π × R2 × C2 Calculate the C2 by the equation: 1 = 2 × π × (R1 + R3 ) × C3 C2 = 1 C1 × C2 2 × π × R2 × C1 + C2 1 = 2 × π × R3 × C3 FP1 = FP2 C3 R2 1 2 × π × R2 × FLC × 0.75 4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation: C1 = C1 R3 ∆ VOSC F × O × R1 VIN FLC C2 C2 2 × π × R2 × C2 × FESR − 1 5.Set the second pole FP2 at the half of the switching V OUT1 R1 FB frequency and also set the second zero FZ2 at the V COMP output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop V REF gain, check the compensation gain at FP2 with the Figure 9. Compensation Network capabilities of the error amplifier. The closed loop gain of the converter can be written FP2 = 0.5 X FS as: FZ2 = FLC GAINLC X GAINPWM X GAINAMP Figure 10. shows the asymptotic plot of the closed Combine the two equations will get the following loop converter gain, and the following guidelines will component calculations: help to design the compensation network. Using the R3 = R1 FS −1 2 × FLC C3 = 1 π × R3 × FS below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 17 www.anpec.com.tw APW7067N Application Information (Cont.) PWM Compensation (Cont.) starting point is to choose the ripple current to be approximately 30% of the maximum output current. F Z1 F Z2 F P1 Once the inductance value has been chosen, select F P2 an inductor that is capable of carrying the required GAIN (dB) peak current without going into saturation. In some 20log (R2/R1) 20log (V IN /Δ V OSC ) types of inductors, especially core that is made of Compensation Gain ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. F LC Output Capacitor Selection F ESR PWM & Filter Gain Converter Gain Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, Frequency(Hz) selecting high performance low ESR capacitors is intended for switching regulator applications. In some Figure 10. Converter Gain and Frequency applications, multiple capacitors have to be parallel to Output Inductor Selection achieve the desired ESR value. A small decoupling The inductor value determines the inductor ripple capacitor in parallel for bypassing the noise is also current and affects the load transient response. Higher recommended, and the voltage rating of the output inductor value reduces the inductor’s ripple current and capacitors also must be considered. If tantalum induces lower output ripple voltage. The ripple current capacitors are used, make sure they are surge tested and ripple voltage can be approximated by: by the manufactures. If in doubt, consult the capacitors IRIPPLE = VIN1 − VOUT1 VOUT1 × FS × L VIN1 manufacturer. Input Capacitor Selection ∆ VOUT1 = IRIPPLE × ESR The input capacitor is chosen based on the voltage where Fs is the switching frequency of the regulator. rating and the RMS current rating. For reliable Although increase of the inductor value and frequency operation, select the capacitor voltage rating to be at reduces the ripple current and voltage, a tradeoff will least 1.3 times higher than the maximum input voltage. exist between the inductor’s ripple current and the regulator load transient response time. The maximum RMS current rating requirement is approximately IOUT1/2, where IOUT1 is the load current. During power up, the input capacitors have to handle A smaller inductor will give the regulator a faster load large amount of surge current. If tantalum capacitors transient response at the expense of higher ripple are used, make sure they are surge tested by the current. Increasing the switching frequency (FS) also manufactures. If in doubt, consult the capacitors reduces the ripple current and voltage, but it will manufacturer. For high frequency decoupling, a ceramic increase the switching loss of the MOSFET and the capacitor 1uF can be connected between the drain of power dissipation of the converter. The maximum ripple upper MOSFET and the source of lower MOSFET. current occurs at the maximum input voltage. A good Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 18 www.anpec.com.tw APW7067N Application Information (Cont.) MOSFET Selection The selection of the N-channel power MOSFETs are traces should minimize interconnecting imped- determined by the RDS(ON), reverse transfer capacitance ances and the magnitude of voltage spike. And signal (CRSS) and maximum output current requirement. There and power grounds are to be kept separate till are two components of loss in the MOSFETs: combined using ground plane construction or single conduction loss and transition loss. For the upper point grounding. Figure 11. illustrates the layout, with and lower MOSFET, the losses are approximately bold lines indicating high current paths; these traces given by the following: must be short and wide. Components along the bold lines should be placed lose together. Below is a PUPPER = IOUT1 (1+ TC)(RDS(ON))D + (0.5)( IOUT1)(VIN1)( tSW)FS checklist for your layout: PLOWER = IOUT1 (1+ TC)(RDS(ON))(1-D) - The metal plate of the bottom of the packages Where IOUT1 is the load current (QFN-16) must be soldered to the PCB and con- TC is the temperature dependency of RDS(ON) nected to the GND plane on the backside through FS is the switching frequency several thermal vias. tSW is the switching interval - Keep the switching nodes (UGATE, LGATE and D is the duty cycle PHASE) away from sensitive small signal nodes Note that both MOSFETs have conduction loss while since these nodes are fast moving signals. the upper MOSFET include an additional transition Therefore, keep traces to these nodes as short as loss. The switching internal, tSW , is a function of the possible. reverse transfer capacitance C RSS. The (1+TC) term is - The traces from the gate drivers to the MOSFETs to factor in the temperature dependency of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” (UG, LG, DRIVE) should be short and wide. - Place the source of the high-side MOSFET and curve of the power MOSFET. the drain of the low-side MOSFET as close as Layout Considerations possible. Minimizing the impedance with wide In any high switching frequency converter, a correct layout plane between the two pads reduces the layout is important to ensure proper operation of the voltage bounce of the node. regulator. With power devices switching at 300KHz or above, the resulting current transient will cause voltage - Decoupling capacitor, compensation component, the resistor dividers and boot capacitors should spike across the interconnecting impedance and be close their pins. (For example, place the parasitic circuit elements. As an example, consider decoupling ceramic capacitor near the drain of the turn-off transition of the PWM MOSFET. Before the high-side MOSFET as close as possible. The turn-off, the MOSFET is carrying the full load current. bulk capacitors are also placed near the drain). During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and - The input capacitor should be near the drain of parasitic diode. Any parasitic inductance of the circuit the upper MOSFET; the output capacitor should generates a large voltage spike during the switching be near the loads. The input capacitor GND should interval. In general, using short, wide printed circuit be close to the output capacitor GND and the lower Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 19 www.anpec.com.tw APW7067N Application Information (Cont.) Layout Considerations (Cont.) MOSFET GND. - The drain of the MOSFETs (VIN1 and PHASE nodes) should be a large plane for heat sinking. APW7067N VIN1 VCC12 VIN2 BOOT DRIVE UGATE FBL PHASE VOUT2 L O A D LGATE L O A D VOUT1 Figure 11. Layout Guidelines Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 20 www.anpec.com.tw APW7067N Package Information 0.015 x 45 H E SOP – 14 (150mil) C D A Dim A A1 B C D E e H L θ° B GAUGE PLANE SEATING PLANE 0.010 e A1 Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 Inches Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150 6.215 1.274 8° 0.228 0.015 0° 1.274 5.808 0.382 0° Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 L Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 21 0.244 0.050 8° www.anpec.com.tw APW7067N Package Information QSOP-16 D E GAUGE PLANE E1 1 2 3 A e b L Millimeters Dim A A1 b D E E1 e L φ1 1 A1 Min. 1.35 0.10 0.20 4.80 5.79 3.81 Inches Max. 1.75 0.25 0.30 5.00 6.20 3.99 Min. 0.053 0.004 0.008 0.189 0.228 0.150 1.27 8° 0.016 0° 0.635 TYP. 0.41 0° Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 Max. 0.069 0.010 0.012 0.197 0.244 0.157 0.025 TYP. 22 0.050 8° www.anpec.com.tw APW7067N Package Information QFN-16 e b E E2 L D D2 A2 A A A1 A2 A3 D E b D2 E2 e L A1 A3 Dim Millimeters Min. 0.76 0.00 0.57 Inches Max. 0.84 0.04 0.63 Min. 0.030 0.00 0.022 4.10 4.10 0.35 2.15 2.15 0.154 0.154 0.010 0.081 0.081 0.20 REF. 3.90 3.90 0.25 2.05 2.05 0.008 REF. 0.650 BSC 0.50 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 Max. 0.033 0.0015 0.025 0.161 0.161 0.014 0.085 0.085 0.0257BSC 0.60 0.002 23 0.024 www.anpec.com.tw APW7067N Physical Specifications Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3. Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone T L to T P Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25 °C to Peak Tim e Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 24 www.anpec.com.tw APW7067N Classification Reflow Profiles (Cont.) Table 1. SnPb Entectic Process – Package Peak Reflow Temperatures 3 3 Package Thickness Volum e m m Volume mm <350 ≥350 <2.5 m m 240 +0/-5°C 225 +0/-5°C ≥2.5 m m 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 m m 260 +0°C* 260 +0°C* 260 +0°C* 1.6 m m – 2.5 m m 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 m m 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 SEC 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA Carrier Tape & Reel Dimensions t D P Po E P1 Bo F W Ko Ao Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 D1 25 www.anpec.com.tw APW7067N Carrier Tape & Reel Dimensions (Cont.) T2 J C A B T1 Application SOP-14 (150mil) A B 330REF 100REF F D 7.5 Application QSOP- 16 C 13.0 + 0.5 - 0.2 D1 φ0.50 + 0.1 φ1.50 (MIN) A B 330 ± 1 62 +1.5 F D 5.5± 1 1.55 +0.1 C J T1 2 ± 0.5 16.5REF Po P1 Ao Ko t 4.0 2.0 6.5 2.10 0.3±0.05 J T1 T2 W P E 12.4 ± 0.2 2 ± 0.2 12± 0. 3 8± 0.1 1.75±0.1 P1 Ao Bo Ko t 2.0 ± 0.1 6.4 ± 0.1 5.2± 0. 1 12.75+ 0.15 2 ± 0.5 D1 Po 1.55+ 0.25 4.0 ± 0.1 T2 W 2.5 ± 025 16.0 ± 0.3 P E 8 1.75 2.1± 0.1 0.3±0.013 (mm) 4x4 Shipping Tray Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 26 www.anpec.com.tw APW7067N 4x4 Shipping Tray(Cont.) Cover Tape Dimensions Application SOP- 14 QSOP- 16 Carrier Width 24 12 Cover Tape Width 21.3 9.3 Devices Per Reel 2500 2500 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369 Copyright ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 27 www.anpec.com.tw