HM5117400B Series 4,194,304-word 4-bit Dynamic Random Access Memory ADE-203-369A (Z) Rev. 1.0 Nov. 15, 1995 Description The Hitachi HM5117400B is a CMOS dynamic RAM organized 4,194,304 word 4 bit. It employs the most advanced CMOS technology for high performance and low power. The HM5117400B offers Fast Page Mode as a high speed access mode. Features Single 5 V ( 10%) High speed Access time : 60 ns/ 70 ns/ 80 ns (max) Low power dissipation Active mode : 605 mW/550 mW/495 mW(max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) Fast page mode capability Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) 3 variations of refresh -only refresh -beforerefresh Hidden refresh Battery backup operation (L-version) Test function 16-bit parallel test mode This specification is fully compatible with the 16-Mbit DRAM specifications from TEXAS INSTRUMENTS. HM5117400B Series Ordering Information Type No. Access Time Package HM5117400BS-6 HM5117400BS-7 HM5117400BS-8 60 ns 70 ns 80 ns 300-mil 26-pin plastic SOJ (CP-26/24DB) HM5117400BLS-6 HM5117400BLS-7 HM5117400BLS-8 60 ns 70 ns 80 ns HM5117400BTS-6 HM5117400BTS-7 HM5117400BTS-8 60 ns 70 ns 80 ns HM5117400BLTS-6 HM5117400BLTS-7 HM5117400BLTS-8 60 ns 70 ns 80 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) Pin Arrangement HM5117400BS/BLS Series VCC 1 26 VSS VCC 1 26 VSS I/O1 2 25 I/O4 I/O1 2 25 I/O4 I/O2 3 24 I/O3 I/O2 3 24 I/O3 4 23 4 23 5 22 5 22 NC 6 21 A9 NC 6 21 A9 A10 8 19 A8 A10 8 19 A8 A0 9 18 A7 A0 9 18 A7 A1 10 17 A6 A1 10 17 A6 A2 11 16 A5 A2 11 16 A5 A3 12 15 A4 A3 12 15 A4 V 13 14 VSS VCC 13 14 VSS CC (Top view) 2 HM5117400BTS/BLTS Series (Top view) HM5117400B Series Pin Description Pin Name Function A0 to A10 Address input A0 to A10 Refresh address input I/O1 to I/O4 Data input/data output Row address strobe Column address strobe Write enable Output enable VCC Power supply (+5 V) VSS Ground NC No connection 3 HM5117400B Series Block Diagram Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O I/O 4 I/O 3 I/O Buffer 4 I/O Buffer 3 bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & Column decoder & driver Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Column decoder & driver bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & 256k memory Sense amp. & I/O Buffer 2 I/O Buffer 1 I/O 2 I/O 1 Address A0 to A10 4 I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O cell I/O bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus array bus HM5117400B Series Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to V SS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg –55 to +125 C Recommended DC Operating Conditions (Ta = 0 to +70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage VCC 4.5 5.0 5.5 V 1 Input high voltage VIH 2.4 — 6.5 V 1 Input low voltage VIL –1.0 — 0.8 V 1 Note: 1. All voltage referred to V SS DC Characteristics (Ta = 0 to +70 C, VCC = 5 V 10%, VSS = 0 V) HM5117400B -6 Parameter Operating current Standby current Standby current (L-version) Symbol Min *1, *2 -7 Max Min -8 Max Min Max Unit Test Conditions I CC1 — 110 — 100 — 90 mA t RC = min I CC2 — 2 — 2 — 2 mA TTL interface , = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface , V CC – 0.2V Dout = High-Z — 150 — 150 — 150 A CMOS interface , V CC – 0.2V Dout = High-Z I CC2 5 HM5117400B Series DC Characteristics (Ta = 0 to +70 C, VCC = 5 V 10%, VSS = 0 V) HM5117400B -6 Parameter Symbol Min -7 Max Min -8 Max Min Max Unit Test Conditions I CC3 — 110 — 100 — 90 mA t RC = min I CC5 — 5 — 5 — 5 mA = VIH, Dout = enable I CC6 — 110 — 100 — 90 mA t RC = min Fast page mode current *1, *3 I CC7 — 80 — 70 — 65 mA t PC = min Battery backup current I CC10 — 350 — 350 — 350 A CMOS interface Dout = High-Z CBR refresh: tRC = 62.5 s t RAS 0.3 s Input leakage current I LI –10 10 –10 10 –10 10 A 0V Output leakage current I LO –10 10 –10 10 –10 10 A 0 V Vout 7 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –5 mA Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 4.2 mA -only refresh current Standby current -beforecurrent *2 *1 refresh Vin = VIL 7V Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while = VIL. 3. Address can be changed once or less while = VIH. Capacitance (Ta = 25 C, V CC = 5 V 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. = VIH to disable Dout. 6 HM5117400B Series AC Characteristics (Ta = 0 to +70 C, VCC = 5 V 10%, VSS = 0 V)*1, *2, *18, *19 Test Conditions Input rise and fall time: 5 ns Input timing reference levels : 0.8 V, 2.4 V Output load : 2 TTL gate + CL (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5117400B -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Random read or write cycle time t RC 110 — 130 — 150 — ns precharge time t RP 40 — 50 — 60 — ns precharge time t CP 10 — 10 — 10 — ns pulse width t RAS 60 10000 70 10000 80 10000 ns pulse width t CAS 15 10000 18 10000 20 10000 ns Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 10 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 10 — 15 — 15 — ns t RCD 20 45 20 52 20 60 ns 3 to column address delay time t RAD 15 30 15 35 15 40 ns 4 hold time t RSH 15 — 18 — 20 — ns hold time t CSH 60 — 70 — 80 — ns to t CRP 5 — 5 — 5 — ns to Din delay time t OED 15 — 18 — 20 — ns 5 delay time from Din t DZO 0 — 0 — 0 — ns 6 t DZC 0 — 0 — 0 — ns 6 tT 3 50 3 50 3 50 ns 7 to delay time precharge time delay time from Din Transition time (rise and fall) 7 HM5117400B Series Read Cycle HM5117400B -6 Parameter Symbol Min Access time from t RAC Access time from -7 -8 Max Min Max Min Max Unit Notes — 60 — 70 — 80 ns 8, 9, 20 t CAC — 15 — 18 — 20 ns 9, 10, 17, 20 Access time from address t AA — 30 — 35 — 40 ns 9, 11, 17, 20 Access time from t OEA — 15 — 18 — 20 ns 9, 20 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to t RCH 0 — 0 — 0 — ns 12 Read command hold time to t RRH 0 — 0 — 0 — ns 12 Column address to lead time t RAL 30 — 35 — 40 — ns Column address to lead time t CAL 30 — 35 — 40 — ns t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 15 — 15 — 15 ns 13 Output buffer turn-off to t OEZ — 15 — 15 — 15 ns 13 t CDD 15 — 18 — 20 — ns 5 Max Unit Notes to output in low-Z to Din delay time Write Cycle HM5117400B -6 -7 -8 Parameter Symbol Min Max Min Write command setup time t WCS 0 — 0 — 0 — ns Write command hold time t WCH 10 — 15 — 15 — ns Write command pulse width t WP 10 — 10 — 10 — ns Write command to lead time t RWL 15 — 18 — 20 — ns Write command to lead time t CWL 15 — 18 — 20 — ns Data-in setup time t DS 0 — 0 — 0 — ns 15 Data-in hold time t DH 10 — 15 — 15 — ns 15 8 Max Min 14 HM5117400B Series Read-Modify-Write Cycle HM5117400B -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Read-modify-write cycle time t RWC 155 — 181 — 205 — ns to delay time t RWD 85 — 98 — 110 — ns 14 to delay time t CWD 40 — 46 — 50 — ns 14 t AWD 55 — 63 — 70 — ns 14 t OEH 15 — 18 — 20 — ns Column address to delay time hold time from Refresh Cycle HM5117400B -6 Parameter Symbol Min -7 -8 Max Min Max Min Max Unit Notes setup time (CBR refresh cycle) t CSR 5 — 5 — 5 — ns hold time (CBR refresh cycle) t CHR 10 — 10 — 10 — ns setup time (CBR refresh cycle) t WRP 0 — 0 — 0 — ns hold time (CBR refresh cycle) t WRH 10 — 10 — 10 — ns t RPC 0 — 0 — 0 — ns precharge to hold time Fast Page Mode Cycle HM5117400B -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode cycle time t PC 40 — 45 — 50 — ns Fast page mode pulse width t RASP — 100000 — Access time from precharge t CPA — 35 — 40 35 — 40 — hold time from precharge t CPRH 100000 — 100000 ns 16 — 45 ns 9, 17, 20 45 — ns 9 HM5117400B Series Fast Page Mode Read-Modify-Write Cycle HM5117400B -6 -7 -8 Parameter Symbol Min Max Min Max Min Max Unit Notes Fast page mode read-modify-write cycle time t PRWC 85 — 96 — 105 — ns 60 — 68 — 75 — ns delay time from precharge t CPW 14 Test Mode Cycle *19 HM5117400B -6 Parameter -7 -8 Symbol Min Max Min Max Min Max Unit Notes Test mode setup time t WTS 0 — 0 — 0 — ns Test mode hold time t WTH 10 — 10 — 10 — ns Refresh Parameter Symbol Max Unit Note Refresh period t REF 32 ms 2048 cycles Refresh period (L-version) t REF 128 ms 2048 cycles Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing -only refresh or -beforerefresh). If the internal refresh counter is used, a minimum of eight -beforerefresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 10 HM5117400B Series 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + t CAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS, t RWD, t CWD, t AWD and t CPW are not restrictive operationg parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to leading edge in early write cycles and to leading edge in delayed write or read-modify-write cycles. 16. t RASP defines pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA, t CAC and t CPA. must disable output buffer prior to applying data to 18. In delayed write or read-modify-write cycles, the device. After is reset, if tOEH tCWL, the I/O pin will remain open circuit (high impedance); if tOEH < tCWL, invalid data will be out at each I/O. 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M 4 are don’t care during test mode. Test mode is set by performing -and-before(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. -beforeTo get out of test mode and enter a normal operation mode, perform either a regular refresh cycle or -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , t AA, t CAC and t CPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 21 XXX: H or L (H: V IH (min) VIN V IH (max), L: VIL (min) V IN V IL (max)) ///////: Invalid Dout 11 HM5117400B Series Timing Waveforms *21 Read Cycle t RC t RAS t RP t CSH t CRP t RCD t RSH t CAS tT t RAD t ASR Address t RAH t RAL t ASC t CAL t CAH Column Row t RRH t RCH t RCS t DZC t CDD High-Z Din t DZO t OEA t OED t OEZ t CAC t OHO t AA t OFF t RAC t CLZ Dout 12 t OH Dout HM5117400B Series Early Write Cycle t RC t RAS t RP t CSH t CRP t RCD t RSH t CAS tT t ASR Address t RAH Row t ASC t CAH Column t WCS t WCH t DS Din Dout t DH Din High-Z** * ** t WCS : H or L t WCS (min) 13 HM5117400B Series Delayed Write Cycle*18 t RC t RAS t RP t CRP t CSH t RCD t RSH t CAS tT t ASR Address t RAH t ASC Row t CAH Column t CWL t RWL t WP t RCS t DZC Din t DS High-Z t DH Din t DZO t OEH t OED t OEZ t CLZ High-Z Dout Invalid Dout 14 HM5117400B Series Read-Modify-Write Cycle*18 t RWC t RAS t RP tT t RCD t CAS t CRP t RAD t ASR Address tRAH t ASC Row t CAH Column t RCS t CWD tCWL t AWD t RWL t RWD t WP t DZC t DH t DS High-Z Din Din t OED t DZO t OEH t OEA t CAC t OEZ t AA t RAC t OHO Dout Dout High-Z t CLZ 15 HM5117400B Series -Only Refresh Cycle t RC t RAS t RP tT t CRP t RPC t ASR Address t CRP t RAH Row t OFF Dout High-Z * Refresh Address A0 - A10 (RA0 - RA10) ** 16 , : H or L HM5117400B Series -Before- Refresh Cycle t RC t RP t RPC t RAS t CSR t RP t CHR t RPC t CRP tT t CP t WRP t WRH t CP Address t OFF Dout High-Z * : H or L 17 HM5117400B Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP tT t RSH t CHR t CRP t RCD t RAD t ASC t ASR t RAH Address t RAL Row t CAH Column t WRP t RRH t RCS t WRH t WRP t DZC t WRH t CDD High-Z Din t DZO t OED t OEA t CAC t OEZ t OHO t AA t RAC t OFF t OH t CLZ Dout 18 Dout HM5117400B Series Fast Page Mode Read Cycle t RASP t CPRH t RP tT t PC t CSH t RCD t RAD t ASR t RAH Address Row t CAS t CP t RSH t CP t CAS t RAL t CAL t CAL t ASC t CAH t CAL t ASC t CAH t ASC t CAH Column 1 Column 2 Column N t RCS tRCS tRCH t DZC Din t DZO t RRH t CDD High-Z High-Z t OED t DZO t OED t CPA t OH t AA t OEA t RCH t DZC t CDD t AA t OHO t CDD High-Z t DZO t OH t OEA t OFF t CAC t OEZ t CLZ t CAC t CLZ Dout t RCS tRCH t DZC t RAC t CRP t CAS Dout 1 t CPA t AA t OHO t OFF t OEZ Dout 2 t OED t OH t OHO t OEA t CAC t CLZ t OFF t OEZ Dout N 19 HM5117400B Series Fast Page Mode Early Write Cycle t RASP t RP tT t CSH t RCD t CAS t ASR t RAH Address Row t RSH t CAS t CP t ASC t CAH t ASC t CAH Column 1 Column 2 Column N t DS Dout t CAS t ASC t CAH t WCS Din t PC t CP t WCH t DH Din 1 t WCS t DS t WCH t DH Din 2 t WCS t WCH t DS t DH Din N High-Z** * ** t WCS 20 t CRP : H or L t WCS (min) HM5117400B Series Fast Page Mode Delayed Write Cycle *18 t RASP t RP tT t CP t CSH t RCD t CRP t CP t PC t CAS t RSH t CAS t CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL Column N t CWL t CWL t RWL t RCS t RCS t WP t DZC t DS t RCS t WP t DZC t DS t WP t DZC t DS t DH t DH Din 1 Din t DZO t DH Din 2 t DZO t OED Din N t DZO t OED t OED t OEH t CLZ t OEH t CLZ t OEZ t OEH t CLZ t OEZ t OEZ High-Z Dout Invalid Dout Invalid Dout Invalid Dout 21 HM5117400B Series Fast Page Mode Read-Modify-Write Cycle *18 t RASP t RP tT t PRWC t CP t RCD t RSH t CP t CAS t CAS t CRP t CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 Column 2 t RWD t CWL Column N t CPW t AWD t CWL t AWD t CWD t RCS t ASC t CAH t RCS t WP t DZC t DS t DZC t DS t DH t DH Din 1 Din t DZO t OED t OED t OEH t OEZ t OEH t OHO t OHO t OEA t CAC t AA t CPA t CLZ t OED t DZO t OEA t CAC t AA Din N t OEH t OHO t RAC t DH Din 2 t DZO t OEA t CAC t RWL t CWD t WP t DZC t DS t CWL t AWD t RCS t CWD t WP t CPW t AA t CPA t OEZ t CLZ t OEZ t CLZ High-Z Dout Dout 1 22 Dout 2 Dout N HM5117400B Series Test Mode Cycle *19 Set Cycle** Test Mode Cycle *,** Reset Cycle * CBR or Normal Mode -only refresh ** Address, Din, : H or L 23 HM5117400B Series Test Mode Set Cycle t RC t RP t RPC t RAS t CSR t RP t CHR t RPC tT t CP t WTS t WTH t CP Address t OFF Dout 24 High-Z t CRP HM5117400B Series Package Dimensions HM5117400BS/BLS Series (CP-26/24DB) 26 1 Unit: mm 16.90 17.27 Max 21 19 6 8 0.74 14 13 1.30 Max 0.43 ± 0.10 2.54 6.71 ± 0.25 1.27 0.10 HM5117400BTS/BLTS Series (TTP-26/24DA) 14 7.62 26 17.14 17.54 Max 21 19 Unit: mm 1 68 1.27 0.40 ± 0.10 0.21 13 9.22 ± 0.2 M 0.08 Min 0.18 Max 1.15 Max +0.075 0.10 0.145 -0.025 1.20 Max 0 – 5° 0.68 0.50 ± 0.10 25