ICmic TM This X24320 device has been acquired by IC MICROSYSTEMS from Xicor, Inc. IC MICROSYSTEMS 4K x 8 Bit X24320 32K 2 400KHz 2-Wire Serial E PROM with Block Lock FEATURES TM DESCRIPTION 2 The X24320 is a CMOS Serial E PROM, internally organized 4K x 8. The device features a serial inter- •Save Critical Data with Programmable Block Lock Protection 2 —Block Lock (0, 1/4, 1/2, or all of E PROM Array) —Software Write Protection face and software protocol allowing operation on a simple two wire bus. The bus operates at 400 KHz all the way down to 1.8V. —Programmable Hardware Write Protect •In Circuit Programmable ROM Mode •400KHz 2-Wire Serial Interface Three device select inputs (S0–S2) allow up to eight devices to share a common two wire bus. —Schmitt Trigger Input Noise Suppression —Output Slope Control for Ground Bounce A Write Protect Register at the highest address location, FFFFh, provides three write protection features: Software Write Protect, Block Lock Protect, and Programmable Hardware Write Protect. The Software Noise Elimination •Longer Battery Life With Lower Power —Active Read Current Less Than 1mA —Active Write Current Less Than 3mA —Standby Current Less Than 1µA •1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power Supply Versions •32 Word Page Write Mode —Minimizes Total Write Time Per Word Write Protect feature prevents any nonvolatile writes to the device until the WEL bit in the Write Protect Register is set. The Block Lock Protection feature gives the user four array block protect options, set by programming two bits in the Write Protect Register. The Programmable Hardware Write Protect feature allows the user to install the device with WP tied to VCC, write to and Block Lock the desired portions of •Internally Organized 4K x 8 •Bidirectional Data Transfer Protocol •Self-Timed Write Cycle the memory array in circuit, and then enable the In Circuit Programmable ROM Mode by programming the —Typical Write Cycle Time of 5ms •High Reliability —Endurance: 100,000 Cycles —Data Retention: 100 Years WPEN bit HIGH in the Write Protect Register. After this, the Block Locked portions of the array, including the Write Protect Register itself, are permanently protected from being erased. •8-Lead SOIC •14-Lead TSSOP •8-Lead PDIP FUNCTIONAL DIAGRAM DATA REGISTER 2 SERIAL E PROM DATA AND ADDRESS (SDA) Y DECODE LOGIC SCL 2 COMMAND DECODE AND CONTROL PAGE DECODE SERIAL E PROM ARRAY 4K x 8 LOGIC LOGIC 1K x 8 BLOCK LOCK AND WRITE PROTECT CONTROL LOGIC 1K x 8 S2 S1 DEVICE SELECT WRITE PROTECT LOGIC REGISTER 2K x 8 S0 WRITE VOLTAGE CONTROL WP 7035 FM 01 Xicor, 1995, 1996 Patents Pending 7035-1.2 4/25/97 T0/C2/D0 SH 1 Characteristics subject to change without notice X24320 2 PIN NAMES Xicor E PROMs are designed and tested for applications requiring extended endurance. Inherent data Symbol retention is greater than 100 years. Description S0, S1, S2 Device Select Inputs PIN DESCRIPTIONS Serial Clock (SCL) SDA Serial Data SCL Serial Clock The SCL input is used to clock all data into and out of the device. WP Write Protect VSS Ground Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. VCC Supply Voltage NC No Connect 7035 FM T01 PIN CONFIGURATION An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the Pull- Not to scale up resistor selection graph at the end of this data sheet. 8-Lead DIP/SOIC Device Select (S0, S1, S2) The device select inputs (S0, S1, S2) are used to set the first three bits of the 8-bit slave address. This * .197” S 0 1 8 S 2 7 S 1 2 V SS allows up to eight devices to share a common bus. These inputs can be static or actively driven. If used statically they must be tied to VSS or VCC as appropriate. If actively driven, they must be driven with CMOS levels (driven to VCC or VSS). X24320 6 3 4 5 V CC WP SCL SDA * .244” 14-Lead TSSOP S 0 1 14 S 2 13 3 4 X24320 11 NC NC 5 10 NC 6 9 SCL 7 8 SDA 1 NC Write Protect (WP) The Write Protect input controls the Hardware Write Protect feature. When held LOW, Hardware Write Protection is disabled. When this input is held HIGH, and the WPEN bit in the Write Protect Register is set .200” NC NC S 2 V SS HIGH, the Write Protect Register is protected, preventing changes to the Block Lock Protection and 12 V CC WP .252” WPEN bits. * SOIC Measurement 2 7035 FM 02 X24320 Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. Refer to Figures 1 and 2. DEVICE OPERATION The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers Start Condition All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL and provide the clock for both transmit and receive operations. Therefore, the device will be is HIGH. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. considered a slave in all applications. Figure 1. Data Validity SCL SDA DATA STABLE DATA CHANGE 7035 FM 03 Figure 2. Definition of Start and Stop SCL SDA START BIT STOP BIT 3 7035 FM 04 X24320 when SCL is HIGH. The stop condition is also used to place the device into the standby power mode after a The device will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word. read sequence. A stop condition can only be issued after the transmitting device has released the bus. In the read mode the device will transmit eight bits of data, release the SDA line and monitor the line for an Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. If an acknowledge is not detected, the device will terminate further data trans- Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after trans- mitting eight bits. During the ninth clock cycle the missions. The master must then issue a stop condition return the device to the standby power mode and place the device into a known state. receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 3. Figure 3. Acknowledge Response From Receiver SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 7035 FM 05 4 to X24320 device select input pins. If the compare is not successful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode. DEVICE ADDRESSING Following a start condition, the master must output the address of the slave it is accessing. The first four bits of the Slave Address Byte are the device type identifier bits. These must equal “1010”. The next 3 bits are the device select bits S0, S1, and S2. This allows up to 8 devices to share a single bus. These bits are The word address is either supplied by the master or obtained from an internal counter, depending on the operation. The master must supply the two Word Address Bytes as shown in figure 4. compared to the S0, S1, and S2 device select input pins. The last bit of the Slave Address Byte defines the 2 The internal organization of the E array is 128 pages by 32 bytes per page. The page address is partially operation to be performed. When the R/W bit is a one, then a read operation is selected. When it is zero then contained in the Word Address Byte 1 and partially in bits 7 through 5 of the Word Address Byte 0. The byte a write operation is selected. Refer to figure 4. After loading the Slave Address Byte from the SDA bus, the address is contained in bits 4 through 0 of the Word Address Byte 0. See figure 4. device compares the device type bits with the value “1010” and the device select bits with the status of the Figure 4. Device Addressing DEVICE SELECT DEVICE TYPE IDENTIFIER 1 0 1 S 2 0 S 1 S 0 R/W SLAVE ADDRESS BYTE HIGH ORDER WORD ADDRESS 0 0 0 0 A11 A10 A9 A8 X24320 WORD ADDRESS BYTE 1 LOW ORDER WORD ADDRESS A7 A6 A5 A4 A3 A2 A1 A0 D1 D0 WORD ADDRESS BYTE 0 D7 D6 D5 D4 D3 DATA BYTE 5 D2 7035 FM 06 X24320 master can transmit up to thirty-one more words. The device will respond with an acknowledge after the WRITE OPERATIONS Byte Write receipt of each word, and then the byte address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to the first byte of the current page. This means that the master can write 32 words to the page beginning at any byte. For a write operation, the device requires the Slave Address Byte, the Word Address Byte 1, and the Word Address Byte 0, which gives the master access to any one of the words in the array. Upon receipt of the Word Address Byte 0, the device responds with an acknowledge, and waits for the first eight bits of data. After If the master begins writing at byte 16, and loads 32 words, then the first 16 words are written to bytes 16 receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle through 31, and the last 16 words are written to bytes 0 through 15. Afterwards, the address counter would point to byte 16. If the master writes more than 32 words, then the previously loaded data is overwritten by the new data, one byte at a time. to the nonvolatile memory. While the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests from the master. The SDA pin is at high impedance. See figure 5. The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of Page Write The device is capable of a thirty-two byte page write operation. It is initiated in the same manner as the byte the internal write cycle. Refer to figure 6 for the address, acknowledge, and data transfer sequence. write operation; but instead of terminating the write operation after the first data word is transferred, the Figure 5. Byte Write Sequence S T SIGNALS FROM THE MASTER A R WORD ADDRESS BYTE 1 SLAVE ADDRESS WORD ADDRESS BYTE 0 S T DATA O P T SDA BUS S1010 0 SIGNALS FROM THE SLAVE P A C A C A C A C K K K K 7035 FM 07 Figure 6. Page Write Sequence (0=n=31) SIGNALS FROM THE MASTER S T A R WORD ADDRESS BYTE 1 SLAVE ADDRESS DATA (n) DATA (0) WORD ADDRESS BYTE 0 S T O P T SDA BUS SIGNALS FROM THE SLAVE S 1010 0 P A C A C A C A C A C K K K K K 7035 FM 08 6 X24320 Acknowledge Polling The maximum write cycle time can be significantly reduced using Acknowledge Polling. To initiate READ OPERATIONS Acknowledge Polling, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the internal write cycle, then no ACK will be returned. If the the Slave Address Byte is set to one. There are three basic read operations: Current Address Reads, Random Reads, and Sequential Reads. device has completed the internal write operation, an ACK will be returned and the host can then proceed Current Address Read Internally, the device contains an address counter that maintains the address of the last word read or written Read operations are initiated in the same manner as write operations with the exception that the R/W bit of with the read or write operation. Refer to figure 7 . incremented by one. After a read operation from the last address in the array, the counter will “roll over” to the first address in the array. After a write operation to the last address in a given page, the counter will “roll Figure 7. Acknowledge Polling Sequence BYTE LOAD COMPLETED BY ISSUING STOP. over” to the first address on the same page. ENTER ACK POLLING Upon receipt of the Slave Address Byte with the R/W bit set to one, the device issues an acknowledge and then transmits the eight bits of the Data Byte. The master terminates the read operation when it does not ISSUE START respond with an acknowledge during the ninth clock and then issues a stop condition. Refer to figure 8 for the address acknowledge, and data transfer sequence. ISSUE SLAVE ADDRESS BYTE ISSUE STOP (READ OR WRITE) ACK RETURNED? It should be noted that the ninth clock cycle of the read operation is not a “don’t care " .” To terminate a read operation, the master must either issue a stop condition during the ninth cycle or hold SDA HIGH during the ninth clock cycle and then issue a stop condition. NO YES HIGH VOLTAGE CYCLE COMPLETE. CONTINUE Figure 8. Current Address Read Sequence NO SEQUENCE? SIGNALS FROM THE MASTER YES A R S T SLAVE ADDRESS O P T SDA BUS CONTINUE NORMAL READ OR WRITE S T ISSUE STOP SIGNALS FROM THE SLAVE COMMAND SEQUENCE S 1 01 0 1 P A C K DATA 7035 FM 10 PROCEED 7035 FM 09 7 X24320 Random Read Random read operation allows the master to access any memory location in the array. Prior to issuing the The next Current Address Read operation will read from the newly loaded address. Slave Address Byte with the R/W bit set to one, the master must first perform a “Dummy” write operation. The master issues the start condition and the Slave Address Byte with the R/W bit low, receives an Sequential Read Sequential reads can be initiated as either a current address read or random read. The first Data Byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating acknowledge, then issues the Word Address Byte 1, receives another acknowledge, then issues the Word it requires additional data. The device continues to output data for each acknowledge received. The Address Byte 0. After the device acknowledges receipt of the Word Address Byte 0, the master issues another start condition and the Slave Address Byte with the R/W bit set to one. This is followed by an acknowledge master terminates the read operation by not with an acknowledge and then issuing a stop condition. responding and then eight bits of data from the device. The master terminates the read operation by not responding with The data output is sequential, with the data from address n followed by the data from address n + 1. The address an acknowledge and then issuing a stop condition. Refer to figure 9 for the address, acknowledge, and data transfer sequence. counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. At the end of the address space the counter “rolls over ” to address 0000h and the device continues to output data for each acknowledge received. Refer to figure 10 for the acknowledge and The device will perform a similar operation called “Set Current Address” if a stop is issued instead of the second start shown in figure 9. The device will go into standby mode after the stop and all bus activity will be data transfer sequence. ignored until a start is detected. The effect of this operation is that the new address is loaded into the address counter, but no data is output by the device. Figure 9. Random Read Sequence SIGNALS FROM THE MASTER S T A R WORD ADDRESS BYTE 1 SLAVE ADDRESS S T WORD ADDRESS BYTE 0 A R T SDA BUS SLAVE ADDRESS S T O P T S1 0 1 0 0 SIGNALS FROM THE SLAVE 1 S P A C A C A C A C K K K K DATA 7035 FM 11 Figure 10. Sequential Read Sequence SIGNALS FROM THE MASTER SLAVE ADDRESS SDA BUS S SIGNALS FROM THE SLAVE A C A C A C K K K S T O P 1 P A C K DATA (1) DATA (2) DATA (n–1) DATA (n) (n is any integer greater than 1) 7035 FM 12 8 X24320 WRITE PROTECT REGISTER (WPR) Writing to the Write Protect Register WPEN: Write Protect Enable Bit (Nonvolatile) The Write Protect (WP) pin and the Write Protect Enable (WPEN) bit in the Write Protect Register The Write Protect Register can only be modified by performing a “ByteWrite” operation directly to the address FFFFh as described below. control the Programmable Hardware Write Protection feature. Hardware Write Protection is enabled when the WP pin is HIGH and the WPEN bit is HIGH, and disabled when either the WP pin is LOW or the WPEN The Data Byte must contain zeroes where indicated in the procedural descriptions below; otherwise the oper- bit is LOW. Figure 12 defines the write protect status for each combination of WPEN and WP. When the ation will not be performed. Only one Data Byte is allowed for each register write operation. The part will not acknowledge any data bytes after the first byte is entered. The user then has to issue a stop to initiate chip is Hardware Write Protected, nonvolatile writes are disabled to the Write Protect Register, including the Block Lock Protect bits and the WPEN bit itself, as well as to the Block Lock protected sections in the memory array. Only the sections of the memory array that are not Block Lock protected, and the volatile bits WEL and RWEL, can be written. the nonvolatile write cycle that writes BL0, BL1, and WPEN to the nonvolatile bits. A stop must also be issued after volatile register write operations to put the device into Standby. The state of the Write Protect Register can be read by performing a random byte read at FFFFh at any time. In Circuit Programmable ROM Mode Note that when the WPEN bit is write protected, it cannot be changed back to a LOW state; so write The part will reset itself after the first byte is read. The master should supply a stop condition to be consistent protection is enabled as long as the WP pin is held HIGH. Thus an In Circuit Programmable ROM function can be implemented by hardwiring the WP pin to VCC, writing to and Block Locking the desired portion of the with the protocol, but a stop is not required to end this operation. After the read, the address counter contains 0000h. array to be ROM, and then programming the WPEN bit HIGH. Write Protect Register: WPR (ADDR = FFFFh) 7 6 5 4 3 WPEN 0 0 BL1 BL0 2 1 RWEL WEL 0 Unused Bit Positions Bits 0, 5 & 6 are not used. All writes to the WPR must have zeros in these bit positions. The data byte output during a WPR read will contain zeros in these bits. 0 WEL: Write Enable Latch (Volatile) 0 = Write Enable Latch reset, writes disabled. Writing to the WEL and RWEL bits WEL and RWEL are volatile latches that power up in the LOW (disabled) state. While the WEL bit is LOW, 1 = Write Enable Latch set, writes enabled. writes to any address other than FFFFh will be ignored (no acknowledge will be issued after the Data Byte). RWEL: Register Write Enable Latch (Volatile) 0 = Register Write Enable Latch reset, writes to the Write Protect Register disabled. The WEL bit is set by writing 00000010 to address FFFFh. Once set, WEL remains HIGH until either it is reset to 0 (by writing 00000000 to FFFFh) or until the part powers up again. Writes to WEL and RWEL do 1 = Register Write Enable Latch set, writes to the Write Protect Register enabled. not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. BL0, BL1: Block Lock Protect Bits (Nonvolatile) The Block Lock Protect Bits, BL0 and BL1, determine which blocks of the array are protected. A write to a protected block of memory is ignored, but will receive an acknowledge. The master must issue a stop to put the part into standby, just as it would for a valid write; The RWEL bit controls writes to the Block Lock Protect bits, BL0 and BL1, and the WPEN bit. If RWEL is 0 but the stop will not initiate an internal nonvolatile write cycle. See figure 11. after any nonvolatile write, including writes to the Block Lock Protect bits, WPEN bit, or any bytes in the memory array. When RWEL is set, WEL cannot be then no writes can be performed on BL0, BL1, or WPEN. RWEL is reset when the device powers up or 9 X24320 reset, nor can RWEL and WEL be reset in one write operation. RWEL can be reset by writing 00000010 to step 2. RWEL is reset to zero in step 3 so that user is required to perform steps 2 and 3 to make another change. RWEL must be 0 in step 3. If the RWEL bit in the data byte for step 3 is a one, then no changes are FFFFh; but this is the same operation as in step 3 described below, and will result in programing BL0, BL1, and WPEN. made to the Write Protect Register and the device remains at step 2. Writing to the BL and WPEN Bits A 3 step sequence is required to change the nonvola- tile Block Lock Protect or Write Protect Enable bits: 1) Set WEL=1, Write 00000010 to address FFFFh (Volatile Write Cycle.) The WP pin must be LOW or the WPEN bit must be LOW before a nonvolatile register write operation is initiated. Otherwise, the write operation will abort and the device will go into standby mode after the master issues the stop condition in step 3. 2) Set RWEL=1, Write 00000110 to address FFFFh (Volatile Write Cycle.) Step 3 is a nonvolatile write operation, requiring tWC to complete (acknowledge polling may be used to reduce this time requirement). It should be noted that step 3 MUST end with a stop condition. If a start condition is 3) Set BL1, BL0, and/or WPEN bits, Write u00xy010 to address FFFFh, where u=WPEN, x=BL1, and y=BL0. (Nonvolatile Write Cycle.) issued during or at the end of step 3 (instead of a stop condition) the device will abort the nonvolatile register The three step sequence was created to make it diffi cult to change the contents of the Write Protect Register accidentally. If WEL was set to one by a write and remain at step 2. If the operation is aborted with a start condition, the master must issue a stop to put the device into standby mode. previous register write operation, the user may start at ABSOLUTE MAXIMUM RATINGS* Figure 11. Block Lock Protect Bits and Protected Addresses BL1 BL0 Protected Addresses Array Location 0 0 None No Protect 0 1 C00h - FFFh Upper 1/4 1 0 800h - FFFh Upper 1/2 1 1 000h - FFFh Full Array 7003 FRM T02 Figure 12. WP Pin and WPEN Bit Functionality WP WPEN Memory Array Not Lock Block Protected 0 X Writable X 0 1 1 Memory Array Block Lock Protected Block Lock Bits WPEN Bit Protected Unprotected Unprotected Writable Protected Unprotected Unprotected Writable Protected Protected Protected 7003 FRM T03 10 X24320 Temperature under Bias X24320 ....................................... –65°C to +135°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation Storage Temperature ........................ –65°C to +150°C Voltage on any Pin with Respect to VSS .................................... –1V to +7V D.C. Output Current ..............................................5mA Lead Temperature (Soldering, .............................. 300°C 10 seconds) of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Supply Voltage Limits Temperature Min. Max. X24320 4.5V to 5.5V Commercial 0°C +70°C 2.5V to 5.5V Industrial –40°C +85°C X24320–2. 5 X24320–1. 1.8V to 3.6V 8 7003 FRM T04 7003 FRM T05 D.C. OPERATING CHARACTERISTICS Limits Symbol Parameter Min. Max. Units ICC1 VCC Supply Current (Read) 1 mA ICC2 VCC Supply Current (Write) 3 mA ISB1 (1) VCC Standby Current 5 ∝A 1 ∝A Test Conditions SCL = VCC X 0.1/VCC X 0.9 Levels @ 400KHz, SDA = Open, All Other Inputs = VSS or VCC – 0.3V SCL = SDA = VCC, All Other Inputs = VSS or VCC – 0.3V, VCC = 5V ± 10% ISB2 (1) VCC Standby Current SCL = SDA = VCC, All Other Inputs = VSS or VCC – 0.3V, VCC = 2.5V ILI Input Leakage Current 10 ∝A VIN = VSS to VCC ILO Output Leakage Current 10 ∝A VOUT = VSS to VCC VlL (2) Input LOW Voltage –0.5 VCC x 0.3 V VIH (2) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VOL Output LOW Voltage 0.4 V Vhys (3) Hysteresis of Schmitt Trigger Inputs VCC x 0.05 IOL = 3mA V 7003 FRM T06 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V Symbol Parameter Max. Units Test Conditions CI/O (3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN (3) Input Capacitance (S0, S1, S2, SCL, WP) 6 pF VIN = 0V 7003 FRM T07 Notes: (1)Must perform a stop command prior to measurement. (2)VIL min. and VIH max. are for reference only and are not 100% tested. (3)This parameter is periodically sampled and not 100% tested. 11 X24320 EQUIVALENT A.C. LOAD CIRCUIT A.C. CONDITIONS OF TEST VCC x 0.1 to VCC x 0.9 Input Pulse Levels Input Rise and Fall Times 5V 10ns Input and Output Timing Levels 1.53KΟ OUTPUT VCC X 0.5 7003 FRM T08 100pF 7035 FM 13 A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits Symbol Parameter Min. Max. Units 0 400 KHz fSCL SCL Clock Frequency tI Noise Suppression Time Constant at SCL, SDA Inputs 50 tAA SCL LOW to SDA Data Out Valid 0.1 tBUF Time the Bus Must Be Free Before a New Transmission Can Start 1.2 ∝s tHD:STA Start Condition Hold Time 0.6 ∝s tLOW Clock LOW Period 1.2 ∝s tHIGH Clock HIGH Period 0.6 ∝s tSU:STA Start Condition Setup Time a Repeated Start Condition) 0.6 ∝s tHD:DAT Data In Hold Time 0 ∝s tSU:DAT Data In Setup Time 100 ns tR SDA and SCL Rise Time 300 ns tF SDA and SCL Fall Time 300 ns tSU:STO Stop Condition Setup Time 0.6 tDH Data Out Hold Time 50 tOF Output Fall Time (for ns ∝s 0.9 ∝s 300 ns 20+0.1Cb (5) 7003 FRM T09 POWER-UP TIMING (4) Symbol Parameter Max. Units tPUR Power-up to Read Operation 1 ms tPUW Power-up to Write Operation 5 ms 7003 FRM T10 Notes: (4)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. 12 X24320 Bus Timing t t F t HIGH t LOW R SCL t t SU:STA HD:STA t t HD:DAT t SU:DAT SU:STO SDA IN t t AA t DH BUF SDA OUT 7035 FM 14 Write Cycle Limits Symbol tWC Parameter (6) (5) Min. Typ. Write Cycle Time 5 Max. Units 10 ms 7003 FRM T11 Notes: (5)Typical values are for TA = 25°C and nominal supply voltage (5V). (6)tWR is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. During the write cycle, the X24320 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the device does not respond to its slave address. Bus Timing SCL SDA ACK 8th BIT WORD n t WC STOP CONDITION RESISTANCE (KΟ) WAVEFORM V R MIN 100 80 = R MAX = CC MAX I OL MIN =1.8KΟ t R C BUS MAX. RESISTANCE 60 40 20 MIN. RESISTANCE 0 0 20 40 60 80 100120 BUS CAPACITANCE (pF) 7035 FM 15 SYMBOL TABLE Guidelines for Calculating Typical Values of Bus Pull-Up Resistors 120 START CONDITION 7035 FM 16 INPUTS OUTPUTS Must be steady Will be steady May change from Low to Will change from Low to High High May change from High to Will change from High to Low Low Don’t Care: Changes Changing: State Not Allowed N/A Known Center Line is High Impedance 13 7035 FM 17 X24320 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) PIN 1 INDEX PIN 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25) 0.050 (1.27) 0.050" TYPICAL 0.010 (0.25) X 45° 0.020 (0.50) 0.050" TYPICAL 0° – 8° 0.0075 (0.19) 0.010 (0.25) 0.250" 0.016 (0.410) 0.037 (0.937) 0.030" TYPICAL FOOTPRINT 8 PLACES NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 7035 FM 19 14 X24320 PACKAGING INFORMATION 14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V .025 (.65) BSC .169 (4.3) .177 (4.5) .252 (6.4) BSC .193 (4.9) .200 (5.1) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15) .010 (.25) Gage Plane 0° – 8° Seating Plane .019 (.50) .029 (.75) Detail A (20X) .031 (.80) .041 (1.05) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 7035 FM 20 15 X24320 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 0.430 (10.92) 0.360 (9.14) 0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.060 (1.52) 0.020 (0.51) 0.145 (3.68) 0.128 (3.25) SEATING PLANE 0.025 (0.64) 0.015 (0.38) 0.150 (3.81) 0.125 (3.18) 0.065 (1.65) 0.045 (1.14) 0.110 (2.79) 0.090 (2.29) 0.015 (0.38) MAX. TYP . 0.020 (0.51) 0.016 (0.41) 0.325 (8.25) 0.300 (7.62) 0° 15° 0.010 (0.25) NOTE: 1.ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 7040 FM 18 16 X24320 ORDERING INFORMATION X24320 P T G -V Device VCC Range Blank = 5V ±10% 2.5 = 2.5V to 5.5V 1.8 = 1.8V to 3.6V G=RoHS Compliant Lead Free package Blank = Standard package. Non lead free Temperature Range Blank = 0°C to +70°C I = –40°C to +85°C Package X24320 S8 = 8-Lead SOIC V14 = 14-Lead TSSOP P = 8-Lead PDIP Part Mark Convention X24320 XG X Blank = 8-Lead SOIC V = 14-Lead TSSOP P = 8-Lead PDIP G = RoHS compliant lead free Blank = 4.5V to 5.5V, 0°C to +70°C I = 4.5V to 5.5V, –40°C to +85°C AE = 2.5V to 5.5V, 0°C to +70°C AF = 2.5V to 5.5V, –40°C to +85°C AG = 1.8V to 3.6V, 0°C to +70°C AH = 1.8V to 3.6V, –40°C to +85°C LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 17