STP2230SOP
July 1997
XB1
DATA SHEET
Crossbar Switch
DESCRIPTION
The STP2230SOP crossbar switch [1] acts as the bridge among three UltraSPARC UPA devices. One of
the buses is dedicated to interfacing to system memory, while the other two are general-purpose
buses. These buses are used for interfacing memory, a processor bus, and an I/O bus. In this particular configuration, eighteen XB1s are required per system implementation.
FEATURES
• Three-port crossbar
- 16-bit data
- 8-bit processor
- 4-bit data ports
• Decoupled memory port; loading and unloading of memory data can take place in parallel with other operations
• Burst transfers operate on four bytes of data per slice
• Power-up safe buses; all buses power up tristated so there will be no bus contention with other parts which may
be on the buses
• Implemented in 0.8-micron BiCMOS and housed in a 48-pin TSSOP package (also called DGG or “shrink-wide
bus”)
1. The STP2230SOP crossbar switch is also referred to as BMX.
1
XB1
Crossbar Switch
STP2230SOP
BLOCK, LOGIC, AND TYPICAL APPLICATION DIAGRAMS
Chip Boundary
IMR_DATA[3:0]
A_BUS[15:0]
IMW_DATA[3:0]
Memory
Data
Interface
Block
MRB_CTRL
MWB_CTRL
I/O
Data
Interface
Block
PW_DATA[7:0]
PIR_DATA[7:0]
X_MIE
X_MIO
X_MPE
SYS_CLK
Command Decode Block
X_MPO
BMX_CMD[3:0]
C_BUS[3:0]
PMR_DATA[7:0]
Processor
Data
Interface
Block
B_BUS[7:0]
X_PM
X_IM
X_PIB
X_PIS
X_IPB
X_IPS
X_IDLE
X_RESET
Note: In previous documentation, the A_BUS, B_BUS, and C_BUS were
referred to as M_BUS, P_BUS, and I_BUS respectively.
X_TEST
Figure 1. STP2230SOP Block Diagram
STP2230SOP
Memory Data Bus
A[15:0]
C[3:0]
16
I/O Data Bus
4
MWB_CTRL
MRB_CTRL
Processor Data Bus
B[7:0]
8
BMX_CMD [3:0]
SEL[3:0]
4
CLK –
CLK +
Figure 2. STP2230SOP Logic Diagram
2
July 1997
XB1
Crossbar Switch
Processor Data Bus, B[143:0]
STP2230SOP
Crossbar Switch
Array (18)
(XB1)
STP2230SOP
Memory Data Bus, A[288:0]
I/O Data Bus
C[71:0]
STP2220SOP
UPA-to-SBus
Interface
(U2S)
A[35:0]
Cmd/Ctrl
UltraSPARC
A[35:0]
STAT
SBus
Controls
STP2200SOP
Uniprocessor
System Controller
(USC)
144
144
MEMADDR[12:0]
RAS[3:0]
CAS[3:0]
WE
Memory SIMMs
Figure 3. STP2230SOP Typical Application Diagram
July 1997
3
XB1
Crossbar Switch
STP2230SOP
SIGNAL DESCRIPTIONS
I/O
No. Pins
A[15:0]
Signal
I/O
16
Bidirectional data from memory bus.
B[7:0]
I/O
8
Processor port, bidirectional, registered
LV TTL
C[3:0]
I/O
4
Input/output port, bidirectional, registered
LV TTL
MRB_CTRL
I
1
Memory read buffer control
LV TTL
MWB_CTRL
I
1
Memory write buffer control
LV TTL
CLK+, CLK–
I
2
Differential clock signals
3.3-V PECL
BMX_CMD[3:0]
I
4
Command input signals
LV TTL
4
Description
I/F Type
LV TTL,
5-volt tolerant
July 1997
XB1
Crossbar Switch
STP2230SOP
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings [1]
Min
Max
Units
VDD
Symbol
DC supply voltage
Parameter
− 0.5
4.6
V
VCC
DC supply voltage
− 0.5
6.0
V
VIN
Input voltage range
− 0.5
VDD + 0.5
V
VIN_A_BUS
Input voltage range (A_bus)
– 0.5
VCC + 0.5
V
IIN
DC input current
–18
mA
IOUT
DC output current
– 50
50
mA
TST
Storage temperature
− 65
150
°C
FCLK
Clock frequency
STP2230SOP-83
0.050
83.34
MHz
STP2230SOP-100
0.050
100
MHz
1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages
are defined with respect to ground. Functional operation of the device at these or any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability.
Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
VDD
DC supply voltage
3.15
3.3
3.45
VCC
DC supply voltage
4.75
5.0
5.25
V
TC
Case temperature
0
–
75
˚C
TJ
Junction temperature
0
–
105
°C
Min
Max
Units
Capacitance
Symbol
Parameter
Conditions
CIN
Input capacitance
Any input
–
6
pF
COUT
Output capacitance
Any output
–
8
pF
CIO
Input/Output capacitance
–
10
pF
July 1997
5
XB1
Crossbar Switch
STP2230SOP
DC Characteristics
Symbol
Parameter
Conditions
Min
VIL
Voltage input low
–
VIH
Voltage input high
2.0
VIL
PECL clock voltage input low
VIH
PECL clock voltage input high
VDIFF
Input differential voltage (PECL inputs)
VOL
Voltage output low
IOL = 8 mA
–
VOH
Voltage output high
IOH = -8 mA
ICC
VCC input current
IDD
VDD input current
Typ
Max
Units
0.8
V
–
V
1.6
2.4
V
V
0.8
V
0.2
0.5
V
2.4
–
V
1
35
mA
35
mA
Max
Unit
5.4
ns
AC Characteristics
-83
Symbol
Parameter
Min
Typ
ports [1]
-100
Max
Min
Typ
tCO,UPA
Clock to output for processor and I/O
tVO,UPA
Clock to output for processor and I/O ports
5.4
tCO,M
Clock to output for memory port
tVO,M
Clock to output valid for memory port
tSPI
Input setup time for processor and I/O ports
tSM
Input setup time for memory port
4.0
4.0
ns
tHPI
Input hold time for processor and I/O ports
0.5
0.5
ns
tHM
Input hold time for memory port
2.0
2.0
ns
tCYCLE
Clock cycle time
12
10
ns
tWL
Clock minimum low width
5.4
4.4
ns
tWH
Clock minimum high width
5.4
4.4
ns
0.5
0.5
ns
6
6
TBD
TBD
2.0
2.0
ns
ns
ns
1. Note: tCO is specified with a 50 pF loading. This timing improves with a 3.1 nS with a 25 pF loading.
AC Characteristics - Clock Signal
-83
Symbol
FCLK
6
Parameter
Clock Frequency
-100
Min
Typ
Max
Min
Typ
Max
Unit
0.1
-
83.4
0.1
-
100
MHz
July 1997
XB1
Crossbar Switch
-83
Symbol
Parameter
Min
Typ
STP2230SOP
-100
Max
Min
Typ
Max
Unit
tCYCLE
Clock cycle time
12
10
ns
tWL
Clock minimum low width
5.4
4.4
ns
tWH
Clock minimum high width
5.4
4.4
ns
tE
Clock rise/fall time
250
July 1997
600
250
600
ps
7
XB1
Crossbar Switch
STP2230SOP
tCYCLE
tWH
tE(RISE)
tWL
3.0V
CLK+
0.0V
tE(FALL)
3.0V
CLK–
tSU
Input
0.0V
tH
VDD/2
tVO
Output
tCO
1.5V
Figure 4. Signal Timing Definition
8
July 1997
XB1
Crossbar Switch
STP2230SOP
TIMING DIAGRAMS
0
1
2
3
4
5
6
7
8
9
D4
D5
D6
D7
8
9
D4
D5
10
11
10
11
CLK
MRB_CTRL
BMX_CMD
MI*
D[0:3]
A[15:0]
D[4:7]
D0
C[3:0]
D1
D2
D3
Figure 5. Basic Memory Read to I/O Ports
0
1
2
3
4
5
6
7
CLK
MRB_CTRL
BMX_CMD
MI*
D[0:3]
A[15:0]
C[3:0]
D[4:7]
D0
D1
D2
D3
D6
D7
Figure 6. Memory Read to I/O Port Controlled by MRB_CTRL
0
1
2
3
4
5
6
7
8
9
10
11
8
9
10
11
CLK
MRB_CTRL
BMX_CMD
MP*
D[0:3]
A[15:0]
D[4:7]
D0, D1
B[7:0]
D2, D3
D4, D5
D6, D7
Figure 7. Basic Memory Read to Processor
0
1
2
3
4
5
6
7
CLK
MRB_CTRL
BMX_CMD
A[15:0]
B[7:0]
MP*
D[4:7]
D[0:3]
D0, D1
D2, D3
D4, D5
D6, D7
Figure 8. Memory Read to Processor Controlled by MRB_CTRL
July 1997
9
XB1
Crossbar Switch
STP2230SOP
0
1
2
3
4
5
6
7
8
9
10
11
9
10
11
CLK
BMX_CMD
PM
D0, D1
B[7:0]
D2, D3
D4, D5
D6, D7
MWB_CTRL
D[4:7]
D[0:3]
A[15:0]
Figure 9. Basic Memory Write From Processor
0
1
2
3
4
5
6
7
8
D1
D2
D3
D4
D5
D6
D7
CLK
IM
BMX_CMD
D0
C[3:0]
MWB_CTRL
D[0:3]
A[15:0]
D[4:7]
Figure 10. Basic Memory Write From I/O Ports
0
1
2
3
4
5
6
7
8
9
10
11
11
CLK
BMX_CMD
PIS
D0, D1
B[7:0]
D0
C[3:0]
D1
Figure 11. Single Transfer From Processor to I/O Port
0
1
2
3
4
5
6
7
8
9
10
D2
D3
D4
D5
D6
D7
CLK
BMX_CMD
B[7:0]
C[3:0]
PIB
D0, D1
D2, D3
D4, D5
D0
D6, D7
D1
Figure 12. Block Transfer From Processor to I/O Port
10
July 1997
XB1
Crossbar Switch
0
1
2
3
4
5
6
7
8
STP2230SOP
9
10
11
9
10
11
CLK
BMX_CMD
IPS
D0
C[3:0]
D1
D0, D1
B[7:0]
Figure 13. Single Transfer From I/O to Processor
0
1
2
3
4
5
6
7
8
D1
D2
D3
D4
D5
D6
D7
CLK
BMX_CMD
IPB
C[3:0]
D0
D0, D1
B[7:0]
D2, D3
D4, D5
D6, D7
Figure 14. Block Transfer From I/O to Processor
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CMD
TEST
P_BUS{7:0]
TEST
D0, D1
TEST
D4, D5
D2, D3
I_BUS[3:0]
M_BUS[15:0]
TEST
IDLE
IDLE
IDLE
IDLE
D6, D7
D0
D2
D0, 1, 0, 1
D2, 3, 2, 3
D4
D4, 5, 4, 5
Figure 15. X_TEST Basic Timing
0
1
2
3
4
5
6
7
8
9
10
11
CLK
CMD
P_BUS{7:0]
I_BUS[3:0]
M_BUS[15:0]
TEST
TEST
D0, D1
TEST
D2, D3
TEST
D4, D5
IDLE
IDLE
IDLE
IDLE
D6, D7
D1
D3
D0, 1, 0, 1
D2, 3, 2, 3
D5
D4, 5, 4
Figure 16. X_TEST2 Basic Timing
July 1997
11
XB1
Crossbar Switch
STP2230SOP
0
1
2
3
4
5
6
7
8
9
10
11
IDLE
IDLE
IDLE
CLK
BMX_CMD
RESET
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
B[7:0]
C[3:0]
A[15:0]
Figure 17. RESET Basic Timing
12
July 1997
XB1
Crossbar Switch
STP2230SOP
PACKAGE INFORMATION
48-Pin SOP Pin Assignments
Pin
Signal Name
Pin
Signal Name
A4
Pin
17
Signal Name
A10
Pin
25
Signal Name
Pin
Signal Name
Pin
Signal Name
1
BMX_CMD0
9
MWB_CTRL
33
C1
41
B3
2
BMX_CMD1
10
GND
18
VCC
3
A0
11
A5
19
A11
26
MRB_CTRL
34
GND
42
VDD
27
C3
35
C0
43
4
GND
12
A6
20
A12
28
B2
GND
36
B7
44
B1
5
A1
13
A7
21
GND
29
CLK –
37
B6
45
GND
6
A2
14
A8
22
A13
30
CLK +
38
B5
46
B0
7
VCC
15
GND
23
A14
31
VDD
39
GND
47
BMX_CMD2
8
A3
16
A9
24
A15
32
C2
40
B4
48
BMX_CMD3
Top View
July 1997
BMX_CMD0
1
48
BMX_CMD3
BMX_CMD1
2
47
BMX_CMD2
A0
3
46
B0
GND
4
45
GND
A1
5
44
B1
A2
6
43
B2
VCC
7
42
VDD
A3
8
41
B3
A4
9
40
B4
GND
10
39
GND
A5
11
38
B5
A6
12
37
B6
A7
13
36
B7
A8
14
35
C0
GND
15
34
GND
A9
16
33
C1
A10
17
32
C2
VCC
18
31
VDD
A11
19
30
CLK +
A12
20
29
CLK –
GND
21
28
GND
A13
22
27
C3
A14
23
25
MRB_CTRL
A15
24
25
MWB_CTRL
13
STP2230SOP
XB1
Crossbar Switch
48-Pin SOP Package Dimensions
0,30
0,15
0,50
48
0,08
M
25
6,40
6,00
8,40
7,80
0,15 NOM
Gage Plane
1
24
0,25
A
0°–5°
0,60
0,40
Seating Plane
1,20 MAX
0,10 MIN
0,10
Dimension
mm
A
Max
12.80
Min
12.40
Note:
1. All linear dimensions are in millimeters.
2. This drawing is subject to change without notice.
3. Body dimensions include mold flash or protrusion.
14
July 1997
XB1
Crossbar Switch
STP2230SOP
ORDERING INFORMATION
Part Number
Speed
Description
STP2230SOP
83 MHz
Crossbar switch for the UPA bus
STP2230SOP-100
100 MHz
Crossbar switch for the UPA bus
Documnet Part Number: 802-7955-02
July 1997
15
STP2230SOP
16
XB1
Crossbar Switch
July 1997