ANACHIP PA7572

PA7572 PEEL Array™
Programmable Electrically Erasable Logic Array
CMOS Electrically Erasable Technology
- Reprogrammable in 40-pin DIP, 44-pin PLCC and
TQFP packages
Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- ICT PLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
Versatile Logic Array Architecture
- 24 I/Os, 14 inputs, 60 registers/latches
- Up to 72 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
High-Speed Commercial and Industrial Versions
- As fast as 13ns/20ns (tpdi/tpdx), 66.6MHz (fMAX)
- Industrial grade available for 4.5 to 5.5V VCC and -40
to +85 °C temperatures
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, other wide-gate functions
General Description
The PA7572’s logic and I/O cells (LCCs, IOCs) are
extremely flexible with up to three output functions per cell
(a total of 72 for all 24 logic cells). Cells are configurable as
D, T, and JK registers with independent or global clocks,
resets, presets, clock polarity, and other features, making
the PA7572 suitable for a variety of combinatorial,
synchronous and asynchronous logic applications. The
PA7572 supports speeds as fast as 13ns/20ns (tpdi/tpdx)
and 66.6MHz (fMAX) at moderate power consumption
140mA (100mA typical). Packaging includes 40-pin DIP
and 44-pin PLCC (see Figure 1). Anachip and popular
third-party development tool manufacturers provide
development and programming support for the PA7572.
The PA7572 is a member of the Programmable Electrically
Erasable Logic (PEEL™) Array family based on Anachip’s
CMOS EEPROM technology. PEEL™ Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7572 offers a
versatile logic array architecture with 24 I/O pins, 14 input
pins and 60 registers/latches (24 buried logic cells, 12 input
registers/latches, 24 buried I/O registers/latches). Its logic
array implements 100 sum-of-products logic functions
divided into two groups each serving 12 logic cells. Each
group shares half (60) of the 120 product-terms available.
Figure 1. Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PLCC
VCC
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I/CLK2
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
I/O
I
I
I
G ND
G ND
I/CLK2
I
I
I
I/O
T Q FP
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G ND
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
I/O
I
I
I
I/CLK1
VCC
VCC
I
I
I/O
I
I
I/O
I
I
G ND
G ND
I/CLK2
I
I
I
I/O
I/CLK1
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
G ND
Figure 2. Block Diagram
I/O
I
I
I
I/CLK1
VCC
VCC
I
I
I
I/O
DIP (600 mil)
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2 Input/
G lobal Clock Pins
G ND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
G lobal
Ce lls
12 Input Pins
2
I/CLK
I
I
I
I
I/O
I/O Cells
Input Cells
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
GND
Lo gic
A rray
4 sum term s
5 product term s
for G lobal Cells
A
B
C
D
24 I/O Pins
Buried
logic
24
VCC
Global C ells
I/O
Cells
(IO C)
24
12
I
08-15-001A
Input
Cells
(INC)
124 (62X2)
Array Inputs
true and
com plem ent
Logic
Control
Cells
(LCC)
24
Logic
func tions
to I/O cells
24
96 sum term s
(four per LCC)
24 Logic Control Cells
up to 3 output functions per cell
(72 total output functions
possible)
I
Logic C ontrol Cells
PA7572
I
I
08-15-002A
I/CLK 2
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights
under any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/10
Inside the Logic Array
The heart of the PEEL™ Array architecture is based on a
logic array structure similar to that of a PLA (programmable
AND, programmable OR). The logic array implements all
logic functions and provides interconnection and control of
the cells. In the PA7572 PEEL™ Array, 62 inputs are
available into the array from the I/O cells, inputs cells and
input/global-clock pins.
products functions provided to the logic cells can be used for
clocks, resets, presets and output enables instead of just
simple product-term control.
The PEEL™ logic array can also implement logic functions
with many product terms within a single-level delay. For
example a 16-bit comparator needs 32 shared product terms
to implement 16 exclusive-OR functions. The PEEL™ logic
array easily handles this in a single level delay. Other
PLDs/CPLDs either run out of product-terms or require
expanders or additional logic levels that often slow
performance and skew timing.
All inputs provide both true and complement signals, which
can be programmed to any product term in the array. The
PA7572 PEEL™ Arrays contains 124 product terms. All
product terms (with the exception of certain ones fed to the
global cells) can be programmably connected to any of the
sum-terms of the logic control cells (four sum-terms per
logic control cell). Product-terms and sum-terms are also
routed to the global cells for control purposes. Figure 3
shows a detailed view of the logic array structure.
Logic Control Cell (LCC)
Logic Control Cells (LCC) are used to allocate and control the
logic functions created in the logic array. Each LCC has four
primary inputs and three outputs. The inputs to each LCC are
complete sum-of-product logic functions from the array, which
can be used to implement combinatorial and sequential logic
functions, and to control LCC registers and I/O cell output
enables.
From
IO Cells
(IO C,INC,
I/CLK)
From G lobal Cell
Preset
System Clock
62 Array Inputs
RegT ype Reset
On/Off
M UX
To
Array
P
D,T,J
M UX
From
Logic
Control
Cells
(LCC)
REG
K
R
From
Array
To
G lobal
Cells
Q
A
B
C
D
125 Product
Term s
To
I/O
Cell
M UX
08-15-004A
To
Logic Control
Cells
(LCC)
Figure 4. Logic Control Cell Block Diagram
As shown in Figure 4, the LCC is made up of three signal
routing multiplexers and a versatile register with synchronous
or asynchronous D, T, or JK registers (clocked-SR registers,
which are a subset of JK, are also possible). See Figure 5.
EEPROM memory cells are used for programming the
desired configuration. Four sum-of-product logic functions
(SUM terms A, B, C and D) are fed into each LCC from the
logic array. Each SUM term can be selectively used for
multiple functions as listed below.
08-15-003A
PA7572 Logic Array
100 Sum Term s
Figure 3. PA7572 Logic Array
True Product-Term Sharing
The PEEL™ logic array provides several advantages over
common PLD logic arrays. First, it allows for true productterm sharing, not simply product-term steering, as commonly found in other CPLDs. Product term sharing ensures
that product-terms are used where they are needed and
not left unutilized or duplicated. Secondly, the sum-ofAnachip Corp.
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Sum A, B or C combinatorial paths. Thus, one LCC output
can be registered, one combinatorial and the third, an output
enable, or an additional buried logic function. The multifunction PEEL™ Array logic cells are equivalent to two or
three macrocells of other PLDs, which have one output per
cell. They also allow registers to be truly buried from I/O pins
without limiting them to input-only (see Figure 8 & Figure 9).
Sum-A = D, T, J or Sum-A
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D
D
P
D Register
Q = D after clocked
Q
Best for storage, sim ple counters,
shifters and state m achines w ith
few hold (loop) conditions.
R
T
P
Q
K
P
Input Cell Clock
T Register
Q toggles w hen T = 1
Q holds w hen T = 0
REG/
Latch
Best for w ide binary counters (saves
product term s) and state m achines
w ith m any hold (loop) conditions.
R
J
From G lobal Cell
Q
Q
M UX
Input
JK Register
Q toggles w hen J/K = 1/1
Q holds w hen J/K = 0/0
Q= 1
w hen J/K = 1/0
Q= 0
w hen J/K = 0/1
Input
To
Array
Input Cell (INC)
R
Com bines features of both D and T
registers.
From G lobal Cell
08-15-005A
Input Cell Clock
Figure 5. LCC Register Types
RE G/
Latch
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I/O cell, or an internal feedback
node. Note that the sums controlling clocks, resets, presets
and output enables are complete sum-of-product functions,
not just product terms as with most other PLDs. This also
means that any input or I/O pin can be used as a clock or
other control function.
Q
To
Array
M UX
Input
M UX
From
Logic
Control
Cell
A,B,C
or
Q
M UX
I/O Pin
M UX
D
1 0
I/O Cell (IO C)
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 9).
08-15-006A
Figure 6. Input and I/O Cell Block Diagrams
D
Q
IOC/INC Register
Q = D after rising edge of clock
holds until next rising edge
L
Multiple Outputs Per Logic Cell
Q
IOC/INC Latch
Q = L w hen clock is high
holds value w hen clock is low
08-15-007A
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Figure 7. IOC/INC Register Configurations
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Input Cells (INC)
Global Cells
Input cells (INC) are included on dedicated input pins. The
block diagram of the INC is shown in Figure 6. Each INC
consists of a multiplexer and a register/transparent latch,
which can be clocked from various sources selected by the
global cell (see Figure 7). The register is rising edge
clocked. The latch is transparent when the clock is high
and latched on the clock’s falling edge. The register/ latch
can also be bypassed for a non-registered input.
The global cells, shown in Figure 10, are used to direct global
clock signals and/or control terms to the LCCs, IOCs and
INCs. The global cells allow a clock to be selected from the
CLK1 pin, CLK2 pin, or a product term from the logic array
(PCLK). They also provide polarity control for INC and IOC
clocks enabling rising or falling clock edges for input
registers/latches. Note that each individual LCC clock has its
own polarity control. The global cell for LCCs includes sumof-products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to save
product terms for loadable counters and state machines (see
Figure 11). The PA7572 provides two global cells that divide
the LCC and IOCs into groups, A and B. Half of the LCCs and
IOCs use global cell A, half use global cell B. This means that
two high-speed global clocks can be used among the LCCs.
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the
LCCs in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a threestate buffer and an output polarity control. The register/
latch can be clocked from a variety of sources determined
by the global cell. It can also be bypassed for a nonregistered input. The PA7572 allows the use of SUM-D as
a feedback to the array when the I/O pin is a dedicated
output. This allows for additional buried registers and logic
paths. (See Figure 8 and Figure 9).
CLK1
CLK2
M UX
INC Clocks
PCLK
G lobal Cell: INC
Group A & B
CLK1
M UX
LCC Clocks
M UX
IOC Clocks
CLK2
Q D
PCLK
Input with optional
register/latch
I/O
Reg-Type
LCC Reg-Type
Preset
I/O with
independent
output enable
A
G lobal Cell: LCC & IO C
B
Figure 10. Global Cells
2
OE
D
08-15-010A
1
D Q
C
LCC Presets
LCC Resets
Reset
Reg-Type from Glob al Cell
08-15-008A
Figure 8. LCC & IOC With Two Outputs
Register Ty pe Change Feature
D
P
Q
Q D
Buried register or
logic paths
A
B
C
D
D Q
O utput
R
Example:
Product term s for 10 bit loadable binary counter
1
T
P
2
3
R
08-15-009A
Global Cell can dynam ically change userselected LCC registers from D to T or from D
to JK. This saves product term s for loadable
counters or state m achines. Use as D register
to load, use as T or JK to count. Tim ing
allow s dynam ic operation.
Q
D uses 57 product term s (47 count, 10 load)
T uses 30 product term s (10 count, 20 load)
D/T uses 20 product term s (10 count, 10 load)
08-15-011 A
Figure 9. LCC & IOC With Three Outputs
Figure 11. Register Type Change Feature
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unexpected changes to be made quickly and without waste.
Programming of PEEL™ Arrays is supported by many
popular third party programmers.
PEEL™ Array Development Support
Development support for PEEL™ Arrays is provided by
Anachip and manufacturers of popular development tools.
Anachip offers the powerful PLACE Development Software
(free to qualified PLD designers).
Design Security and Signature Word
The PEEL™ Arrays provide a special EEPROM security bit
that prevents unauthorized reading or copying of designs.
Once set, the programmed bits of the PEEL™ Arrays
cannot be accessed until the entire chip has been
electrically erased. Another programming feature,
signature word, allows a user-definable code to be
programmed into the PEEL™ Array. The code can be read
back even after the security bit has been set. The signature
word can be used to identify the pattern programmed in the
device or to record the design revision.
The PLACE software includes an architectural editor, logic
compiler, waveform simulator, documentation utility and a
programmer interface. The PLACE editor graphically
illustrates and controls the PEEL™ Array’s architecture,
making the overall design easy to understand, while
allowing the effectiveness of boolean logic equations, state
machine design and truth table entry. The PLACE compiler
performs logic transformation and reduction, making it
possible to specify equations in almost any fashion and fit
the most logic possible in every design. PLACE also
provides a multi-level logic simulator allowing external and
internal signals to be simulated and analyzed via a
waveform display.(See Figure 12, Figure 13, Figure 14)
Figure 13. PLACE LCC and IOC Screen
Figure 12. PLACE Architectural Editor
PEEL™ Array development is also supported by popular
development tools, such as ABEL and CUPL, via ICT’s
PEEL™ Array fitters. A special smart translator utility adds
the capability to directly convert JEDEC files for other
devices into equivalent JEDEC files for pin-compatible
PEEL™ Arrays.
Programming
PEEL™ Arrays are EE-reprogrammable in all package
types, plastic-DIP, PLCC and SOIC. This makes them an
ideal development vehicle for the lab. EEreprogrammability is also useful for production, allowing
Figure 14. PLACE Simulator Screen
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This device has been designed and tested for the specified
operating ranges. Improper operation outside of these levels
is not guaranteed. Exposure to absolute maximum
ratings may cause permanent damage.
Table 1. Absolute Maximum Ratings
Symbol
Parameter
Conditions
Ratings
VCC
Supply Voltage
Relative to Ground
VI, VO
Voltage Applied to Any Pin
Relative to Ground
Per pin (IOL, IOH)
IO
Output Current
TST
Storage Temperature
TLT
Lead Temperature
1
Unit
-0.5 to + 7.0
V
-0.5 to VCC + 0.6
V
±25
mA
-65 to + 150
°C
+300
°C
Soldering 10 seconds
Table 2. Operating Ranges
Symbol
Parameter
Conditions
Min
Max
Commercial
4.75
5.25
Industrial
4.5
5.5
Commercial
0
+70
Industrial
-40
+85
VCC
Supply Voltage
TA
Ambient Temperature
TR
Clock Rise Time
See Note 2
20
ns
TF
Clock Fall Time
See Note 2
20
ns
TRVCC
VCC Rise Time
See Note 2
250
ms
Max
Unit
Table 3. D.C. Electrical Characteristics
Symbol
Unit
V
°C
Over the Operating Range
Parameter
Conditions
Min
VOH
Output HIGH Voltage - TTL
VCC = Min, IOH = -4.0mA
VOHC
Output HIGH Voltage CMOS
2.4
V
VCC = Min, IOH = -10µA
VCC - 0.3
V
VOL
Output LOW Voltage - TTL
VCC = Min, IOL = 16mA
0.5
V
VOLC
Output LOW Voltage CMOS
VCC = Min, IOL = -10µA
0.15
V
VIH
Input HIGH Level
2.0
VCC + 0.3
V
VIL
Input LOW Level
-0.3
0.8
V
IIL
Input Leakage Current
VCC = Max, GND ≤VIN ≤VCC
±10
µA
IOZ
Output Leakage Current
I/O = High-Z, GND ≤VO ≤VCC
±10
µA
ISC
Output Short Circuit
4
Current
VCC = 5V, VO = 0.5V, TA= 25°C
-120
mA
VCC Current
VIN = 0V or VCC
f = 25MHz
4
All outputs disabled
3,11
ICC
11
CIN
7
COUT
Input Capacitance
7
5
Output Capacitance
5
-30
-20
18
75
50 (typ.)
I-20
mA
85
6
pF
12
pF
TA = 25°C, VCC = 5.0V @ f = 1 MHz
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Table 4. A.C Electrical Characteristics Combinatorial
Parameter6,12
Symbol
Over the Operating Range
-20/I-20
Min
Max
Unit
tPDI
Propagation delay Internal (tAL + tLC)
13
ns
tPDX
Propagation delay External (tIA + tAL +tLC + tLO)
20
ns
tIA
Input or I/O pin to array input
2
ns
tAL
Array input to LCC
12
ns
1
ns
5
ns
5
ns
20
ns
tLC
LCC input to LCC output
tLO
LCC output to output pin
tOD, tOE
tOX
10
Output Disable, Enable from LCC output
Output Disable, Enable from input pin
7
7
This device has been designed and tested for the recommended operating conditions. Proper operation outside of these
levels is not guaranteed. Exposure to absolute maximum ratings may cause permanent damage
Figure 15. Combinatorial Timing - Waveforms and Block Diagram
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Table 5. A.C. Electrical Characteristics Sequential
8
tSCI
tSCX
-20/I-20
Parameter6,1
Symbol
Internal set-up to system clock - LCC
(tAL + tSK + tLC - tCK)
Min
14
16
Input (EXT.) set-up to system clock, - LCC (tIA + tSCI)
Max
Unit
8
ns
10
ns
14
tCOI
System-clock to Array Int. - LCC/IOC/INC (tCK +tLC)
7
ns
tCOX
System-clock to Output Ext. - LCC (tCOI + tLO)
12
ns
tHX
Input hold time from system clock - LCC
0
ns
tSK
LCC Input set-up to async. clock - LCC
13
1
ns
tAK
Clock at LCC or IOC - LCC output
1
ns
tHK
LCC input hold time from system clock - LCC
4
ns
tSI
Input set-up to system clock - IOC/INC (tSK - tCK)
0
ns
tHI
Input hold time from system clock - IOC/INC (tSK - tCK)
5
tPK
Array input to IOC PCLK clock
14
ns
9
17
ns
tSPI
Input set-up to PCLK clock - IOC/INC (tSK-tPK-tIA)
0
ns
tHPI
Input hold from PCLK clock - IOC/INC (tPK+tIA-tSK)
10
ns
tSD
Input set-up to system clock - IOC/INC Sum-D
(
tIA + tAL + tLC + tSK - tCK)
10
ns
tHD
Input hold time from system clock - IOC Sum-D
0
ns
7
ns
0
ns
17
15
tHDP
Input set-up to PCLK clock - IOC Sum-D
(tIA + tAL + tLC + tSK - tPK)
Input hold time from PCLK clock - IOC Sum-D
tCK
System-clock delay to LCC/IOC/INC
tCW
System-clock low or high pulse width
fMAX1
Max. system-clock frequency Int/Int 1/(tSCI + tCOI)
66.6
MHz
fMAX2
Max. system-clock frequency Ext/Int 1/(tSCX + tCOI)
58.8
MHz
fMAX3
Max. system-clock frequency Int/Ext 1/(tSCI + tCOX)
50.0
MHz
fMAX4
Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX)
45.4
MHz
71.4
MHz
tSDP
6
ns
7
9
ns
fTGL
Max. system-clock toggle frequency 1/(tCW + tCW)
tPR
LCC presents/reset to LCC output
1
ns
tST
Input to Global Cell present/reset (tIA + tAL + tPR)
15
ns
tAW
Asynch. preset/reset pulse width
tRT
Input to LCC Reg-Type (RT)
8
ns
tRTV
LCC Reg-Type to LCC output register change
1
ns
tRTC
Input to Global Cell register-type change (tRT + tRTV)
9
ns
tRW
Asynch. Reg-Type pulse width
tRESET
8
ns
10
Power-on reset time for registers in clear state
2
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ns
5
µs
Rev. 1.0 Dec 16, 2004
8/10
Figure 16. Sequential Timing – Waveforms and Block Diagram
Notes
1. Minimum DC input is -0.5V, however inputs may under-shoot to -2.0V
for periods less than 20ns.
2.Test points for Clock and VCC in tR,tF,tCL,tCH, and tRESET are referenced at
10% and 90% levels.
3. I/O pins are 0V or VCC.
4. Test one output at a time for a duration of less than 1 sec.
5. Capacitances are tested on a sample basis.
6. Test conditions assume: signal transition times of 5ns or less from the
10% and 90% points, timing reference levels of 1.5V (unless
otherwise specified).
7. tOE is measured from input transition to VREF ±0.1V (See test loads at
end of Section 6 for VREF value). tOD is measured from input transition
to VOH -0.1V or VOL +0.1V.
8. DIP: “System-clock” refers to pin 1/21 high speed clocks. PLCC: “System-clock” refers to pin 2/24 high speed clocks.
9. For T or JK registers in toggle (divide by 2) operation only.
10. For combinatorial and async-clock to LCC output delay.
11. ICC for a typical application: This parameter is tested with the device
programmed as a 10-bit D-type counter.
12. Test loads are specified in Section 5 of this Data Book.
13. “Async. Clock” refers to the clock from the Sum term (OR gate).
14. The “LCC” term indicates that the timing parameter is applied to the
LCC register. The “LCC/IOC” term indicates that the timing
parameter is applied to both the LCC and IOC registers. The
“LCC/IOC/INC” term indicates that the timing parameter is applied to
the LCC, IOC, and INC registers.
15. This refers to the Sum-D gate routed to the IOC register for an
additional buried register.
16. The term “input” without any reference to another term refers to an
(external) input pin.
17. The parameter tSPI indicates that the PCLK signal to the IOC register
is always slower than the data from the pin or input by the absolute
value of (tSK -tPK -tIA). This means that no set-up time for the data
from the pin or input is required, i.e. the external data and clock can
be sent to the device simultaneously. Additionally, the data from the
pin must remain stable for tHPI time, i.e. to wait for the PCLK signal to
arrive at the IOC register.
18. Typical (typ) ICC is measured at TA = 25° C, freq = 25MHZ, VCC =
5V
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
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Table 6. Ordering Information
Part Number
PA7572P-20 (L)
PA7572F-20 (L)
PA7572J-20 (L)
PA7572PI-20 (L)
PA7572FI-20 (L)
PA7572JI-20 (L)
Speed
Temperature
13/20ns
C
13/20ns
I
Package
P40
F44
J44
P40
F44
J44
Figure 17. Part Number
Device
Suffix
PA7572J-20X
Lead Free
Blank : Normal
L : Lead Free Package
Package
P = 600mil DIP
F = Thin Quad Flat Pack (TQFP)
J = Plastic (J) Leaded Chip Carrier (PLCC)
Speed
-20 = 13ns/20ns tpd/tpdx
Temperature Range
(Blank) = Commercial 0 to 70oC
I = Industrial -40 to +85oC
Anachip Corp.
Head Office,
2F, No. 24-2, Industry E. Rd. IV, Science-Based
Industrial Park, Hsinchu, 300, Taiwan
Tel: +886-3-5678234
Fax: +886-3-5678368
Anachip USA
780 Montague Expressway, #201
San Jose, CA 95131
Tel: (408) 321-9600
Fax: (408) 321-9696
Email: sales_usa@anachip.com
Website: http://www.anachip.com
©2004 Anachip Corp.
Anachip reserves the right to make changes in specifications at any time and without notice. The information furnished by
Anachip in this publication is believed to be accurate and reliable. However, there is no responsibility assumed by Anachip
for its use nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted
under any patents or patent rights of Anachip. Anachip’s products are not authorized for use as critical components in life
support devices or systems.
Marks bearing © or ™ are registered trademarks and trademarks of Anachip Corp.
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
10/10