LXT386 QUAD T1/E1/J1 Transceiver Datasheet The LXT386 is a quad short haul Pulse Code Modulation (PCM) transceiver for use in both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four independent receivers and four independent transmitters in a single PBGA-160 or LQFP-100 package. The transmit drivers provide low impedance independent of the transmit pattern and supply voltage variations.The LXT386 transmits shaped waveforms meeting G.703 and T1.102 specifications. The LXT386 exceeds the latest transmit return loss specifications, such as ETSI ETS-300166. The LXT386’s differential receiver architecture provides high noise interference margin and is able to work with up to 12 dB of cable attenuation. The digital clock recovery PLL and jitter attenuator are referenced to a low frequency 1.544 MHz or 2.048 MHz clock. The LXT386 incorporates an advanced crystal-less jitter attenuator switchable between the receive and transmit path. The jitter attenuation performance meets the latest international specifications such as CTR12/13. The jitter attenuation performance was optimized for Synchronous Optical NETwork/Synchronous Digital Hierarchy (SONET/SDH) applications. The LXT386 can be configured as a 3 channel transceiver with G.772 compliant non intrusive protected monitoring points. It uses a single 3.3V supply for low power consumption. The constant delay characteristic of the LXT386 JA as well as a power down mode of all transmitters allows the implementation of Hitless Protection Switching (HPS) applications without the use of relays. Applications ■ ■ ■ SONET/SDH tributary interfaces Digital cross connects Public/private switching trunk line interfaces ■ ■ Microwave transmission systems M13, E1-E3 MUX As of January 15, 2001, this document replaces the Level One document LXT386 — QUAD T1/E1/J1 Transceiver¶ Font>. Order Number: 249253-001 January 2001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT386 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Contents 1.0 Features ......................................................................................................................... 7 2.0 Pin Assignments and Signal Description ........................................................ 9 3.0 Functional Description...........................................................................................22 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 Initialization..........................................................................................................22 3.1.1 Reset Operation .....................................................................................22 Receiver ..............................................................................................................23 3.2.1 Loss of Signal Detector ..........................................................................24 3.2.1.1 E1 Mode ....................................................................................24 3.2.1.2 T1 Mode ....................................................................................24 3.2.1.3 Data Recovery Mode.................................................................24 3.2.2 Alarm Indication Signal (AIS) Detection .................................................24 3.2.2.1 E1 Mode ....................................................................................25 3.2.2.2 T1 Mode ....................................................................................25 3.2.3 In Service Code Violation Monitoring .....................................................25 Transmitter ..........................................................................................................25 3.3.1 Transmit Pulse Shaping .........................................................................26 3.3.1.1 Hardware Mode .........................................................................26 3.3.1.2 Host Mode .................................................................................26 3.3.2 Transmit Pulse Shaping .........................................................................27 3.3.2.1 Output Driver Power Supply ......................................................27 3.3.2.2 Power Sequencing ....................................................................27 Driver Failure Monitor..........................................................................................27 Line Protection ....................................................................................................28 Jitter Attenuation .................................................................................................30 Loopbacks ...........................................................................................................31 3.7.1 Analog Loopback....................................................................................31 3.7.2 Digital Loopback.....................................................................................32 3.7.3 Remote Loopback ..................................................................................32 3.7.4 Transmit All Ones (TAOS)......................................................................32 G.772 Performance Monitoring ...........................................................................33 Hitless Protection Switching (HPS) .....................................................................34 Operation Mode Summary ..................................................................................34 Interfacing with 5V logic ......................................................................................35 Parallel Host Interface .........................................................................................35 3.12.1 Motorola Interface ..................................................................................35 3.12.2 Intel Interface..........................................................................................36 Interrupt Handling................................................................................................36 3.13.1 Interrupt Enable......................................................................................36 3.13.2 Interrupt Clear ........................................................................................37 Serial Host Mode.................................................................................................37 4.0 Register Descriptions .............................................................................................38 5.0 JTAG Boundary Scan .............................................................................................45 5.1 5.2 Datasheet Overview .............................................................................................................45 Architecture .........................................................................................................45 3 LXT386 — QUAD T1/E1/J1 Transceiver 5.3 5.4 5.5 6.0 Test Specifications .................................................................................................. 53 6.1 7.0 TAP Controller..................................................................................................... 45 JTAG Register Description.................................................................................. 47 5.4.1 Boundary Scan Register (BSR).............................................................. 48 Device Identification Register (IDR) .................................................................... 50 5.5.1 Bypass Register (BYR) .......................................................................... 50 5.5.2 Analog Port Scan Register (ASR) .......................................................... 50 5.5.3 Instruction Register (IR) ......................................................................... 51 Recommendations and Specifications ................................................................ 75 Mechanical Specifications ................................................................................... 76 Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 4 LXT386 Block Diagram ......................................................................................... 7 LXT386 Detailed Block Diagram ........................................................................... 8 LXT386 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and Package Markings......................................................................................................... 9 LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments........................... 10 Pullup Resistor to RESET ................................................................................... 23 50% AMI Encoding.............................................................................................. 26 External Transmit/Receive Line Circuitry ............................................................ 29 Jitter Attenuator Loop.......................................................................................... 31 Analog Loopback ................................................................................................ 31 Digital Loopback.................................................................................................. 32 Remote Loopback ............................................................................................... 32 TAOS Data Path ................................................................................................. 33 TAOS with Analog Loopback .............................................................................. 33 Serial Host Mode Timing..................................................................................... 37 LXT386 JTAG Architecture ................................................................................. 45 JTAG State Diagram ........................................................................................... 47 Analog Test Port Application............................................................................... 52 Transmit Clock Timing Diagram.......................................................................... 59 Receive Clock Timing Diagram........................................................................... 60 JTAG Timing ....................................................................................................... 61 Non-Multiplexed Intel Mode Read Timing ........................................................... 62 Multiplexed Intel Read Timing............................................................................. 63 Non-Multiplexed Intel Mode Write Timing ........................................................... 64 Multiplexed Intel Mode Write Timing ................................................................... 65 Non-Multiplexed Motorola Mode Read Timing.................................................... 66 Multiplexed Motorola Mode Read Timing............................................................ 67 Non-Multiplexed Motorola Mode Write Timing .................................................... 68 Multiplexed Motorola Mode Write Timin.............................................................. 69 Serial Input Timing .............................................................................................. 70 Serial Output Timing ........................................................................................... 70 E1, G.703 Mask Templates................................................................................. 71 T1, T1.102 Mask Templates ............................................................................... 72 LXT386 Jitter Tolerance Performance ................................................................ 73 Jitter Transfer Performance ................................................................................ 74 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 35 36 37 Output Jitter for CTR12/13 applications ..............................................................75 60 Plastic Ball Grid Array (PBGA) Package Dimensions ....................................76 100 Pin Low Quad Flat Packages (LQFP) Dimensions ......................................77 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Assignments and Signal Descriptions...........................................................11 Line Length Equalizer Inputs...............................................................................27 Jitter Attenuation Specifications ..........................................................................30 Operation Mode Summary ..................................................................................34 Microprocessor Parallel Interface Selection ........................................................35 Serial and Parallel Port Register Addresses .......................................................38 Register Bit Names .............................................................................................38 ID Register, ID (00H)...........................................................................................39 Analog Loopback Register, ALOOP (01H)..........................................................39 Remote Loopback Register, RLOOP (02H) ........................................................40 TAOS Enable Register, TAOS (03H) ..................................................................40 LOS Status Monitor Register, LOS (04H) ...........................................................40 DFM Status Monitor Register, DFM (05H) ..........................................................40 LOS Interrupt Enable Register, LIE (06H)...........................................................40 DFM Interrupt Enable Register, DIE (07H)..........................................................40 LOS Interrupt Status Register, LIS (08H)............................................................41 DFM Interrupt Status Register, DIS (09H)...........................................................41 Software Reset Register, RES (0AH)..................................................................41 Performance Monitoring Register, MON (0BH)...................................................41 Digital Loopback Register, DL (0CH) ..................................................................41 LOS/AIS Criteria Register, LCS (0DH)................................................................41 Automatic TAOS Select Register, ATS (0EH).....................................................42 Global Control Register, GCR (0FH)...................................................................42 Pulse Shaping Indirect Address Register, PSIAD (10H) .....................................43 Pulse Shaping Data Register, PSDAT (11H) ......................................................43 Output Enable Register, OER (12H) ...................................................................43 AIS Status Monitor Register, AIS (13H) ..............................................................43 AIS Interrupt Enable Register, AISIE (14H) ........................................................44 AIS Interrupt Status Register, AISIS (15H) .........................................................44 TAP State Description .........................................................................................46 Device Identification Register (IDR) ....................................................................50 Analog Port Scan Register (ASR) .......................................................................51 Instruction Register (IR) ......................................................................................51 Absolute Maximum Ratings.................................................................................53 Recommended Operating Conditions .................................................................53 DC Characteristics ..............................................................................................54 E1 Transmit Transmission Characteristics..........................................................55 E1 Receive Transmission Characteristics...........................................................55 T1 Transmit Transmission Characteristics ..........................................................56 T1 Receive Transmission Characteristics ...........................................................57 Jitter Attenuator Characteristics ..........................................................................58 Analog Test Port Characteristics.........................................................................59 Transmit Timing Characteristics..........................................................................59 Receive Timing Characteristics...........................................................................60 Tables Datasheet 5 LXT386 — QUAD T1/E1/J1 Transceiver 45 46 47 48 49 50 51 52 53 6 JTAG Timing Characteristics .............................................................................. 61 Intel Mode Read Timing Characteristics ............................................................. 61 Intel Mode Write Timing Characteristics ............................................................. 63 Motorola Bus Read Timing Characteristics......................................................... 65 Motorola Mode Write Timing Characteristics ...................................................... 67 Serial I/O Timing Characteristics......................................................................... 69 Transformer Specifications3 ............................................................................... 70 G.703 2.048 Mbit/s Pulse Mask Specifications ................................................... 71 T1.102 1.544 Mbit/s Pulse Mask Specifications.................................................. 71 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 1.0 Features • Single rail 3.3V supply with 5V tolerant inputs • Low power consumption of 150mW per channel (typical) • Superior crystal-less jitter attenuator — Meets ETSI CTR12/13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications — Optimized for SONET/SDH applications, meets ITU G.783 mapping jitter specification — Constant throughput delay jitter attenuator • • • • • • • • • Hitless Protection Switching (HPS) for 1 to 1 protection without relays HDB3, B8ZS, or AMI line encoder/decoder Provides protected monitoring points per ITU G.772 Analog/digital and remote loopback testing functions LOS per ITU G.775, ETS 300 233 and T1.231 8 bit parallel or 4 wire serial control interface Hardware and Software control modes JTAG Boundary Scan test port per IEEE 1149.1 160 PBGA and 100 pin LQFP packages Figure 1. LXT386 Block Diagram MODE JTAG SERIAL/ PARALLEL PORT LOOP 0..3 HARDWARE / SOFTWARE CONTROL (JTAG INTERFACE) JASEL CLKE MCLK LOS LOS DATA SLICER TRING LINE DRIVER PULSE PULSE SHAPER JITTER ATTENUATOR RX OR TX PATH JITTER ATTENUATOR RX OR TX PATH RPOS REMOTE LOOPBACK DATA CLOCK CLOCK RECOVERY DIGITAL LOOPBACK TTIP ANALOG LOOPBACK RRING G.772 MONITOR RTIP B8ZS / HDB3 DECODER RCLK RNEG TPOS B8ZS / HDB3 ENCODER TCLK TNEG 0 1 2 3 Datasheet 7 LXT386 — QUAD T1/E1/J1 Transceiver Figure 2. LXT386 Detailed Block Diagram JTAG SERIAL/ PARALLEL PORT MODE LOOP 0..7 JASEL CLKE MCLK HARDWARE / SOFTWARE CONTROL (JTAG INTERFACE) Transceiver 3 LOS3 LOS TRING3 RTIP2/RRING2 TTIP2/TRING2 RTIP1/RRING1 LINE DRIVER PULSE PULSE SHAPER JITTER ATTENUATOR RX OR TX PATH JITTER ATTENUATOR RX OR TX PATH REMOTE LOOPBACK ANALOG LOOPBACK TTIP3 G.772 Protected Monitoring Point RRING3 DATA CLOCK CLOCK RECOVERY DIGITAL LOOPBACK DATA SLICER RTIP3 B8ZS / HDB3 DECODER RPOS3 RCLK3 RNEG3 B8ZS / HDB3 ENCODER TPOS3 TCLK3 TNEG3 LOS2 Transceiver 2 RPOS2/RNEG2/RCLK2 TPOS2/TNEG2/TCLK2 LOS1 Transceiver 1 RPOS1/RNEG1/RCLK1 TTIP1/TRING1 TPOS1/TNEG1/TCLK1 Transceiver 0 LOS0 LOS TRING0 DATA CLOCK CLOCK RECOVERY LINE DRIVER PULSE PULSE SHAPER JITTER ATTENUATOR RX OR TX PATH JITTER ATTENUATOR RX OR TX PATH REMOTE LOOPBACK TTIP0 MUX DIGITAL LOOPBACK RTIP0 RRING0 ANALOG LOOPBACK DATA SLICER B8ZS / HDB3 DECODER RPOS0 RCLK0 RNEG0 B8ZS / HDB3 ENCODER TPOS0 TCLK0 TNEG0 A3 - A0 8 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 2.0 Pin Assignments and Signal Description AT2 AT1 77 76 MODE MCLK ALE ACK INT 78 OE 82 81 80 79 CLKE 83 A1 A0 D1 D0 91 A3 A2 D2 92 87 86 85 84 D4 D3 94 93 A4 D7 D6 D5 97 96 95 88 CS 98 90 89 MUX 100 99 RESET Figure 3. LXT386 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and Package Markings MOT 1 2 75 74 VCC R/W DS VCC 3 73 TDO 4 5 6 72 TRST 71 70 TMS TDI 7 8 69 TCK VCC VCC 9 68 67 VCC VCC GND GND 10 66 GND GND TCLK1 12 TPOS1 13 14 GND VCC GND Rev # LXT386LE XX XXXXXX XXXXXXXX Part # LOT # FPO # 11 65 64 63 GND TCLK2 TPOS2 RNEG1 17 62 61 60 59 LOS1 TCLK0 18 58 LOS2 19 20 57 TCLK3 56 21 55 TPOS3 TNEG3 22 54 RCLK3 53 52 RPOS3 RNEG0 23 24 LOS0 25 51 46 47 48 49 50 TVCC3 RRING3 RTIP3 N/C 45 44 TGND3 TRING3 TTIP3 42 43 RRING2 RTIP2 TRING2 TGND2 38 39 40 41 RTIP1 TVCC2 TTIP2 36 37 35 32 TGND1 TRING1 TTIP1 29 30 31 TGND0 RTIP0 RRING0 TVCC1 RRING1 28 TRING0 33 34 26 27 RCLK0 RPOS0 TTIP0 TPOS0 TNEG0 15 16 TVCC0 TNEG1 RCLK1 RPOS1 TNEG2 RCLK2 RPOS2 RNEG2 RNEG3 LOS3 Package Topside Markings Marking Definition Part # Unique identifier for this product family. Rev # Identifies the particular silicon “stepping” — refer to the specification update for additional stepping information. Lot # Identifies the batch. FPO # Datasheet Identifies the Finish Process Order. 9 LXT386 — QUAD T1/E1/J1 Transceiver Figure 4. LXT386 Plastic Ball Grid Array (PBGA) 160 Ball Assignments 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A N/C N/C N/C TVCC N/C GND N/C N/C GND N/C VCC N/C N/C N/C A B GND GND GND TVCC N/C GND N/C N/C GND N/C VCC GND GND GND B C N/C N/C N/C VCC N/C GND N/C N/C GND N/C VCC N/C N/C N/C C D GND GND GND VCC N/C GND N/C N/C GND N/C VCC GND GND GND D E OE CLKE N/C N/C N/C N/C MODE MCLK E F TCK TDO TDI TMS A 4 A 3 A 2 A 1 F G VCC AT 2 TRST GND GND A 0 D0 VCC G GND D1 D2 VCC H LXT386BE (BOTTOM VIEW) H VCC AT 1 MOT GND J DS R/W ALE CS D3 D4 D5 D6 J K ACK INT LOS 2 LOS 3 LOS 0 LOS 1 MUX D7 K L TCLK 2 TPOS 2 TNEG 2 TVCC 2 TTIP 2 TGND 2 RRING RRING 2 1 TGND 1 TTIP 1 TVCC 1 TNEG 1 TPOS 1 TCLK 1 L M RCLK 2 RPOS 2 RNEG 2 TVCC 2 TRING 2 TGND 2 RTIP 2 RTIP 1 TGND 1 TRING 1 TVCC 1 RNEG 1 RPOS 1 RCLK 1 M N TCLK 3 TPOS 3 TNEG 3 TVCC 3 TTIP 3 TGND 3 RRING RRING 3 0 TGND 0 TTIP 0 TVCC 0 TNEG 0 TPOS 0 TCLK 0 N P RCLK 3 RPOS 3 RNEG 3 TVCC 3 TRING 3 TGND 3 RTIP 3 RTIP 0 TGND 0 TRING 0 TVCC 0 RNEG 0 RPOS 0 RCLK 0 P 14 13 12 11 10 9 8 7 6 5 4 3 2 1 10 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 1. Ball # PBGA Pin Assignments and Signal Descriptions Pin # LQFP Symbol I/O1 Description Master Clock. MCLK is an independent, free-running reference clock. It’s frequency should be 1.544 MHz for T1 operation and 2.048 MHz for E1 operation. This reference clock is used to generate several internal reference signals: • Timing reference for the integrated clock recovery unit • Timing reference for the integrated digital jitter attenuator • Generation of RCLK signal during a loss of signal condition E1 78 MCLK DI • Reference clock during a blue alarm transmit all ones condition • Reference timing for the parallel processor wait state generation logic If MCLK is High, the PLL clock recovery circuit is disabled. In this mode, the LXT386 operates as simple data receiver. If MCLK is Low, the complete receive path is powered down and the output pins RCLK, RPOS and RNEG are switched to Tri-state mode. MCLK is not required if LXT386 is used as a simple analog front-end without clock recovery and jitter attenuation. Note that wait state generation via RDY/ACK is not available if MCLK is not provided. Mode Select. This pin is used to select the operating mode of the LXT386. In Hardware Mode, the parallel processor interface is disabled and hardwired pins are used to control configuration and report status. In Parallel Host Mode, the parallel port interface pins are used to control configuration and report status. In Serial Host Mode the serial interface pins: SDI, SDO, SCLK and CS are used. E2 79 MODE DI MODE Operating Mode L Hardware Mode H Parallel Host Mode Vcc/2 Serial Host Mode For Serial Host Mode, the pin should connected to a resistive divider consisting of two 10 kΩ resistors across VCC and Ground. F4 89 A4 DI Address Select. In host mode, this pin is Address 4 input pin. In hardware mode this pin must be connected to Ground. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” Datasheet 11 LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Ball # PBGA Pin Assignments and Signal Descriptions (Continued) Pin # LQFP Symbol I/O1 Description Protected Monitoring/Address Select Inputs. Hardware Mode In hardware mode these pins are used to select a specific port for non intrusive monitoring. During protection monitoring receiver 0 inputs are internally connected to a specific transmit or receive port. Receiver 0 routes the data from the selected port to its data and clock recovery circuits. The data on the monitor port can be routed to TTIP0/TRING0 by activating the remote loopback for channel 0 (TCLK0 must be active in order for this operation to take place). In addition, the recovered clock and data can be observed at the RCLK0/RPOS0/RNEG0 outputs. If A0-A3 are Low, the LXT386 is configured as a quad line transceiver without monitoring capability. A3 A2 A1 A0 Selection 0 0 0 0 No Protection Monitoring 0 0 0 1 Receiver 1 0 0 1 0 Receiver 2 F3 88 A3 DI 0 0 1 1 Receiver 3 F2 87 A2 DI 0 1 0 0 Reserved F1 86 A1 DI 0 1 0 1 Reserved G3 85 A0 DI 0 1 1 0 Reserved 0 1 1 1 Reserved 1 0 0 0 No Protection Monitoring 1 0 0 1 Transmitter 1 1 0 1 0 Transmitter 2 1 0 1 1 Transmitter 3 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Transmitter monitoring is not supported when the respective channel is set to analog loopback mode. Host Mode In non-multiplexed host mode, these pins function as non-multiplexed address pins. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” 12 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 1. Ball # PBGA Pin Assignments and Signal Descriptions (Continued) Pin # LQFP Symbol I/O1 Description Loopback Mode Select/Parallel Data bus. Host Mode: When a non-multiplexed microprocessor interface is selected, these pins function as a bi-directional 8-bit data port. When a multiplexed microprocessor interface is selected, these pins carry both bi-directional 8-bit data and address inputs A0 -A7. In serial Mode, D0-7 should be grounded. Hardware Mode: In hardware mode, the LXT386 works in normal operation if this pin is left open (unconnected). G2 90 D0/LOOP0 DI/O H3 91 D1/LOOP1 DI/O H2 92 D2/LOOP2 DI/O J4 93 D3/LOOP3 DI/O J3 94 D4/DLOOP0 DI/O J2 95 D5/DLOOP1 DI/O J1 96 D6/DLOOP2 DI/O K1 97 D7/DLOOP3 DI/O The LXT386 enters remote loopback mode if LOOP is Low. In this mode, data on TPOS and TNEG is ignored and data received on RTIP and RRING is looped around and retransmitted on TTIP and TRING. Note: in data recovery mode, the pulse template cannot be guaranteed while in a remote loopback. The LXT386 enters analog local loopback mode if LOOP=1 and DLOOP=0. In this mode, data received on RTIP and RRING is ignored and data transmitted on TTIP and TRING is internally looped around and routed back to the receive inputs. The LXT386 enters digital local loopback if LOOP=1 and DLOOP=1. In this mode, data received on TCLK/TPOS/TNEG is digitally looped back to RCLK/RPOS/RNEG. LOOP DLOOP Operating Mode Open x Normal Mode 0 x Remote Loopback 1 0 Analog Local Loopback 1 1 Digital Local Loopback Note: Note: when these inputs are left open, they stay in a high impedance state. Therefore, the layout design should not route signals with fast transitions near the LOOP pins. This practice will minimize capacitive coupling. L1 12 L2 13 L3 14 M1 15 M2 16 M3 17 K3 18 TCLK1 DI Transmit Clock. TPOS1/ DI Transmit Positive Data. TDATA1 DI Transmit Data. TNEG1/ DI Transmit Negative Data. UBS1 DI Unipolar/Bipolar Select. RCLK1 DO Receive Clock. Receive Positive Data. RPOS1/ DO RDATA1 DO Receive Data. RNEG1/ DO Receive Negative Data. BPV1 DO Bipolar Violation Detect. LOS1 DO Loss of Signal. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” Datasheet 13 LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Ball # PBGA Pin Assignments and Signal Descriptions (Continued) Pin # LQFP Symbol I/O1 Description Transmit Clock. During normal operation TCLK is active, and TPOS and TNEG are sampled on the falling edge of TCLK. If TCLK is Low, the output drivers enter a low power high Z mode. If TCLK is High for more than 16 clock cycles the pulse shaping circuit is disabled and the transmit output pulse widths are determined by the TPOS and TNEG duty cycles. When pulse shaping is disabled, it is possible to overheat and damage the LXT384 device by leaving transmit inputs high continuously. For example a programmable ASIC might leave all outputs high until it is programmed. To prevent this, clock one of these signals: TPOS, TNEG, TCLK or MCLK. Another solution is to set one of these signals low: TPOS, TNEG, TCLK, or OE. N1 19 TCLK0 DI TCLK Operating Mode Clocked Normal operation H TAOS (if MCLK supplied) H Disable transmit pulse shaping (when MCLK is not available) L Driver outputs enter tri-state Note that the TAOS generator uses MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. Transmit Positive Data. Transmit Data. Transmit Negative Data. Unipolar/Bipolar Select. N2 N3 20 21 TPOS0/ DI Bipolar Mode: TDATA0 DI TPOS/TNEG are active high NRZ inputs. TPOS indicates the transmission of a positive pulse whereas TNEG indicates the transmission of a negative pulse. TNEG0/ DI UBS0 DI TPOS TNEG Selection 0 0 Space 1 0 Positive Mark 0 1 Negative Mark 1 1 Space Unipolar Mode: When TNEG/UBS is pulled High for more than 16 consecutive TCLK clock cycles, unipolar I/O is selected. In unipolar mode, B8ZS/HDB3 or AMI encoding/decoding is determined by the CODEN pin (hardware mode) or by the CODEN bit in the GCR register (software mode). TDATA is the data input in unipolar I/O mode. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” 14 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 1. Ball # PBGA Pin Assignments and Signal Descriptions (Continued) Pin # LQFP Symbol I/O1 Description Receive Clock. Normal Mode: P1 22 RCLK0 DO This pin provides the recovered clock from the signal received at RTIP and RRING. Under LOS conditions there is a transition from RCLK signal (derived from the recovered data) to MCLK signal at the RCLK output. Data Recovery Mode: If MCLK is High, the clock recovery circuit is disabled and RPOS and RNEG are internally connected to an EXOR that is fed to the RCLK output for external clock recovery applications. RCLK will be in high impedance state if the MCLK pin is Low. Receive Positive. Receive Data. Receive Negative Data. Bipolar Violation Detect. Bipolar Mode: P2 23 RPOS0/ DO RDATA0 DO In clock recovery mode these pins act as active high bipolar non return to zero (NRZ) receive signal outputs. A High signal on RPOS corresponds to receipt of a positive pulse on RTIP/RRING. A High signal on RNEG corresponds to receipt of a negative pulse on RTIP/RRING. These signals are valid on the falling or rising edges of RCLK depending on the CLKE input. In Data recovery Mode these pins act as RZ data receiver outputs. The output polarity is selectable with CLKE (Active High output polarity when CLKE is High and Active Low Polarity when CLKE is Low). RPOS and RNEG will go to the high impedance state when the MCLK pin is Low. Unipolar Mode: P3 24 RNEG0/ DO BPV0 DO In uni-polar mode, the LXT386 asserts BPV High if any in-service Line Code Violation is detected. RDATA acts as the receive data output. Hardware Mode: During a LOS condition, RPOS and RNEG will remain active. Host Mode: RPOS and RNEG will either remain active or insert AIS into the receive path. Selection is determined by the RAISEN bit in the GCR register. K4 25 LOS0 DO Loss of Signal. LOS goes High to indicate a loss of signal, i.e. when the incoming signal has no transitions for a specified time interval. The LOS condition is cleared and the output pin returns to Low when the incoming signal has sufficient number of transitions in a specified time interval. See “Loss of Signal Detector” on page 24. Multiplexed/Non-Multiplexed Select. K2 99 MUX DI N4, P4 26 TVCC0 S When Low the parallel host interface operates in non-multiplexed mode. When High the parallel host interface operates in multiplexed mode. In hardware mode tie this unused input low. Transmit Driver Power Supply. Power supply pin for the port 0 output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter description. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” Datasheet 15 LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Ball # PBGA Pin Assignments and Signal Descriptions (Continued) Pin # LQFP Symbol I/O1 Description Transmit Tip. Transmit Ring. N5 27 TTIP0 AO P5 28 TRING0 AO N6, P6 29 TGND0 S P7 30 RTIP0 AI Receive Ring. N7 31 RRING0 AI These pins are the inputs to the differential line receiver. Data and clock are recovered and output on the RPOS/RNEG and RCLK pins. L6, M6 32 TGND1 S Transmit Driver Ground. M5 33 TRING1 AO Transmit Ring. L5 34 TTIP1 AO Transmit Tip. L4, M4 35 TVCC1 S Transmit Driver Power Supply. Power supply pin for the port 1 output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter description. These pins are differential line driver outputs. TTIP and TRING will be in high impedance state if the TCLK pin is Low or the OE pin is Low. In software mode, TTIP and TRING can be tristated on a port-by-port basis by writing a ‘1’ to the OEx bit in the Output Enable Register (OER). Transmit Driver Ground. Ground pin for the output driver. Receive Tip. L7 36 RRING1 AI Receive Ring. M7 37 RTIP1 AI Receive Tip. L11, M11 38 TVCC2 S Transmit Driver Power Supply. Power supply pin for the port 2 output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter description. L10 39 TTIP2 AO Transmit Tip. M10 40 TRING2 AO Transmit Ring. L9, M9 41 TGND2 S Transmit Driver Ground. M8 42 RTIP2 AI Receive TIP. L8 43 RRING2 AI Receive Ring. N9, P9 44 TGND3 S Transmit Driver Ground. P10 45 TRING3 AO Transmit Ring. N10 46 TTIP3 AO Transmit Tip. N11, P11 47 TVCC3 S Transmit Driver Power Supply. Power supply pin for the port 3 output driver. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to the Transmitter description. N8 48 RRING3 AI Receive Ring. P8 49 RTIP3 AI Receive Tip. K11 51 P12 52 P13 53 P14 54 LOS3 DO Loss of Signal. RNEG3/ DO Receive Negative Data. BPV3 DO Bipolar Violation Detect. RPOS3/ DO Receive Positive Data. RDATA3 DO Receive Data. RCLK3 DO Receive Clock. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” 16 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # PBGA Pin # LQFP N12 55 N13 56 N14 Symbol I/O1 TNEG3/ DI Transmit Negative Data. UBS3 DI Unipolar/Bipolar Select. Description TPOS3/ DI Transmit Positive Data. TDATA3 DI Transmit Data. 57 TCLK3 DI Transmit Clock. K12 58 LOS2 DO Loss of Signal. M12 59 RNEG2/ DO Receive Negative Data. BPV2 DO Bipolar Violation Detect. M13 60 M14 61 L12 62 L13 63 L14 64 K13 80 RPOS2/ DO Receive Positive Data. RDATA2 DO Receive Data. RCLK2 DO Receive Clock. TNEG2/ DI Transmit Negative Data. UBS2 DI Unipolar/Bipolar Select. TPOS2/ DI Transmit Positive Data. TDATA2 DI Transmit Data. TCLK2 DI Transmit Clock. DO Interrupt. This active Low, maskable, open drain output requires an external 10k pull up resistor. If the corresponding interrupt enable bit is enabled, INT goes Low to flag the host when the LXT386 changes state (see details in the interrupt handling section). The microprocessor INT input should be set to level triggering. INT Data Transfer acknowledge (Motorola Mode). Ready (Intel mode). Serial Data Output (Serial Mode). Motorola Mode K14 81 ACK/ DO RDY/ DO SDO DO A Low signal during a databus read operation indicates that the information is valid. A Low signal during a write operation acknowledges that a data transfer into the addressed register has been accepted (acknowledge signal).Wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g. read modify write). Intel Mode A High signal acknowledges that a register access operation has been completed (Ready Signal). A Low signal on this pin signals that a data transfer operation is in progress. The pin goes tristate after completion of a bus cycle. Serial Mode If CLKE is High, SDO is valid on the rising edge of SCLK. If CLKE is Low, SDO is valid on the falling edge of SCLK. This pin goes into high Z state during a serial port write access. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” Datasheet 17 LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Ball # PBGA Pin Assignments and Signal Descriptions (Continued) Pin # LQFP Symbol I/O1 Description Data Strobe (Motorola Mode). Write Enable (Intel mode). Serial Data Input (Serial Mode). J14 3 DS/ DI WR/ DI Host Mode SDI/ DI LEN0 DI This pin acts as data strobe in Motorola mode and as Write Enable in Intel mode. In serial mode this pin is used as Serial Data Input. Line Length Equalizer (Hardware Mode). Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Refer to Table 2. Read/Write (Motorola Mode). Read Enable (Intel mode). Line Length Equalizer (Hardware Mode). J13 2 R / W/ DI Host Mode RD/ DI LEN1 DI This pin functions as the read/write signal in Motorola mode and as the Read Enable in Intel mode. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Refer to Table 2. Address Latch Enable (Host Mode). Shift Clock (Serial Mode). Address Strobe (Motorola Mode). Line Length Equalizer (Hardware Mode). J12 82 ALE/ DI Host Mode SCLK/ DI AS/ DI The address on the multiplexed address/data bus is clocked into the device with the falling edge of ALE. LEN2 DI In serial Host mode this pin acts as serial shift clock. In Motorola mode this pin acts a an active Low address strobe. Hardware Mode This pin determines the shape and amplitude of the transmit pulse. Refer to Table 2. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” 18 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 1. Pin Assignments and Signal Descriptions (Continued) Ball # PBGA Pin # LQFP Symbol I/O1 Description Chip Select/Jitter Attenuator Select. Host Mode This active Low input is used to access the serial/parallel interface. For each read or write operation, CS must transition from High to Low, and remain Low. Hardware Mode J11 98 CS/ DI JASEL DI This input determines the Jitter Attenuator position in the data path: JASEL JA Position L Transmit path H Receive path Z Disabled Motorola/Intel/Codec Enable Select. Host Mode: When Low, the host interface is configured for Motorola microcontrollers. When High, the host interface is configured for Intel microcontrollers. H12 MOT/INTL/ CODEN 1 Hardware Mode: DI DI This pin determines the line encode/decode selection when in unipolar mode: When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1 respectively. When High, enables AMI encoder/decoder (transparent mode). G13 76 AT2 AO JTAG Analog Output Test Port 2. H13 77 AT1 AI JTAG Analog Input Test Port 1. G12 72 TRST F11 71 TMS DI JTAG Test Mode Select. Used to control the test logic state machine. Sampled on rising edge of TCK. TMS is pulled up internally and may be left disconnected. F14 69 TCK DI JTAG Clock. Clock input for JTAG. Connect to GND when not used. F13 73 TDO DO JTAG Data Output. Test Data Output for JTAG. Used for reading all serial configuration and test data from internal test logic. Updated on falling edge of TCK. F12 70 TDI DI JTAG Data Input. Test Data input for JTAG. Used for loading serial instructions and data into internal test logic. Sampled on rising edge of TCK. TDI is pulled up internally and may be left disconnected. DI Output Driver Enable. If this pin is asserted Low all analog driver outputs immediately enter a high impedance mode to support redundancy applications without external mechanical relays. All other internal circuitry stays active. In software mode, TTIP and TRING can be tristated on a port-by-port basis by writing a ‘1’ to the OEx bit in the Output Enable Register (OER). E14 83 OE JTAG Controller Reset. Input is used to reset the JTAG controller. TRST is pulled up internally and may be left disconnected. 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” Datasheet 19 LXT386 — QUAD T1/E1/J1 Transceiver Table 1. Ball # PBGA Pin Assignments and Signal Descriptions (Continued) Pin # LQFP Symbol I/O1 Description Clock Edge Select. In clock recovery mode, setting CLKE High causes RDATA or RPOS and RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge of SCLK. Setting CLKE Low makes RDATA or RPOS and RNEG to be valid on the rising edge of RCLK and SDO to be valid on the falling edge of SCLK. In Data recovery Mode, RDATA or RPOS/RNEG are active High output polarity when CLKE is High and active low polarity when CLKE is Low. E13 84 CLKE DI CLKE N/C2 RPOS/RNEG SDO Low RCLK SCLK High RCLK SCLK 100 RESET DI Reset Input. (Added in Revision B1) In either hardware mode or software mode, setting RESET low will begin to initialize the LXT386 and freeze the device until set high. One microsecond after setting RESET high, initialization will complete and the LXT386 will be ready for normal operation. For Revision B1 only, the device requires a pull up resistor to VCC at this pin between 1 and 10 kohms in value. It is not necessary to retain the pull up resistor for any other revision. Please refer to the section on Reset Operation for more information. The BGA package does not have this pin feature. 5, 7, 10, 11, 65, 66, 74 GND S Power Supply Ground. Connect all pins to power supply ground. A6, A9 B: 1, 2, 3, 6, 9, 12, 13, 14 C6, C9 D: 1, 2, 3, 6, 9, 12, 13, 14 G4, G11 H4, H11 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” 20 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 1. Ball # PBGA Pin Assignments and Signal Descriptions (Continued) Pin # LQFP Symbol I/O1 4, 6, 8, 9, 67, 68, 75, VCC S Power Supply. Connect all pins to +3.3 volt power supply. - TVCC S Transmit Driver Power Supply. Power supply pins for the output drivers. TVCC pins can be connected to either a 3.3V or 5V power supply. Refer to “Transmitter” on page 25 for details. 50 N/C NC Description A4, B4, C4, C11, D4, D11, G1, G14, H1, H14 A11, B11 A: 1, 2, 3, 5, 7, 10, 12, 13, 14 B: 7, 8, 10 C: 1, 2, 3, 5, 7, 8, 10, 12, 13, 14 Not Connected. These pins must be left open for normal operation. D: 5, 7, 8, 10 E: 3, 4, 11, 12 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply; N.C.: Not Connected. 2. N/C means “Not Connected” Datasheet 21 LXT386 — QUAD T1/E1/J1 Transceiver 3.0 Functional Description Figure 1 is a simplified block diagram of the LXT386. The LXT386 is a fully integrated quad line interface unit designed for T1 1.544 Mbps and E1 2.048 Mbps short haul applications. Each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive. These two lines comprise a digital data loop for full duplex transmission. The LXT386 can be controlled through hard-wired pins or by a microprocessor through a serial or parallel interface (Host mode). The transmitter timing reference is TCLK, and the receiver reference clock is MCLK. The LXT386 is designed to operate without any reference clock when used as an analog front-end (line driver and data recovery). MCLK is mandatory if the on chip clock recovery capability is used. All four clock recovery circuits share the same reference clock defined by the MCLK input signal. 3.1 Initialization During power up, the transceiver remains static until the power supply reaches approximately 60% of VCC. During power-up, an internal reset sets all registers to their default values and resets the status and state machines for the LOS. 3.1.1 Reset Operation In Revision B1, no connect pin 100 was converted to the RESET pin. Only revision B1 requires a pull up resistor to VCC at pin 100, the pull up resistor is unnecessary for all other revisions. Figure 4 shows the connections needed for revision B1 only. Note: The BGA package does not have a RESET pin. There are two methods of resetting the LXT386: 1. Override Reset - Setting the RESET pin low in either hardware mode or host mode. Until the RESET pin returns high, the LXT386 remains frozen and will not function. Once the RESET pin has returned high, the LXT386 will operaate normally. Override Reset changes all the internal registers to their default values. 2. Software Reset - Writing to the RES reset register initiates a 1microsecond reset cycle, except in Intel non-multiplexed mode. In Intel non-multiplexed mode, the reset cycle takes 2 microseconds. Please refer to Host mode section for more information. This operation changes all LXT386 registers to their default values. 22 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 5. Pullup Resistor to RESET VCC 1K 100 RESET LXT386LE 3.2 Receiver The four receivers in the LXT386 are identical. The following paragraphs describe the operation of one. The twisted-pair input is received via a 1:2 step down transformer. Positive pulses are received at RTIP, negative pulses at RRING. Recovered data is output at RPOS and RNEG in the bipolar mode and at RDATA in the unipolar mode. The recovered clock is output at RCLK. RPOS/RNEG validation relative to RCLK is pin selectable (CLKE). The receive signal is processed through the peak detector and data slicers. The peak detector samples the received signal and determines its maximum value. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For DSX-1 applications (line length inputs LEN2-0 from 011 to 111) the threshold is set to 70% (typical) of the peak value. This threshold is maintained above the specified level for up to 15 successive zeros over the range of specified operating conditions. For E1 applications (LEN2-0 = 000), the threshold is 50% (typical). The receiver is capable of accurately recovering signals with up to 12 dB of attenuation (from 2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is 1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level, the peak detectors are held above a minimum level of 0.150 V (typical) to provide immunity from impulsive noise. After processing through the data slicers, the received signal goes to the data and timing recovery section. The data and timing recovery circuits provide an input jitter tolerance better than required by Pub 62411 and ITU G.823, as shown in Test Specifications, Figure 33. Depending on the options selected, recovered clock and data signals may be routed through the jitter attenuator, through the B8ZS/HDB3/AMI decoder, and may be output to the framer as either bipolar or unipolar data. Datasheet 23 LXT386 — QUAD T1/E1/J1 Transceiver 3.2.1 Loss of Signal Detector The loss of signal detector in the LXT386 uses a dedicated analog and digital loss of signal detection circuit. It is independent of its internal data slicer comparators and complies to the latest ITU G.775 and ANSI T1.231 recommendations. Under software control, the detector can be configured to comply to the ETSI ETS 300 233 specification (LACS Register). In hardware mode, the LXT386 supports LOS per G.775 for E1 and ANSI T1.231 for T1 operation. The receiver monitor loads a digital counter at the RCLK frequency. The counter is incremented each time a zero is received, and reset to zero each time a one (mark) is received. Depending on the operation mode, a certain number of consecutive zeros sets the LOS signal. The recovered clock is replaced by MCLK at the RCLK output with a minimum amount of phase errors. MCLK is required for receive operation. When the LOS condition is cleared, the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will reflect the data content at the receiver input during the entire LOS detection period for that channel. 3.2.1.1 E1 Mode In G.775 mode a loss of signal is detected if the signal is below 200mV (typical) for 32 consecutive pulse intervals. When the received signal reaches 12.5% ones density (4 marks in a sliding 32-bit period) with no more than 15 consecutive zeros and the signal level exceeds 250mV (typical), the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. In ETSI 300 233 mode, a loss of signal is detected if the signal is below 200mV for 2048 consecutive intervals (1 ms). The LOS condition is cleared and the output pin returns to Low when the incoming signal has transitions when the signal level is equal or greater than 250mV for more than 32 consecutive pulse intervals. This mode is activated by setting the LACS register bit to one. If it is necessary to use AIS with LOS, see errata 10.3 for a way to implement this. 3.2.1.2 T1 Mode The T1.231 LOS detection criteria is employed. LOS is detected if the signal is below 200mV for 175 contiguous pulse positions. The LOS condition is terminated upon detecting an average pulse density of 12.5% over a period of 175 contiguous pulse positions starting with the receipt of a pulse. The incoming signal is considered to have transitions when the signal level is equal or greater than 250mV. 3.2.1.3 Data Recovery Mode In data recovery mode the LOS digital timing is derived from a internal self timed circuit. RPOS/ RNEG stay active during loss of signal. The analog LOS detector complies with ITU-G.775 recommendation. The LXT386 monitors the incoming signal amplitude. Any signal below 200mV for more than 30µs (typical) will assert the corresponding LOS pin. The LOS condition is cleared when the signal amplitude rises above 250mV. The LXT386 requires more than 10 and less than 255 bit periods to declare a LOS condition in accordance to ITU G.775. 3.2.2 Alarm Indication Signal (AIS) Detection The AIS detection is performed by the receiver independent of any loopback mode. This feature is available in host mode only. Because there is no clock in data recovery mode, AIS detection will not work in that mode. AIS requires MCLK to have clock applied, since this function depends on the clock to count the number of ones in an interval. 24 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 3.2.2.1 E1 Mode One detection mode suitable for both ETSI and ITU is available when the LACS register bits are cleared to zero. If the LACS register bit is set to one, see errata 10.3 to implement this: ETSI ETS300233 and G.775 detection The AIS condition is declared when the received data stream contains less than 3 zeros within a period of 512 bits. The AIS condition is cleared when 3 or more zeros within 512 bits are detected. 3.2.2.2 T1 Mode ANSI T1.231 detection is employed. The AIS condition is declared when less than 9 zeros are detected in any string of 8192 bits. This corresponds to a 99.9% ones density over a period of 5.3ms. The AIS condition is cleared when the received signal contains 9 or more zeros in any string of 8192 bits. 3.2.3 In Service Code Violation Monitoring In unipolar I/O mode with HDB3/B8ZS decoding, the LXT386 reports bipolar violations on RNEG/BPV for one RCLK period for every HDB3/B8ZS code violation that is not part of the zero code substitution rules. In AMI mode, all bipolar violations (two consecutive pulses with the same polarity) are reported at the BPV output. 3.3 Transmitter The four low power transmitters of the LXT386 are identical. Transmit data is clocked serially into the device at TPOS/TNEG in the bipolar mode or at TDATA in the unipolar mode. The transmit clock (TCLK) supplies the input synchronization. Unipolar I/O and HDB3/B8ZS/AMI encoding/decoding is selected by pulling TNEG High for more than 16 consecutive TCLK clock cycles. The transmitter samples TPOS/TNEG or TDATA inputs on the falling edge of TCLK. Refer to the Test Specifications Section for MCLK and TCLK timing characteristics. If TCLK is not supplied, the transmitter remains powered down and the TTIP/ TRING outputs are held in a High Z state. In addition, fast output tristatability is also available through the OE pin (all ports) and/or the port’s OEx bit in the Output Enable Register (OER). Zero suppression is available only in Unipolar Mode. The two zero-suppression types are B8ZS, used in T1 environments, and HDB3, used in E1 environments. The scheme selected depends on whether the device is set for T1 or E1 operation (determined by LEN2-0 pulse shaping settings). The LXT386 also supports AMI line coding/decoding as shown in Figure 6. In Hardware mode, AMI coding/decoding is selected by the CODEN pin. In host mode, AMI coding/decoding is selected by bit 4 in the GCR (Global Control Register). Datasheet 25 LXT386 — QUAD T1/E1/J1 Transceiver Figure 6. 50% AMI Encoding TTIP Bit Cell 1 0 1 TRING Each output driver is supplied by a separate power supply (TVCC and TGND). The transmit pulse shaper is bypassed if no MCLK is supplied while TCLK is pulled high. In this case TPOS and TNEG control the pulse width and polarity on TTIP and TRING. With MCLK supplied and TCLK pulled high the driver enters TAOS (Transmit All Ones pattern). Note that the TAOS generator uses MCLK as a timing reference. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability.TAOS is inhibited during Remote Loopback. 3.3.1 Transmit Pulse Shaping The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The line driver provides a constant low output impedance regardless of whether it is driving marks, spaces or if it is in transition. This well controlled dynamic impedance provides excellent return loss when used with external precision resistors (± 1% accuracy) in series with the transformer. 3.3.1.1 Hardware Mode In hardware mode, pins LEN0-2 determine the pulse shaping as described in Table 2. The LEN settings also determine whether the operating mode is T1 or E1. Note that in T1 operation mode, all four ports will share the same pulse shaping setting. Independent pulse shaping for each channel is available in host mode 3.3.1.2 Host Mode In Host Mode, the contents of the Pulse Shaping Data Register (PSDAT) determines the shape of pulse output at TTIP/TRING. Refer to Table 24 and Table 25. 26 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 . Table 2. Line Length Equalizer Inputs Line Length1 Cable Loss2 LEN2 LEN1 LEN0 0 1 1 0 - 133 ft. ABAM 0.6 dB 1 0 0 133 - 266 ft. ABAM 1.2 dB 1 0 1 266 - 399 ft. ABAM 1.8 dB 0 399 - 533 ft. ABAM 2.4 dB 533 - 655 ft. ABAM 3.0 dB 1 1 1 1 1 0 0 0 E1 G.703, 75Ω coaxial cable and 120 Ω twisted pair cable. Operation Mode T1 E1 1. Line length from LXT386 to DSX-1 cross-connect point. 2. Maximum cable loss at 772KHz. 3.3.2 Transmit Pulse Shaping The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The line driver provides a constant low output impedance regardless of whether it is driving marks. 3.3.2.1 Output Driver Power Supply The output driver power supply (TVCC pins) can be either 3.3V or 5V nominal. When TVCC=5V, LXT386 drives both E1 (75Ω/120Ω) and T1 100Ω lines through a 1:2 transformer and 11Ω/9.1Ω series resistors. When TVCC=3.3V, the LXT386 drives E1 (75Ω/120Ω) lines through a 1:2 transformer and 11Ω series resistor. A configuration with a 1:2 transformer and without series resistors should be used to drive T1 100Ω lines. Removing the series resistors for T1 applications with TVCC=3.3V, improves the power consumption of the device. See Table 35. On the other hand, series resistors in the transmit configuration improve the transmit return loss performance. Good transmit return loss performance minimizes reflections in harsh cable environments. In addition, series resistors provide protection against surges coupled to the device. The resistors should be used in systems requiring protection switching without external relays. Please refer to Figure 7 for the recommended external line circuitry. 3.3.2.2 Power Sequencing For the LXT384, we recommend sequencing TVCC first then VCC second or at the same time as TVCC to prevent excessive current draw. 3.4 Driver Failure Monitor The LXT386 transceiver incorporates an internal power Driver Failure Monitor (DFM) in parallel with TTIP and TRING that is capable of detecting secondary shorts without cable. DFM is available only in configurations with no transmit series resistors (T1 mode with TVCC=3.3V). This feature is available in the serial and parallel host modes but not available in the hardware mode of operation. Datasheet 27 LXT386 — QUAD T1/E1/J1 Transceiver A capacitor, charged via a measure of the driver output current and discharged by a measure of the maximum allowable current, is used to detect a secondary short failure. Secondary shorted lines draw excess current, overcharging the cap. When the capacitor charge deviates outside the nominal charge window, a driver short circuit fail (DFM) is reported in the respective register by setting an interrupt. During a long string of spaces, a short-induced overcharge eventually bleeds off, clearing the DFM flag. Note that unterminated lines of adequate length (λ/4) may effectively behave as short-circuits as seen by the driver and therefore trigger the DFM. Under these circumstances, the alarm should be disabled. In addition, LXT386 features output driver short-circuit protection. When the output current exceeds 100 mA, LXT386 limits the driver’s output voltage to avoid damage. 3.5 Line Protection Figure 7 on page 29 shows recommended line interface circuitry. In the receive side, the 1 kΩ series resistors protect the receiver against current surges coupled into the device. Due to the high receiver impedance (70 kΩ typical) the resistors do not affect the receiver sensitivity. In the transmit side, the Schottky diodes D1-D4 protect the output driver.While not mandatory for normal operation, these protection elements are strongly recommended to improve the design robustness. 28 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 7. External Transmit/Receive Line Circuitry TVCC TVCC TVCC TVCC 68µF TVS1 TVS1 1 0.1µF TVCC TGND TVCC D4 RT 1:2 TTIP D3 3.3V VCC TVCC 0.1µF Tx LINE 2 560pF D2 GND TRING D1 RTT 3 LXT386 (ONE CHANNEL) CHANNEL) (ONE 1kΩ 1kΩ 1:2 1:2 RTIP RTIP R RR R RR R R RRING RRING Datasheet 0.22µF 0.22µF Rx Rx LINE LINE 1kΩ 1kΩ 1 1 Common decoupling capacitor for all TVCC and TGND pins. Common decoupling capacitor for all TVCC and TGND pins. 2 2 Typical value. Adjust for actual board parasitics to obtain optimum return loss. Typical value. Adjust for actual board parasitics to obtain optimum return loss. 3 3 Refer to Transformer Specifications Table for transformer specifications. Refer to Transformer Specifications Table for transformer specifications. 29 LXT386 — QUAD T1/E1/J1 Transceiver 3.6 Jitter Attenuation A digital Jitter Attenuation Loop (JAL) combined with a FIFO provides Jitter attenuation. The JAL is internal and requires no external crystal nor high-frequency (higher than line rate) reference clock. In Host Mode, the Global Control Register (GCR) determines whether the JAL is positioned in the receive or transmit path. In Hardware Mode, the JAL position is determined by the JASEL pin. The FIFO is a 32 x 2-bit or 64 x 2-bit register (selected by the FIFO64 bit in the GCR). Data is clocked into the FIFO with the associated clock signal (TCLK or RCLK), and clocked out of the FIFO with the dejittered JAL clock. See Figure 8. When the FIFO is within two bits of overflowing or underflowing, the FIFO adjusts the output clock by 1/8 of a bit period. The Jitter Attenuator produces a constant delay of 17 or 33 bits in the associated path (refer to test specifications). This feature can be used for hitless switching applications. This advanced digital jitter attenuator meets latest jitter attenuation specifications. See Table 3. Under software control, the low limit jitter attenuator corner frequency depends on FIFO length and the JACF bit setting (this bit is in the GCR register). In Hardware Mode, the FIFO length is fixed to 64 bits. The corner frequency is fixed to 6 Hz for T1 mode and 3.5 Hz for E1 mode. Table 3. Jitter Attenuation Specifications T1 E1 AT&T Pub 62411 ITU-T G.736 GR-253-CORE1 ITU-T G.7423 ITU-T G.7834 TR-TSY-0000092 ETSI CTR12/13 BAPT 220 1. 2. 3. 4. 30 Category I, R5-203. Section 4.6.3. Section 6.2 When used with the SXT6234 E2-E1 mux/demux. Section 6.2.3.3 combined jitter when used with the SXT6251 21E1 mapper. Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 8. Jitter Attenuator Loop FIFO64 TPOS RPOSi TPOSo RPOS TNEG RNEGi TNEGo RNEG FIFO IN CK TCLK RCLKi IN OUT CK DPLL TCLK RCLK OUT JASEL0-1 JASEL0-1 x 32 MCLK JACF GCR control bits 3.7 Loopbacks The LXT386 offers three loopback modes for diagnostic purposes. In hardware mode, the loopback mode is selected with the LOOPn pins. In software mode, the ALOOP, DLOOP and RLOOP registers are employed. 3.7.1 Analog Loopback When selected, the transmitter outputs (TTIP & TRING) are connected internally to the receiver inputs (RTIP & RRING) as shown in Figure 9. Data and clock are output at RCLK, RPOS & RNEG pins for the corresponding transceiver. Note that signals on the RTIP & RRING pins are ignored during analog loopback. TCLK TPOS TNEG HDB3/B8ZS Encoder* JA* RCLK RPOS RNEG HDB3/B8ZS Decoder* Figure 9. Analog Loopback JA* Timing & Control TTIP Timing Recovery RTIP TRING RRING * If Enabled Datasheet 31 LXT386 — QUAD T1/E1/J1 Transceiver 3.7.2 Digital Loopback The digital loopback function is available in software and hardware mode. When selected, the transmit clock and data inputs (TCLK, TPOS & TNEG) are looped back and output on the RCLK, RPOS & RNEG pins (Figure 10). The data presented on TCLK, TPOS & TNEG is also output on the TTIP & TRING pins. Note that signals on the RTIP & RRING pins are ignored during digital loopback. RCLK RPOS RNEG HDB3/B8ZS Encoder* TCLK TPOS TNEG Timing & Control TTIP JA* HDB3/B8ZS Decoder* Figure 10. Digital Loopback JA* Timing Recovery RTIP TRING RRING * If Enabled 3.7.3 Remote Loopback During remote loopback (Figure 11) the RCLK, RPOS & RNEG outputs routed to the transmit circuits and output on the TTIP & TRING pins. Note that input signals on the TCLK, TPOS & TNEG pins are ignored during remote loopback. TCLK TPOS TNEG HDB3/B8ZS Encoder* JA* RCLK RPOS RNEG HDB3/B8ZS Decoder* Figure 11. Remote Loopback JA* Timing & Control TTIP Timing Recovery RTIP TRING RRING * If Enabled Note: 3.7.4 In data recovery mode, the pulse template cannot be guaranteed while in a remote loopback. Transmit All Ones (TAOS) In Hardware mode, the TAOS mode is set by pulling TCLK High for more than 16 MCLK cycles. In software mode, TAOS mode is set by asserting the corresponding bit in the TAOS Register. In addition, automatic ATS insertion (in case of LOS) may be set using the ATS Register. Note: The TAOS generator uses MCLK as a timing reference, therefore TAOS doesn’t work in data recovery mode. In order to assure that the output frequency is within specification limits, MCLK must have the applicable stability. DLOOP does not function with TAOS active. 32 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 12. TAOS Data Path MCLK TCLK TPOS TNEG HDB3/B8ZS Encoder* RCLK RPOS RNEG HDB3/B8ZS Decoder* TAOS mode Timing & Control TTIP TRING (ALL 1’s) Timing Recovery JA* RTIP RRING * If Enabled Figure 13. TAOS with Analog Loopback MCLK TAOS Mode RCLK RPOS RNEG Timing & Control HDB3/B8ZS Encoder* HDB3/B8ZS Decoder* TCLK TPOS TNEG TTIP TRING (ALL 1’s) JA* Timing Recovery RTIP RRING * If Enabled 3.8 G.772 Performance Monitoring The LXT386 can be configured as a quad line interface unit with all channels working as regular transceivers. In applications using only three channels, the fourth channel can be configured to monitor any of the remaining channels inputs or outputs. The monitoring is non-intrusive per ITUT G.772. Figure 2 on page 8 illustrates this concept. The monitored line signal (input or output) goes through channel 0 clock and data recovery. The signal can be observed digitally at the RCLK/RPOS/RNEG outputs. This feature can also be used to create timing interfaces derived from an E1 or T1 signal. In addition, channel 0 can be configured to a Remote Loopback while in monitoring mode (TCLK0 must be active in order for this operation to take place). This will output the same data as in the signal being monitored at the channel 0 output (TTIP/TRING). The output signal can then be connected to a standard test equipment with a T1/E1 electrical interface for monitoring purposes (non-intrusive monitoring). Datasheet 33 LXT386 — QUAD T1/E1/J1 Transceiver 3.9 Hitless Protection Switching (HPS) The LXT386 transceivers include an output driver tristatability feature for T1/E1 redundancy applications. This feature greatly reduces the cost of implementing redundancy protection by eliminating external relays. Please refer to Application Note 119 for guidelines for implementing redundancy systems for both T1 and E1 operation using the LXT380/1/4/6. 3.10 Operation Mode Summary Table 4 lists summarizes all LXT386 hardware settings and corresponding operating modes. Table 4. Operation Mode Summary MCLK TCLK LOOP1 Receive Mode Transmit Mode Loopback Clocked Clocked Open Data/Clock recovery Pulse Shaping ON No Loopback Clocked Clocked L Data/Clock recovery Pulse Shaping ON Remote Loopback Clocked Clocked H Data/Clock recovery Pulse Shaping ON Analog Loopback Clocked L Open Data/Clock recovery Power down No Loopback Clocked L L Data/Clock Recovery Power down No effect on op. Clocked L H Data/Clock Recovery Power down No Analog Loopback Clocked H Open Data/Clock Recovery Transmit All Ones No Loopback Clocked H L Data/Clock Recovery Pulse Shaping ON Remote Loopback Clocked H H Data/Clock Recovery Transmit All Ones No effect on op. L Clocked Open Power Down Pulse Shaping ON No Loopback L Clocked L Power Down Pulse Shaping ON No Remote Loopback L Clocked H Power Down Pulse Shaping ON No effect on op. L H Open Power Down Pulse Shaping OFF No Loopback L H L Power Down Pulse Shaping OFF No Remote Loop L H H Power Down Pulse Shaping OFF No effect on op. L L X Power Down Power down No Loopback H Clocked Open Data Recovery Pulse Shaping ON No Loopback H Clocked L Data Recovery Pulse Shaping OFF Remote Loopback H Clocked H Data Recovery Pulse Shaping ON Analog Loopback H L Open Data Recovery Power down No Loopback H L L Data Recovery Pulse Shaping OFF Remote Loopback H H Open Data Recovery Pulse Shaping OFF No Loopback H H L Data Recovery Pulse Shaping OFF Remote Loopback H H H Data Recovery Pulse Shaping OFF Analog Loopback 1. Hardware mode only. 34 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 3.11 Interfacing with 5V logic The LXT386 can interface directly with 5V logic. The internal input pads are tolerant to 5V outputs from TTL and CMOS family devices. 3.12 Parallel Host Interface The LXT386 incorporates a highly flexible 8-bit parallel microprocessor interface. The interface is generic and is designed to support both non-multiplexed and multiplexed address/data bus systems for Motorola and Intel bus topologies. Two pins (MUX and MOT/INTL) select four different operating modes as shown in Table 5. Table 5. Microprocessor Parallel Interface Selection MUX MOT/INTL Operating Mode Low Low Motorola Non-Multiplexed Low High Intel Non-Multiplexed High Low Motorola Multiplexed High High Intel Multiplexed The interface includes an address bus (A4 - A0) and a data bus (D7 - D0) for non-multiplexed operation and an 8-bit address/data bus for multiplexed operation. WR, RD, R/W, CS, ALE, DS, INT and RDY/ACK are used as control signals. A significant enhancement is an internal wait-state generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In Motorola mode ACK Low signals valid information is on the data bus. During a write cycle a Low signal acknowledges the acceptance of the write data. In Intel mode RDY High signals to the controlling processor that the bus cycle can be completed. While Low the microprocessor must insert wait states. This allows the LXT386 to interface with wait-state capable micro controllers, independent of the processor bus speed. To activate this function a reference clock is required on the MCLK pin. There is one exception to write cycle timing for Intel non-multiplexed mode: Register 0Ah, the reset register. Because of timing issues, the RDY line remains high after the first part of the cycle is done, not signalling write cycle completion with another transition low. In this mode, add 2 microseconds of delay, overall 3 microseconds from CS low to end of cycle, to allow the reset cycle to completely initialize the device before proceeding. An additional active Low interrupt output signal indicates alarm conditions like LOS and DFM to the microprocessor. The LXT386 has a 5 bit address bus and provides 18 user accessible 8-bit registers for configuration, alarm monitoring and control of the chip. 3.12.1 Motorola Interface The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode the falling edge of DS is used to latch the address information on the address bus. In multiplexed operation the address on the multiplexed address data bus is latched into the device with the falling edge of AS. In non-multiplexed mode, AS should be pulled High. Datasheet 35 LXT386 — QUAD T1/E1/J1 Transceiver The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/ W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising edge on DS. Both cycles require the CS signal to be Low and the Address pins to be actively driven by the microprocessor. Note that CS and DS can be connected together in Motorola mode. In a write cycle the data bus is driven by the microprocessor. In a read cycle the bus is driven by the LXT386. 3.12.2 Intel Interface The Intel interface is selected by asserting the MOT/INTL pin High. The LXT386 supports nonmultiplexed interfaces with separate address and data pins when MUX is asserted Low, and multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS is used as the WR signal. A read cycle is indicated to the LXT386 when the processor asserts RD Low while the WR signal is held High. A write operation is indicated to the LXT386 by asserting WR Low while the RD signal is held High. Both cycles require the CS signal to be Low. 3.13 Interrupt Handling Interrupt Sources There are three interrupt sources: 1. Status change in the Loss Of Signal (LOS) status register (04H). The LXT386’s analog/digital loss of signal processor continuously monitors the receiver signal and updates the specific LOS status bit to indicate presence or absence of a LOS condition. 2. Status change in the Driver Failure Monitoring (DFM) status register (05H). The LXT386’s smart power driver circuit continuously monitors the output drivers signal and updates the specific DFM status bit to indicate presence or absence of a secondary driver short circuit condition. 3. Status change in the Alarm Indication Signal (AIS) status register (13H).The LXT386’s receiver monitors the incoming data stream and updates the specific AIS status bit to indicate presence or absence of a AIS condition. 3.13.1 Interrupt Enable The LXT386 provides a latched interrupt output (INT). An interrupt occurs any time there is a transition on any enabled bit in the status register. Registers 06H, 07H and 14H are the LOS, DFM and AIS interrupt enable registers (respectively). Writing a logic “1” into the mask register will enable the respective bit in the respective Interrupt status register to generate an interrupt. The power-on default value is all zeroes. The setting of the interrupt enable bit does not affect the operation of the status registers. Registers 08H, 09H and 15H are the LOS, DFM and AIS (respectively) interrupt status registers. When there is a transition on any enabled bit in a status register, the associated bit of the interrupt status register is set and an interrupt is generated (if one is not already pending). When an interrupt 36 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR operation. 3.13.2 Interrupt Clear When an interrupt occurs, the interrupt service routine (ISR) should read the interrupt status registers (08H, 09H and 15H) to identify the interrupt source. Reading the Interrupt Status register clears the “sticky” bit set by the interrupt. Automatically clearing the register prepares it for the next interrupt. The ISR should then read the corresponding status monitor register to obtain the current status of the device. Note that there are three status monitor registers: the LOS (04H), the DFM (05H) and the AIS (013H). Reading either status monitors register will clear its corresponding interrupts on the rising edge of the read or data strobe. When all pending interrupts are cleared, the INT pin goes High. 3.14 Serial Host Mode The LXT386 operates in Serial Host Mode when the MODE pin is tied to VCC÷2. Figure 14 shows the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/ Address byte (bits R/W and A1-A7) and a subsequent 8bit data byte (bits D0-7). Bit R/W determines whether a read or a write operation occurs. Bits A5-0 in the Command/Address byte address specific registers (the address decoder ignores bits A7-6). The data byte depends on both the value of bit R/W and the address of the register as set in the Command/Address byte. Figure 14. Serial Host Mode Timing CS SCLK INPUT DATA BYTE ADDRESS/COMMAND BYTE SDI R/W A1 A2 A3 A4 A5 SDO - REMAINS HIGH Z A6 X A7 X D0 D1 D2 D3 D4 D5 D6 D7 SDO IS DRIVEN IF R/W = 1 R/W = 1: Read from the LXT386 R/W = 0: Write to the LXT386 X = Don’t care Datasheet 37 LXT386 — QUAD T1/E1/J1 Transceiver 4.0 Register Descriptions Table 6. Serial and Parallel Port Register Addresses Address Name Symbol ID Register Mode Serial Port A7-A1 Parallel Port A7-A0 ID xx00000 xxx00000 R Analog Loopback ALOOP xx00001 xxx00001 R/W Remote Loopback RLOOP xx00010 xxx00010 R/W TAOS Enable TAOS xx00011 xxx00011 R/W LOS Status Monitor LOS xx00100 xxx00100 R DFM Status Monitor DFM xx00101 xxx00101 R LOS Interrupt Enable LIE xx00110 xxx00110 R/W DFM Interrupt Enable DIE xx00111 xxx00111 R/W LOS Interrupt Status LIS xx01000 xxx01000 R DFM Interrupt Status DIS xx01001 xxx01001 R Software Reset Register RES xx01010 xxx01010 R/W Performance Monitoring MON xx01011 xxx01011 R/W Digital Loopback DL xx01100 xxx01100 R/W LOS/AIS Criteria Selection LOSC xx01101 xxx01101 R/W Automatic TAOS Select ATS xx01110 xxx01110 R/W Global Control Register GCR xx01111 xxx01111 R/W Pulse Shaping Indirect Address Register PSIAD xx10000 xxx10000 R/W Pulse Shaping Data Register PSDAT xx10001 xxx10001 R/W Output Enable Register OER xx10010 xxx10010 R/W AIS Status Register AIS xx10011 xxx10011 R AIS Interrupt Enable AISIE xx10100 xxx10100 R/W AIS Interrupt Status AISIS xx10101 xxx10101 R Table 7. Register Bit Names Register Name Bit Sym RW 7 6 5 4 3 2 1 0 ID R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Analog Loopback ALOOP R/W - - - - AL3 AL2 AL1 AL0 Remote Loopback RLOOP R/W - - - - RL3 RL2 RL1 RL0 TAOS R/W - - - - TAOS3 TAOS2 TAOS1 TAOS0 ID Register TAOS Enable 38 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 7. Register Bit Names (Continued) Register Bit Name Sym RW 7 6 5 4 3 2 1 0 LOS Status Monitor LOS R - - - - LOS3 LOS2 LOS1 LOS0 DFM Status Monitor DFM R - - - - DFM3 DFM2 DFM1 DFM0 LOS Interrupt Enable LIE R/W - - - - LIE3 LIE2 LIE1 LIE0 DFM Interrupt Enable DIE R/W - - - - DIE3 DIE2 DIE1 DIE0 LOS Interrupt Status LIS R - - - - LIS3 LIS2 LIS1 LIS0 DFM Interrupt Status DIS R - - - - DIS3 DIS2 DIS1 DIS0 Software Reset Register RES R/W - - - - RES3 RES2 RES1 RES0 Performance Monitoring MON R/W reserve d reserve d reserve d reserve d A3 A2 A1 A0 DL R/W - - - - DL3 DL2 DL1 DL0 Digital Loopback LOS/AIS Criteria Select LACS R/W - - - - LACS3 LACS2 LACS1 LACS0 Automatic TAOS Select ATS R/W - - - - ATS3 ATS2 ATS1 ATS0 Global Control Register GCR R/W reserve d RAISE N CDIS CODEN FIFO64 JACF JASEL1 JASEL0 Pulse Shaping Indirect Address Register PSIAD R/W reserve d reserve d reserve d reserve d reserve d LENAD2 LENAD1 LENAD0 Pulse Shaping Data Register PSDAT R/W reserve d reserve d reserve d reserve d reserve d LEN2 LEN1 LEN0 Output Enable Register OER R/W - - - - OE3 OE2 OE1 OE0 AIS Status Register AIS R - - - - AIS3 AIS2 AIS1 AIS0 AIS Interrupt Enable AISIE R/W - - - - AISIE3 AISIE2 AISIE1 AISIE0 AIS Interrupt Status AISIS R - - - - AISIS3 AISIS2 AISIS1 AISIS0 Table 8. Bit ID Register, ID (00H) Name Function This register contains a unique revision code and is mask programmed. 7-0 ID7-ID0 For Revision A1, ID register = 00h For Revision B1, ID register = 21h For Revision B2, ID register = 22h Table 9. Analog Loopback Register, ALOOP (01H) Bit Name 3-0 AL3-AL0 Datasheet Function Setting a bit to “1” enables analog local loopback for transceivers 3- 0 respectively. 39 LXT386 — QUAD T1/E1/J1 Transceiver Table 10. Remote Loopback Register, RLOOP (02H) Bit Name 3-0 RL3-RL0 Function Setting a bit to “1” enables remote loopback for transceivers 3-0 respectively. Table 11. TAOS Enable Register, TAOS (03H) Bit1 Name 3-0 TAOS3-TAOS0 7-4 - Function2 Setting a bit to “1” causes a continuous stream of marks to be sent out at the TTIP and TRING pins of the respective transceiver 3-0. Write “0” to these positions for normal operation. 1. On power up all register bits are set to “0”. 2. MCLK is used as timing reference. If MCLK is not available then the channel TCLK is used as the reference. This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High) Table 12. LOS Status Monitor Register, LOS (04H) Bit1 Name Function 3-0 LOS3-LOS0 Respective bit(s) are set to “1” every time the LOS processor detects a valid loss of signal condition in transceivers 3-0. 1. On power up all register bits are set to “0”. Any change in the state causes an interrupt. All LOS interrupts are cleared by a single read operation. Table 13. DFM Status Monitor Register, DFM (05H) Bit1 Name 3-0 DFM3-DFM0 Function Respective bit(s) are set to “1” every time the short circuit monitor detects a valid secondary output driver short circuit condition in transceivers 3-0. Note that DFM is available only in configurations with no transmit series resistors (T1 mode with TVCC=3.3V). 1. On power-up all the register bits are set to “0”. All DFM interrupts are cleared by a single read operation. Table 14. LOS Interrupt Enable Register, LIE (06H) Bit1 Name 3-0 LIE3-LIE0 7-4 - Function Transceiver 3-0 LOS interrupts are enabled by writing a “1” to the respective bit. Write “0” to these positions for normal operation. 1. On power-up all the register bits are set to “0”and all interrupts are disabled. Table 15. DFM Interrupt Enable Register, DIE (07H) Bit1 Name 3-0 DIE3-DIE0 7-4 - Function Transceiver 3-0 DFM interrupts are enabled by writing a “1” to the respective bit. Write “0” to these positions for normal operation. 1. On power-up all the register bits are set to “0”and all interrupts are disabled. 40 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 16. LOS Interrupt Status Register, LIS (08H) Bit Name Function 3-0 LIS3-LIS0 These bits are set to “1” every time a LOS status change has occurred since the last clear interrupt in transceivers 3-0 respectively. Table 17. DFM Interrupt Status Register, DIS (09H) Bit Name 3-0 DIS3-DIS0 Function These bits are set to “1” every time a DFM status change has occurred since the last cleared interrupt in transceivers 3-0 respectively. Table 18. Software Reset Register, RES (0AH) Bit Name Function 3-0 RES3-RES0 Writing to this register initiates a 1 microsecond reset cycle, except for Intel nonmultiplexed mode. When using Intel non-multiplexed host mode, extend cycle time to 2 microseconds. Please refer to Host Mode section for more information. This operation sets all LXT386 registers to their default values. Table 19. Performance Monitoring Register, MON (0BH) Bit Name 3-0 A3:A0 4-7 reserved Function Protected Monitoring selection. See Table 1 on page 11. Reserved. Table 20. Digital Loopback Register, DL (0CH) Bit 1 Function2 Name 3-0 DL3-DL0 Setting a bit to “1” enables digital loopback for the respective transceiver. 1. On power up all register bits are set to “0”. 2. During digital loopback LOS and TAOS stay active and independent of TCLK, while data received on TPOS/TNEG/TCKLK is looped back to RPOS/RNEG/RCLK. Table 21. LOS/AIS Criteria Register, LCS (0DH) Bit1 Function2 Name T1 Mode2 Don’t care. T1.231 compliant LOS/AIS detection is used. 3-0 LCS3-LCS0 1 E1 Mode Setting a bit to “1” selects the ETS1 300233 LOS. Setting a bit to “0” selects G.775 LOS mode. AIS works correctly for both ETSI and ITU when the bit is cleared to “0”. See errata revision 10.3 or higher for a way to implement ETSI LOS and AIS. 1. On power-on reset the register is set to “0”. 2. T1 or E1 operation mode is determined by the PSDR settings. Datasheet 41 LXT386 — QUAD T1/E1/J1 Transceiver Table 22. Automatic TAOS Select Register, ATS (0EH) Bit1 Name 3-0 ATS3-ATS0 7-4 - Function Setting a bit to “1” enables automatic TAOS generation whenever a LOS condition is detected in the respective transceiver. Write “0” to these positions for normal operation. 1. On power-on reset the register is set to “0”. 2. This feature is not available in data recovery and line driver mode (MCLK= High and TCLK = High) Table 23. Global Control Register, GCR (0FH) Bit1 Name 0 JASEL0 1 Function These bits determine the jitter attenuator position: JASEL0 JASEL1 JA Position 1 0 Transmit Path 1 1 Receive Path 0 x Disabled JASEL1 2 JACF 3 FIFO64 4 CODEN 5 CDIS This bit determines the jitter attenuator low limit 3dB corner frequency. Refer to the Jitter Attenuator specifications for details (Table 41 on page 58). This bit determines the jitter attenuator FIFO depth: 0 = 32 bit 1 = 64 bit This bit selects the zero suppression code for unipolar operation mode: 0 = B8ZS/HDB3 (T1/E1 respectively) 1 = AMI This bit controls enables/disables the short circuit protection feature: 0 = enabled 1 = disabled This bit controls automatic AIS insertion in the receive path when LOS occurs: 6 RAISEN 0 = Receive AIS insertion disabled on LOS 1 = RPOS/RNEG = AIS on LOS Note: this feature is not available in data recovery mode (MCLK=High). Disable AIS interrupts when changing this bit value to prevent inadvertent interrupts. 7 - Reserved. 1. On power-on reset the register is set to “0”. 42 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 24. Pulse Shaping Indirect Address Register, PSIAD (10H) Bit1 Name Function The three bit value written to these bits determine the channel to be addressed: 0-2 LENAD 0-2 0H = channel 0 1H = channel 1 2H = channel 2 3H = channel 3 Data can be read from (written to) the Pulse Shaping Data Register (PSDAT). 3-7 - Reserved. 1. On power-on reset the register is set to “0”. Table 25. Pulse Shaping Data Register, PSDAT (11H) Bit Name Function LEN0-2 determine the LXT386 operation mode: T1 or E1. In addition, for T1 operation, LEN2-0 set the pulse shaping to meet the T1.102 pulse template at the DSX-1 crossconnect point for various cable lengths: LEN2 0-2 3-7 LEN 0-2 1, 3 - LEN1 LEN0 Line Length Cable Loss2 0 1 1 0 - 133 ft. ABAM 0.6 dB 1 0 0 133 - 266 ft. ABAM 1.2 dB 1 0 1 266 - 399 ft. ABAM 1.8 dB 1 1 0 399 - 533 ft. ABAM 2.4 dB 1 1 1 533 - 655 ft. ABAM 3.0 dB 0 0 0 E1 G.703, 75Ω coaxial cable and 120 Ω twisted pair cable. Operation Mode T1 E1 Reserved. 1. On power-on reset the register is set to “0”. 2. Maximum cable loss at 772 KHz. 3. When reading LEN, bit values appear inverted. “B1” revision silicon will fix this so the bits read back correctly. Table 26. Output Enable Register, OER (12H) Bit1 Name 3-0 OE3 - OE0 Function Setting a bit to “1” tristates the output driver of the corresponding transceiver. 1. On power-up all the register bits are set to “0”. Table 27. AIS Status Monitor Register, AIS (13H) Bit1 Name 3-0 AIS3-AIS0 Function Respective bit(s) are set to “1” every time the receiver detects a AIS condition in transceivers 3-0. 1. On power-up all the register bits are set to “0”. All AIS interrupts are cleared by a single read operation. Datasheet 43 LXT386 — QUAD T1/E1/J1 Transceiver Table 28. AIS Interrupt Enable Register, AISIE (14H) Bit1 Name 3-0 AISIE3-AISIE0 7-4 - Function Transceiver 3-0 AIS interrupts are enabled by writing a “1” to the respective bit. Write “0” to these positions for normal operation. 1. On power-up all the register bits are set to “0”. Table 29. AIS Interrupt Status Register, AISIS (15H) Bit1 Name Function 3-0 AISIS3-AISIS0 These bits are set to “1” every time a AIS status change has occurred since the last clear interrupt in transceivers 3-0 respectively. 1. On power-up all the register bits are set to “0”. 44 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 5.0 JTAG Boundary Scan 5.1 Overview The LXT386 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT386 also includes analog test port capabilities. This feature provides access to the TIP and RING signals in each channel (transmit and receive). This way, the signal path integrity across the primary winding of each coupling transformer can be tested. 5.2 Architecture Figure 15 represents the LXT386 basic JTAG architecture. The LXT386 JTAG architecture includes a TAP Test Access Port Controller, data registers and an instruction register. The following paragraphs describe these blocks in detail. Figure 15. LXT386 JTAG Architecture Boundry Scan Data Register BSR Analog Port Scan Register ASR TDI Device Identification Register IDR MUX TDO Bypass Register BYR Instruction Register IR TCK TMS TAP Controller TRST 5.3 TAP Controller The TAP controller is a 16 state synchronous state machine controlled by the TMS input and clocked by TCK ( Figure 16).The TAP controls whether the LXT386 is in reset mode, receiving an instruction, receiving data, transmitting data or in an idle state. Table 30 describes in detail each of the states represented in Figure 16. Datasheet 45 LXT386 — QUAD T1/E1/J1 Transceiver Table 30. TAP State Description State Description Test Logic Reset In this state the test logic is disabled. The device is set to normal operation mode. While in this state, the instruction register is set to the ICODE instruction. Run -Test/Idle The TAP controller stays in this state as long as TMS is low. Used to perform tests. Capture - DR The Boundary Scan Data Register (BSR) is loaded with input pin data. Shift - DR Shifts the selected test data registers by one stage tword its serial output. Update - DR Data is latched into the parallel output of the BSR when selected. Capture - IR Used to load the instruction register with a fixed instruction. Shift - IR Shifts the instruction register by one stage. Update - IR Loads a new instruction into the instruction register. Pause - IR Pause - DR Momentarily pauses shifting of data through the data/instruction registers. Exit1 - IR Exit1 - DR Exit2 - IR Exit2 - DR Temporary states that can be used to terminate the scanning process. 46 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 16. JTAG State Diagram 1 TEST-LOGIC RESET 0 0 RUN TEST/IDLE 1 SELECT-DR 1 SELECT-IR 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 0 0 SHIFT-DR SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR PAUSE-IR 1 1 EXIT2-DR 0 EXIT2-IR 1 0 UPDATE-DR 1 5.4 1 0 0 0 1 0 UPDATE-IR 1 0 JTAG Register Description The following paragraphs describe each of the registers represented in Figure 15. Datasheet 47 LXT386 — QUAD T1/E1/J1 Transceiver 5.4.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns to/from the board. Each pin is associated with a scan cell in the BSR register. Bidirectional pins or tristatable pins require more than one position in the register. Table 1 shows the BSR scan cells and their functions. Data into the BSR is shifted in LSB first. Example 1. Boundary Scan Register (BSR) Bit # Pin Signal I/O Type Bit Symbol 0 LOS3 O LOS3 RNEG3 O RNEG3 N/A - HIZ3 RPOS3 O RPOS3 RCLK3 O RCLK3 TNEG3 I TNEG3 TPOS3 I TPOS3 TCLK3 I TCLK3 LOS2 O LOS2 RNEG2 O RNEG2 N/A - HIZ2 RPOS2 O RPOS2 RCLK2 O RCLK2 TNEG2 I TNEG2 TPOS2 I TPOS2 TCLK2 I TCLK2 MCLK I MCLK MODE I MODE INT O INTRUPTB N/A - SDORDYENB ACK O SDORDY ALE I ALE OE I OE CLKE I CLKE A0 I A0 A1 I A1 A2 I A2 A3 I A3 48 A4 I A4 LOOP0 I/O PADD0 Comments HIZ3 controls the RPOS3, RNEG3 and RCLK3 pins. Setting HIZ3 to “0” enables output on the pins. Setting HIZ3 to “1” tristates the pins. HIZ2 controls the RPOS2, RNEG2 and RCLK2 pins. Setting HIZ2 to “0” enables output on the pins. Setting HIZ2 to “1” tristates the pins. SDORDYENB controls the ACK pin. Setting SDORDYENB to “0” enables output on ACK pin. Setting SDORDYENB to “1” tristates the pin. Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Example 1. Boundary Scan Register (BSR) (Continued) Bit # Pin Signal I/O Type Bit Symbol LOOP0 I/O PDO0 LOOP1 I/O PADI1 LOOP1 I/O PDO1 LOOP2 I/O PADI2 LOOP2 I/O PDO2 LOOP3 I/O PADI3 LOOP3 I/O PDO3 LOOP4 I/O PADI4 LOOP4 I/O PDO4 LOOP5 I/O PADI5 LOOP5 I/O PDO5 LOOP6 I/O PADI6 LOOP6 I/O PDO6 LOOP7 I/O PADI7 Comments PDOENB controls the LOOP0 through LOOP7 pins. N/A - PDOENB Setting PDOENB to “0” configures the pins as outputs. The output value to the pin is set in PDO[0..7]. Setting PDOENB to “1” tristates all the pins. The input value to the pins can be read in PADD[0..7]. LOOP7 I/O PDO7 CS I CSB MUX I MUX RESET I RSTB MOT/INTL I IMB R/W I RDB DS I WRB TCLK1 I TCLK1 TPOS1 I TPOS1 TNEG1 I TNEG1 RCLK1 O RCLK1 RPOS1 O RPOS1 N/A - HIZ1 RNEG1 O RNEG1 LOS1 O LOS1 TCLK0 I TCLK0 TPOS0 I TPOS0 TNEG0 I TNEG0 RCLK0 O RCLK0 Datasheet HIZ1 controls the RPOS1, RNEG1 and RCLK1 pins. Setting HIZ1 to “0” enables output on the pins. Setting HIZ1 to “1” tristates the pins. 49 LXT386 — QUAD T1/E1/J1 Transceiver Example 1. Boundary Scan Register (BSR) (Continued) Bit # 5.5 Pin Signal I/O Type Bit Symbol RPOS0 O RPOS0 N/A - HIZ0 RNEG0 O RNEG0 LOS0 O LOS0 Comments HIZ0 controls the RPOS0, RNEG0 and RCLK0 pins. Setting HIZ0 to “0” enables output on the pins. Setting HIZ0 to “1” tristates the pins. Device Identification Register (IDR) The IDR register provides access to the manufacturer number, part number and the LXT386 revision. The register is arranged per IEEE 1149.1 and is represented in Table 31. Data into the IDR is shifted in LSB first. Table 31. Device Identification Register (IDR) 5.5.1 Bit # Comments 31 - 28 Revision Number 27 - 12 Part Number 11 - 1 Manufacturer Number 0 Set to “1” Bypass Register (BYR) The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the TDO output. 5.5.2 Analog Port Scan Register (ASR) The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into the ASR is shifted in LSB first. Table 32 shows the 8 possible control codes and the corresponding operation on the analog port. The Analog Test Port can be used to verify continuity across the coupling transformers primary winding. The Analog Test Port can be used to verify continuity across the coupling transformer’s primary winding as shown in Figure 17. By applying a stimulus to the AT1 input, a known voltage will appear at AT2 for a given load. This, in effect, tests the continuity of a receive or transmit interface. 50 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 32. Analog Port Scan Register (ASR) 5.5.3 ASR Control Code AT1 Forces Voltage To: AT2 Senses Voltage From: 11111 TTIP0 TRING0 11110 TTIP1 TRING1 11101 TTIP2 TRING2 11100 TTIP3 TRING3 11011 Reserved 11010 Reserved 11001 Reserved 11000 Reserved 10111 RTIP0 RRING0 10110 RTIP1 RRING1 10101 RTIP2 RRING2 10100 RTIP3 RRING3 10011 Reserved 10010 Reserved 10001 Reserved 10000 Reserved Instruction Register (IR) The IR is a 3 bit shift register that loads the instruction to be performed. The instructions are shifted LSB first. Table 33 shows the valid instruction codes and the corresponding instruction description. Table 33. Instruction Register (IR) Instruction Code # EXTEST 000 Connects the BSR to TDI and TDO. Input pins values are loaded into the BSR. Output pins values are loaded from the BSR. INTEST_ANALOG 010 Connects the ASR to TDI and TDO. Allows voltage forcing/sensing through AT1 and AT2. Refer to Table 32. SAMPLE / PRELOAD 100 Connects the BSR to TDI and TDO. The normal path between the LXT386 logic and the I/O pins is maintained. The BSR is loaded with the signals in the I/O pins. IDCODE 110 Connects the IDR to the TDO pin. BYPASS 111 Serial data from the TDI input is passed to the TDO output through the 1 bit Bypass Register. Datasheet Comments 51 LXT386 — QUAD T1/E1/J1 Transceiver Figure 17. Analog Test Port Application JTAG Port ASR Register RTIP3 Transceiver 3 RRING3 TTIP3 TRING3 TTIP2 TRING2 1K Analog Mux RTIP2 RRING2 Transceiver 2 RTIP0 RRING0 Transceiver 0 1K AT2 AT1 52 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 6.0 Test Specifications Note: Table 34 through Table 53 and Figure 18 through Figure 33 represent the performance specifications of the LXT386 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in Table 36 through Table 53 are guaranteed over the recommended operating conditions specified in Table 35. Table 34. Absolute Maximum Ratings Parameter Symbol Min Max Unit DC supply voltage Vcc -0.5 4.0 V DC supply voltage Tvcc 0-3 -0.5 7.0 V Input voltage on any digital pin Vin GND-0.5 5.5 V Input voltage on RTIP, RRING1 Vin GND-0.5 VCC + 0.5 VCC + 0.5 V ESD voltage on any Pin 2 Vin 2000 Transient latch-up current on any pin Iin Input current on any digital pin 3 Iin Iin DC input current on TTIP, TRING 3 DC input current on RTIP, RRING 3 Storage temperature Maximum power dissipation in package – V 100 mA -10 10 mA – ±100 mA Iin – ±100 mA Tstor -65 +150 °C 830 mW PP Case Temperature, 100 pin LQFP package Tcase – 120 °C Case Temperature, 160 pin PBGA package Tcase – 120 °C Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. Referenced to ground. 2. Human body model. 3. Constant input current. Table 35. Recommended Operating Conditions Sym Min Typ Max Unit Test Condition VCC 3.135 3.3 3.465 V 3.3V ± 5% Transmitter supply voltage, TVCC=5V nominal TVCC 4.75 5.0 5.25 V 5V ± 5% Transmitter supply voltage, TVCC=3.3V nominal TVCC 3.135 3.3 3.465 V 3.3V ± 5% Ta -40 25 +85 °C Parameter Digital supply voltage (VCC) Ambient operating temperature LEN 1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. 2. Power consumption includes power absorbed by line load and external transmitter components. 3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101). 4. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load. Datasheet 53 LXT386 — QUAD T1/E1/J1 Transceiver Table 35. Recommended Operating Conditions (Continued) Parameter LEN Average Transmitter Power Supply Current, T1 Mode 1, 2, 3 Average Digital Power Supply Current 1, 4 Sym Min ITVCC - Typ Max Unit Test Condition 215 245 mA 100% 1’s 110 - mA 50% 1’s IVCC - 50 60 mA Rl 25 – – Ω Typ Max1,2 Unit Test Condition 440 - mW 50% 1’s Output load at TTIP and TRING Device Power Consumption Mode TVCC Load LEN 75 Ω E1 - - - - - 680 mW 100% 1’s - - 400 - mW 50% 1’s - - - 600 mW 100% 1’s - - 550 - mW 50% 1’s - - - 1025 mW 100% 1’s - - 610 - mW 50% 1’s - - - 930 mW 100% 1’s - - 540 - mW 50% 1’s - - - 810 mW 100% 1’s - - 830 - mW 50% 1’s - - - 1400 mW 100% 1’s 000 3.3V T13 3.3V E1 120 Ω 000 100 Ω 101-111 75 Ω 000 120 Ω 000 5.0V T13 100 Ω 5.0V 101-111 1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. 2. Power consumption includes power absorbed by line load and external transmitter components. 3. T1 maximum values measured with maximum cable length (LEN = 111). Typical values measured with typical cable length (LEN = 101). 4. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF load. Table 36. DC Characteristics Parameter Sym Min Typ High level input voltage Vih 2 – – V Low level input voltage Vil – – 0.8 V Voh 2.4 – VCC V IOUT= 400µA Vol – – 0.4 V IOUT= 1.6mA High level output voltage1 Low level output voltage 1 Low level input voltage Max Unit Vinl – – 1/3VCC-0.2 V MODE, LOOP0-3 Midrange level input voltage Vinm 1/3VCC+0.2 1/2VCC 2/3VCC-0.2 V and High level input voltage Vinh 2/3VCC+0.2 – – V JASEL Low level input current Iinl – – 50 µA High level input current Iinh – – 50 µA Test Condition 1. Output drivers will output CMOS logic levels into CMOS loads. 54 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 36. DC Characteristics (Continued) Parameter Input leakage current Sym Min Typ Max Unit Iil -10 +10 µA Tri state leakage current Ihz -10 +10 µA Tri state output current Ihz – – 1 µA Line short circuit current – – – 50 Input Leakage (TMS, TDI, TRST) – – – 50 mA RMS Test Condition TTIP, TRING 2 x 11 Ω series resistors and 1:2 transformer µA 1. Output drivers will output CMOS logic levels into CMOS loads. Table 37. E1 Transmit Transmission Characteristics Parameter Output pulse amplitude 75Ω Peak voltage of a space 75Ω Sym – 120Ω Transmit amplitude variation with supply – Difference between pulse sequences – Pulse width ratio of the positive and negative pulses 51kHz to 102 kHz Unit 2.14 2.37 2.60 V 2.7 3.0 3.3 V -0.237 0.237 V -0.3 0.3 V -1 +1 % 200 mV 0.95 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz 102 kHz to 2.048 MHz – 2.048 MHz to 3.072 MHz Transmit intrinsic jitter; 20Hz to 100kHz – 15 17 15 17 15 17 15 20 15 20 15 20 – 0.030 Tested at the line side For 17 consecutive pulses Rt = 11 Ω ± 1% 1:2 – Test Condition At the nominal half amplitude 1.05 – 75/120Ω characteristic impedance Transmit return loss 120 Ω twisted pair cable1 Max – Transmit transformer turns ratio for 51kHz to 102 kHz Typ – 120Ω Transmit return loss 75 Ω coaxial cable1 Min dB – dB Using components in the LXD384 evaluation board. dB dB – dB Using components in the LXD384 evaluation board. dB 0.050 U.I. Bipolar mode 2 U.I. Unipolar mode 7 U.I. Transmit path delay Tx path TCLK is jitter free JA Disabled 1. Guaranteed by design and other correlation methods. Table 38. E1 Receive Transmission Characteristics Parameter Sym Min Typ Max Unit – – – 12 dB Receiver dynamic range DR 0.5 – – Vp Signal to noise interference margin S/I -15 – – dB Permissible cable attenuation Test Condition @1024 kHz Per G.703, O.151 @ 6 dB cable Attenuation 1. Guaranteed by design and other correlation methods. Datasheet 55 LXT386 — QUAD T1/E1/J1 Transceiver Table 38. E1 Receive Transmission Characteristics (Continued) Parameter Data decision threshold Sym Min Typ Max Unit SRE 43 50 57 % Data slicer threshold – – 150 – mV Loss of signal threshold – – 200 – mV LOS hysteresis – – 50 – mV Consecutive zeros before loss of signal – – – – LOS reset – 12.5% – – – – 1.5 – – Low limit 1Hz to 20Hz input jitter 20Hz to 2.4kHz tolerance 1 18kHz to 100kHz 36 0.2 Differential receiver input impedance – – Input termination resistor tolerance – Common mode input impedance to ground – 51 kHz - 102 kHz Input return loss1 102 - 2048 kHz 32 2048 ETSI 300 233 specification 1’s density U.I. G735 recommendation U.I. Note 1 U.I. Cable Attenuation is 6 dB kΩ @1.024 MHz – – – ±1 % – 20 – kΩ dB Measured against nominal impedance using components in the LXD384 evaluation board. dB 20 2048kHz - 3072 kHz Rel. to peak input voltage G.775 recommendation 70 20 – Test Condition – dB 20 LOS delay time – – 30 – µs Data recovery mode LOS reset – 10 – 255 marks Data recovery mode Receive intrinsic jitter, RCLK output – – 0.040 0.0625 U.I. Receive path delay Bipolar mode 1 U.I. Unipolar mode 6 U.I. Wide band jitter JA Disabled 1. Guaranteed by design and other correlation methods. Table 39. T1 Transmit Transmission Characteristics Parameter Sym Min Typ Max Unit Output pulse amplitude – 2.4 3.0 3.6 V Test Condition Measured at the DSX Peak voltage of a space – -0.15 – +0.15 V Driver output impedance1 – – 1 – Ω Transmit amplitude variation with power supply – -1 – +1 % Ratio of positive to negative pulse amplitude – 0.95 – 1.05 – T1.102, isolated pulse Difference between pulse sequences – – – 200 mV Pulse width variation at half amplitude – – – 20 ns For 17 consecutive pulses, GR-499-CORE 0.020 10Hz - 8KHz Jitter added by Transmitter1 8KHz - 40KHz 10Hz - 40KHz Wide Band @ 772 KHz – – – 0.025 0.025 UIpk-pk AT&T Pub 62411 TCLK is jitter free. 0.050 1. Guaranteed by design and other correlation methods. 2. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern. 56 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 39. T1 Transmit Transmission Characteristics (Continued) Parameter Output power levels2 Sym @ 772 KHz Min – 17.9 -29 Unit dBm dBm 15 21 15 21 15 21 dB Bipolar mode 2 U.I. Unipolar mode 7 U.I. 51kHz to 102 kHz Transmit return loss 1 Max 12.6 – @ 1544 KHz Typ 102 kHz to 2.048 MHz – 2.048 MHz to 3.072 MHz dB – dB Transmit path delay Test Condition T1.102 - 1993 Referenced to power at 772 KHz With transmit series resistors (TVCC=5V). Using components in the LXD384 evaluation board. JA Disabled 1. Guaranteed by design and other correlation methods. 2. Power measured in a 3 KHz bandwidth at the point the signal arrives at the distribution frame for an all 1’s pattern. Table 40. T1 Receive Transmission Characteristics Parameter Sym Permissible cable attenuation – Receiver dynamic range DR Signal to noise interference margin S/I Data decision threshold SRE Min Typ Max Unit Test Condition – – 12 dB 0.5 – – Vp -16.5 – – dB @ 655 ft. of 22 ABAM cable 63 70 77 % Rel. to peak input voltage @ 772 KHz Data slicer threshold – – 150 – mV Loss of signal threshold – – 200 – mV LOS hysteresis – – 50 – mV Consecutive zeros before loss of signal – 100 175 250 – T1.231 - 1993 LOS reset – 12.5% – – – 1’s density Low limit 0.1Hz to 1Hz input jitter 4.9Hz to 300Hz tolerance 1 10KHz to 100KHz 138 - 28 - - Input termination resistor tolerance - - Common mode input impedance to ground - - 51 KHz - 102 KHz 102 - 2048 KHz - - 20 U.I. 70 20 - kΩ ±1 % - kΩ - - 20 30 - @772 kHz dB Measured against nominal impedance. Using components in the LXD384 evaluation board. µs Data recovery mode dB dB - - LOS reset - 10 - 255 - Receive intrinsic jitter, RCLK output1 - - 0.035 0.0625 U.I. Receive path delay AT&T Pub. 62411 U.I. 20 2048 KHz - 3072 KHz LOS delay time - 0.4 Differential receiver input impedance Input return loss1 U.I. Bipolar mode 1 U.I. Unipolar mode 6 U.I. Data recovery mode Wide band jitter JA Disabled 1. Guaranteed by design and other correlation methods. Datasheet 57 LXT386 — QUAD T1/E1/J1 Transceiver Table 41. Jitter Attenuator Characteristics Parameter Min Typ Max Unit - 2.5 - Hz - 3.5 - Hz - 2.5 - Hz - 3.5 - Hz - 3 - Hz - 3 - Hz - 6 - Hz - 6 - Hz E1 - 3.5 - Hz T1 - 6 - Hz - 17 - UI - 33 - UI - 24 - UI - 56 - UI -0.5 -0.5 +19.5 +19.5 – – dB ITU-T G.736 (Figure 34 on page 74) 0 0 33.3 40 40 – – dB AT&T Pub. 62411 (Figure 34 on page 74) 0.060 0.11 UI ETSI CTR12/13 Output jitter 32bit FIFO Test Condition JACF = 0 64bit E1 jitter attenuator 3dB corner frequency, host mode1 FIFO 32bit FIFO JACF = 1 64bit FIFO 32bit FIFO Sinusoidal jitter modulation JACF = 0 64bit T1 jitter attenuator 3dB corner frequency, host mode1 FIFO 32bit FIFO JACF = 1 64bit FIFO Jitter attenuator 3dB corner frequency, hardware mode1 32bit FIFO Data latency delay 64bit FIFO 32bit Input jitter tolerance before FIFO overflow or underflow FIFO 64bit FIFO Delay through the Jitter attenuator only. Add receive and transmit path delay for total throughput delay. @ 3 Hz @ 40 Hz @ 400 Hz @ 100 KHz E1 jitter attenuation @ 1 Hz T1 jitter attenuation @ 20 Hz @1 KHz @ 1.4 KHz @ 70 KHz Output Jitter in remote loopback1 1. Guaranteed by design and other correlation methods. 58 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 42. Analog Test Port Characteristics Parameter Sym 3 dB bandwidth Min Typ Max Unit At13db - 5 - MHz Input voltage range At1iv 0 - VCC V Output voltage range At2ov 0 - VCC V Test Condition Table 43. Transmit Timing Characteristics Parameter Sym Min Typ Max Unit Test Condition E1 MCLK – 2.048 – MHz T1 MCLK – 1.544 – MHz Master clock tolerance – -100 – 100 ppm Master clock duty cycle – 40 – 60 % E1 Tw 219 244 269 ns T1 Tw 291 324 356 ns E1 Tclke1 - 2.048 - MHz T1 Tclkt1 - 1.544 - MHz Transmit clock tolerance Tclkt -50 – +50 ppm Transmit clock burst rate Tclkb - – 20 MHz Transmit clock duty cycle Tdc 10 – 90 % NRZ mode RZ mode (TCLK = H for >16 clock cycles) Master clock frequency Output pulse width Transmit clock frequency E1 TPOS/TNEG pulse width (RZ mode) Tmpwe1 236 – 252 ns TPOS/TNEG to TCLK setup time Tsut 20 - - ns TCLK to TPOS/TNEG hold time Tht 20 - - ns Toez - - 1 µs Ttz 50 60 75 µs Delay time OE Low to driver High Z Delay time TCLK Low to driver High Z Gapped transmit clock Figure 18. Transmit Clock Timing Diagram TCLK TPOS tSUT tHT TNEG Datasheet 59 LXT386 — QUAD T1/E1/J1 Transceiver Table 44. Receive Timing Characteristics Parameter Sym Min Typ Max Unit Test Condition E1 – – ±80 – ppm Relative to nominal frequency T1 – – ±180 – ppm MCLK = ±100 ppm Rckd 40 50 60 % Clock recovery capture range Receive clock duty cycle 1 Receive clock pulse width 1 E1 Tpw 447 488 529 ns T1 Tpw 583 648 713 ns E1 Tpwl 203 244 285 ns T1 Tpwl 259 324 389 ns Receive clock pulse width Low time E1 Tpwh 203 244 285 ns T1 Tpwh 259 324 389 ns Tr 20 – – ns E1 Tpwdl 200 244 300 ns T1 Tpwdl 250 324 400 ns 200 244 – ns 200 324 – ns 200 244 – ns 200 324 – ns – – 5 ns Receive clock pulse width High time Rise/fall time 4 RPOS/RNEG pulse width (MCLK=H) 2 E1 RPOS/RNEG to RCLK rising setup time @ CL=15 pF Tsur T1 E1 RCLK Rising to RPOS/RNEG hold time Thr T1 Delay time between RPOS/RNEG and RCLK – MCLK = H 3 1. RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement for E1 per ITU G.823). 2. Clock recovery is disabled in this mode. 3. If MCLK = H the receive PLLs are replaced by a simple EXOR circuit. 4. For all digital outputs. Figure 19. Receive Clock Timing Diagram tPW RCLK tPWH tPWL tSUR tHR RPOS RNEG CLKE = 1 tSUR tHR RPOS RNEG CLKE = 0 60 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 45. JTAG Timing Characteristics Parameter Sym Min Typ Max Unit Cycle time Tcyc 200 - - ns J-TMS/J-TDI to J-TCK rising edge time Tsut 50 - - ns J-CLK rising to J-TMS/L-TDI hold time Tht 50 - - ns Tdod - - 50 ns J-TCLK falling to J-TDO valid Test Conditions Figure 20. JTAG Timing tCYC TCK tSUR tHT TMS TDI tDOD TDO Table 46. Intel Mode Read Timing Characteristics Parameter2 Address setup time to latch Sym Min Typ1 Max Unit Tsalr 10 – – ns Valid address latch pulse width Tvl 30 – – ns Latch active to active read setup time Tslr 10 – – ns Chip select setup time to active read Tscsr 0 – – ns – – ns Chip select hold time from inactive read Thcsr 0 Address hold time from inactive ALE Thalr 5 Active read to data valid delay time Tprd 10 – 50 ns Address setup time to RD inactive Thar 1 – – ns Test Conditions ns Address hold time from RD inactive Tsar 5 – – ns Inactive read to data tri-state delay time Tzrd 3 – 35 ns Valid read signal pulse width Tvrd 60 – – ns Inactive read to inactive INT delay time Tint – – 10 ns Active chip select to RDY delay time Tdrdy 0 – 12 ns Active ready Low time Tvrdy – – 40 ns Inactive ready to tri-state delay time Trdyz – – 3 ns 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. Datasheet 61 LXT386 — QUAD T1/E1/J1 Transceiver Figure 21. Non-Multiplexed Intel Mode Read Timing tSAR ADDRESS A4 - A0 tHAR ALE (pulled High) tHCSR tSCSR CS tVRD RD tPRD tZRD D7 - D0 DATA OUT tINT INT tDRDY tDRDY Tristate tVRDY tRDYZ Tristate RDY 62 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 22. Multiplexed Intel Read Timing tVL tSLR ALE tSCSR tHSCR CS tVRD tPRD RD tSALR tZRD tHALR ADDRESS AD7-AD0 DATA OUT tINT INT tDRDY tDRDY tVRDY tRDYZ Tristate Tristate RDY Table 47. Intel Mode Write Timing Characteristics Parameter2 Sym Min Typ1 Max Unit Tsalw 10 – – ns Valid address latch pulse width Tvl 30 – – ns Latch active to active write setup time Tslw 10 – – ns Address setup time to latch Chip select setup time to active write Tscsw 0 – – ns Chip select hold time from inactive write Thcsw 0 – – ns Address hold time from inactive ALE Thalw 5 Data valid to write active setup time Tsdw 40 – – ns Data hold time to active write Thdw 30 – – ns Address setup time to WR inactive Thaw 2 – – ns Address hold time from WR inactive Tsaw 6 – – ns Test Conditions ns 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. 3. These times don’t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset Operation and Host Mode sections for more information. Datasheet 63 LXT386 — QUAD T1/E1/J1 Transceiver Table 47. Intel Mode Write Timing Characteristics (Continued) Parameter2 Sym Min Typ1 Valid write signal pulse width Tvwr 60 Inactive write to inactive INT delay time Tint – Tdrdy Chip select to RDY delay time 3 Active ready Low time Inactive ready to tri-state delay time 3 Max Unit – – ns – 10 ns 0 – 12 ns Tvrdy – – 40 ns Trdyz – – 3 ns Test Conditions 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. 3. These times don’t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset Operation and Host Mode sections for more information. Figure 23. Non-Multiplexed Intel Mode Write Timing tSAW A4-A0 ALE ADDRESS (pulled High) tHAW tSCSW tHCSW CS tVWR WR tHDW tSDW D7-D0 WRITE DATA tINT INT tDRDY tDRDY Tristate tVRDY tRDYZ Tristate RDY 64 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 24. Multiplexed Intel Mode Write Timing tSLW ALE tVL tSCSW tHCSW CS tVWR WR tHALW tHDW tSALW tSDW ADDRESS AD7-AD0 WRITE DATA tINT INT tDRDY tDRDY tDRDYZ tVRDY Tristate Tristate RDY Table 48. Motorola Bus Read Timing Characteristics Parameter2 Sym Min Typ1 Max Unit Address setup time to address or data strobe Tsar 10 – – ns Address hold time from address or data strobe Thar 5 – – ns Valid address strobe pulse width Tvas 95 – – ns R/W setup time to active data strobe Tsrw 10 – – ns R/W hold time from inactive data strobe Thrw 0 – – ns Chip select setup time to active data strobe Tscs 0 – – ns Chip select hold time from inactive data strobe Thcs 0 – – ns Address strobe active to data strobe active delay Tasds 20 – – ns Delay time from active data strobe to valid data Tpds 3 – 30 ns Delay time from inactive data strobe to data High Z Tdz 3 – 30 ns Valid data strobe pulse width Tvds 60 – – ns Inactive data strobe to inactive INT delay time Tint – – 10 ns Data strobe inactive to address strobe inactive delay Tdsas 15 – – ns DS asserted to ACK asserted delay Tdackp – – 40 ns DS deasserted to ACK deasserted delay Tdack – – 10 ns Active ACK to valid data delay Tpack – – 0 ns Test Conditions 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. Datasheet 65 LXT386 — QUAD T1/E1/J1 Transceiver Figure 25. Non-Multiplexed Motorola Mode Read Timing A4-A0 ADDRESS tSAR AS tHAR (pulled High) tSRW tHRW R/W tSCS tHCS CS tVDS DS tPDS tDZ D7-D0 DATA OUT tINT INT tDACKP tPACK tDACK ACK 66 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 26. Multiplexed Motorola Mode Read Timing tVAS tDSAS AS tSRW tHRW R/W tSCS tHCS CS tASDS tVDS DS tPDS tSAR D7-D0 tHAR tDZ DATA OUT ADDRESS tINT INT tDACKP tDACK tPACK ACK Table 49. Motorola Mode Write Timing Characteristics Parameter2 Sym Min Typ1 Max Unit Address setup time to address strobe Tsas 10 – – ns Address hold time to address strobe Thas 5 – – ns Valid address strobe pulse width Tvas 95 – – ns R/W setup time to active data strobe Tsrw 10 – – ns R/W hold time from inactive data strobe Thrw 0 – – ns Chip select setup time to active data strobe Tscs 0 – – ns Chip select hold time from inactive data strobe Thcs 0 – – ns Address strobe active to data strobe active delay Tasds 20 – – ns Data setup time to DS deassertion Tsdw 40 – – ns Data hold time from DS deassertion Thdw 30 – – ns Valid data strobe pulse width Tvds 60 – – ns Inactive data strobe to inactive INT delay time Tint – – 10 ns Test Conditions 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. Datasheet 67 LXT386 — QUAD T1/E1/J1 Transceiver Table 49. Motorola Mode Write Timing Characteristics (Continued) Parameter2 Sym Min Typ1 Max Unit Data strobe inactive to address strobe inactive delay Tdsas 15 – – ns Active data strobe to ACK output enable time Tdack 0 – 12 ns DS asserted to ACK asserted delay Tdackp – 40 ns Test Conditions 1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CL= 100pF on D0-D7, all other outputs are loaded with 50pF. Figure 27. Non-Multiplexed Motorola Mode Write Timing A4-A0 ADDRESS tSAS tHAS AS (pulled High) tSRW tHRW R/W tSCS tHCS CS tVDS DS tSDW tHDW WRITE DATA D7-D0 tINT INT tDACKP tDACK ACK 68 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 g Figure 28. Multiplexed Motorola Mode Write Timin tVAS tDSAS AS tHRW tSRW R/W tHCS tSCS CS tASDS tVDS DS tSAS D7-D0 tHDW tHAS tSDW ADDRESS WRITE DATA tINT INT tDACKP tDACK ACK Table 50. Serial I/O Timing Characteristics Sym Min Typ1 Max Unit Rise/fall time any pin Trf - - 100 ns SDI to SCLK setup time Tdc 5 - - ns SCLK to SDI hold time Parameter Tcdh 5 - - ns SCLK Low time Tcl 25 - - ns SCLK High time Tch 25 - - ns Tr, Tf - - 50 ns SCLK rise and fall time CS falling edge to SCLK rising edge Tcc 10 - - ns Last SCLK edge to CS rising edge Tcch 10 - - ns CS inactive time Tcwh 50 - - ns SCLK to SDO valid delay time Tcdv - - 5 ns SCLK falling edge or CS rising edge to SDO High Z Tcdz - 10 - ns Test Condition Load 1.6mA, 50 pF 1. Typical figures are at 25 C° and are for design aid only; not guaranteed and not subject to production testing. Datasheet 69 LXT386 — QUAD T1/E1/J1 Transceiver Figure 29. Serial Input Timing CS tCWH tCC tCH tCCH tCL SCLK tCDH tDC tCDH LSB LSB SDI MSB CONTROL BYTE DATA BYTE Figure 30. Serial Output Timing CLKE = 0 2 1 3 4 5 6 7 8 9 10 11 1 2 12 13 14 15 5 6 16 SCLK CS tCCH tCDZ SDO 0 4 3 7 CLKE = 1 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK CS 0 SDO 1 2 3 4 5 tCDZ 6 tCCH 7 Table 51. Transformer Specifications3 Tx/Rx Turns Ratio1 Primary Inductance mH (min.) Leakage Inductance µH (max.) Interwinding Capacitance pF (max.) TX 1:2 1.2 0.60 60 RX 1:2 1.2 0.60 60 DCR Ω (max.) 0.70 pri 1.20 sec 1.10 pri 1.10 sec Dielectric Breakdown Voltage V2 (min.) 1500 Vrms 1500 Vrms 1. Transformer turns ratio accuracy is ± 2%. 1. This parameter is application dependent.LIU side: Line side. 2. Refer to the FAQ or Application Note 118 for recommended magnetics. 70 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Table 52. G.703 2.048 Mbit/s Pulse Mask Specifications Cable Parameter Unit TWP Coax Test load impedance 120 75 Ω Nominal peak mark voltage 3.0 2.37 V Nominal peak space voltage 0 ±0.30 0 ±0.237 V Nominal pulse width 244 244 ns Ratio of positive and negative pulse amplitudes at center of pulse 95-105 95-105 % Ratio of positive and negative pulse amplitudes at nominal half amplitude 95-105 95-105 % Figure 31. E1, G.703 Mask Templates 20% 20% V = 100% 10% 10% 269 ns (244+25) 194 ns (244- 50) NOMINAL PULSE 50% 244 ns 20% 10% 10% 0% 10% 10% 219 ns (244-25) 488 ns (244+244) Table 53. T1.102 1.544 Mbit/s Pulse Mask Specifications Cable Parameter Unit TWP 100 Ω Nominal peak mark voltage 3.0 V Nominal peak space voltage 0 ±0.15 V 324 ns 95-105 % Test load impedance Nominal pulse width Ratio of positive and negative pulse amplitudes Datasheet 71 LXT386 — QUAD T1/E1/J1 Transceiver Figure 32. T1, T1.102 Mask Templates 1.20 1.00 0.80 Normalized Amplitude 0.60 0.40 0.20 -0.80 -0.60 -0.40 -0.20 0.00 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -0.20 -0.40 -0.60 Tim e [UI] 72 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 33. LXT386 Jitter Tolerance Performance 1000 UI Jitter 100 UI 28 UI @ 4.9 Hz AT&T 62411, Dec 1990 (T1) 18 UI @ 1.8 Hz LXT386 typ. 28 UI @ 300 Hz 10 UI GR-499-CORE, Dec 1995 (T1) 5 UI @ 500 Hz 0.4 UI @ 10 kHz ITU G.823, Mar 1993 (E1) 1 UI 1.5 UI @ 2.4 kHz 1.5 UI @ 20 Hz .1 UI 1 Hz 0.2 UI @ 18 kHz 0.1 UI @ 8 kHz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Frequency Datasheet 73 LXT386 — QUAD T1/E1/J1 Transceiver Figure 34. Jitter Transfer Performance 10 dB E1 ITU G.736 Template 0.5 dB @ 3Hz 0 dB 0.5 dB @ 40Hz -10 dB Gain f 3dB =2.5 Hz -19.5 dB @ 20 kHz -20 dB f 3dB =3.5 Hz -19.5 dB @ 400 Hz -30 dB -40 dB LXT386 typ. -60 dB -80 dB 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Frequency T1 10 dB 0 dB @ 1 Hz 0 dB @ 20 Hz 0.1 dB @ 40 Hz 0.5 dB @ 350 Hz 0 dB AT&T Pub 62411 GR-253-CORE TR-TSY-000009 Gain -10 dB -20 dB -6 dB @ 2 Hz -33.3 dB @ 1 kHz f -30 dB 3dB f -33.7 dB @ 2.5kHz = 3 Hz 3dB -40 dB @ 1.4 kHz = 6 Hz -40 dB -40 dB @ 70 kHz -49.2 dB @ 15kHz LXT386 typ. -60 dB -60 dB @ 57 Hz -80 dB 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz Frequency 74 Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 35. Output Jitter for CTR12/13 applications Jitter Amplitude (Ulpp) 0.2 0.15 0.1 LXT386 typ, f 3dB = 2.5Hz & 3.5 Hz 0.05 0 10 Hz 6.1 20 Hz 100 Hz 1 kHz Frequency 10 kHz 100 kHz Recommendations and Specifications AT&T Pub 62411 ANSI T1.102 - 199X Digital Hierarchy Electrical Interface ANSI T1.231 -1993 Digital Hierarchy Layer 1 In-Service Digital Transmission Performance Monitoring Bellcore TR-TSY-000009 Asynchronous Digital Multiplexes Requirements and Objectives Bellcore GR-253-CORE SONET Transport Systems Common Generic Criteria Bellcore GR-499-CORE Transport Systems Generic Requirements G.703 Physical/electrical characteristics of hierarchical digital interfaces G. 704 Functional characteristics of interfaces associated with network nodes G.735 Characteristics of Primary PCM multiplex equipment operating at 2048 kbit/s and offering digital access at 384 kbit/s and/or synchronous digital access at 64 kbit/s G.736 Characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s G.772 Protected Monitoring Points provided on Digital Transmission Systems G.775 Loss of signal (LOS) and alarm indication (AIS) defect detection and clearance criteria G.783 Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/ s hierarchy O.151 Specification of instruments to measure error performance in digital systems OFTEL OTR-001 Short Circuit Current Requirements ETS 300166 Physical and Electrical Characteristics ETS 300386-1 Electromagnetic Compatibility Requirement Datasheet 75 LXT386 — QUAD T1/E1/J1 Transceiver 7.0 Mechanical Specifications Figure 36. 60 Plastic Ball Grid Array (PBGA) Package Dimensions 160 PBGA Package • Part Number LXT386BE • Extended Temperature Range (-40°C to 85° C) 15.00 13.00 ±0.20 1.00 REF 13.00 4.72 ±0.10 PIN #A1 CORNER 1.00 A 0.50 B ±0.10 C PIN #A1 ID D 4.72 ±0.10 1.00 E F 13.00 15.00 ±0.20 G 13.0 H J K L M N P Ø1.00 (3 plcs) 14 13 12 11 10 9 TOP VIEW 8 7 6 5 4 3 2 1 1.00 R BOTTOM VIEW 0.85 1.61 ± 0.19 NOTE: 1. ALL DIMENSIONS IN MILLIMETERS. SEATING PLANE SIDE VIEW 76 0.36 ±0.04 0.40 ± 0.10 2. ALL DIMENSIONS AND TOLERANCES CONFORM TO ASME Y 14.5M-1994. 3. TOLERANCE = ± 0.05 UNLESS SPECIFIED OTHERWISE. Datasheet QUAD T1/E1/J1 Transceiver — LXT386 Figure 37. 100 Pin Low Quad Flat Packages (LQFP) Dimensions 100 Pin LQFP • Part Number LXT386LE • Extended Temperature Range (-40°C to 85° C) ALL DIMENSIONS IN MILLIMETERS All dimensions and tolerances conform to ANSI Y14.5M-1982. 16.00 BSC 14.00 BSC 12.00 BSC 16.00 BSC 14.00 BSC 0.22 ±0.05 12.00 BSC Pin #1 Index 0.50 BSC 1 2 3 1.40 ±0.05 1.60 max See Detail "A" 0.05 min 0.15 max DETAIL "A" 0.60 ±0.15 0.20 min 1.00 REF Datasheet 77