LXT331 Dual T1/E1 Line Interface Unit Datasheet The LXT331 is a Dual Line Interface Unit (DLIU) optimized for North America 1.544 Mbps (T1) and international 2.048 Mbps (E1/CEPT) applications. It features a constant low output impedance transmitter for high return loss. Transmit pulse shape is selectable for various line lengths and cable types. The data recovery circuit also offers selectable slicer ratios for T1 or E1 applications. The LXT331 offers both a serial interface (SIO) for microprocessor control and a hardware control mode for stand-alone operation. The LXT331 offers a variety of advanced diagnostic and performance monitoring features. It uses an advanced double-poly, double-metal CMOS process and requires only a single 5-volt power supply. Applications ■ ■ ■ Digital Access and Cross-connect Systems (DACS) T1/E1 Multiplexer SONET/SDH Multiplexers ■ ■ ■ Digital Loop Carrier (DLC) terminals Cost efficient AFE for Digital Backend ASICS Analog LOS using PMRK/NMRK Product Features ■ ■ ■ ■ ■ Complete line driver and data recovery functions Constant low output impedance transmitter with a programmable equalizer that shapes pulses to meet the DSX-1 pulse template from 0 to 655 ft. High transmit and receive return loss Meets or exceeds industry specifications including ITU G.703 and ANSI T1. 1021993 Compatible with industry standard framers ■ ■ ■ ■ ■ Minimum receive signal of 500 mV, with selectable slicer levels (E1/DSX-1) to improve SNR Analog loopback function Transmit performance monitors with Driver Fail Monitor (DFM) output for transmit driver short circuit detection Transmit Driver Performance Monitor (DPM) output on external pins MTIP and MRING Available in 44-pin PLCC and 44-pin QFP packages As of January 15, 2001, this document replaces the Level One document LXT331 — Dual T1/E1 Line Interface Unit. Order Number: 249074-001 January 2001 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT331 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. Datasheet Dual T1/E1 Line Interface Unit — LXT331 Contents 1.0 Pin Assignments & Signal Descriptions .......................................................... 6 2.0 Functional Description...........................................................................................10 2.1 2.2 2.3 2.4 2.5 3.0 Receiver ..............................................................................................................10 Transmitter ..........................................................................................................10 2.2.1 Pulse Shape ...........................................................................................11 2.2.2 Driver Performance Monitor ...................................................................11 2.2.3 Driver Failure Monitor.............................................................................12 Control Modes .....................................................................................................12 2.3.1 Host Mode Control .................................................................................13 2.3.1.1 Serial Input Word.......................................................................13 2.3.1.2 Serial Output Word ....................................................................14 2.3.1.3 Interrupt Handling......................................................................14 2.3.2 Hardware Mode Control .........................................................................14 Diagnostic Mode Operation.................................................................................18 Initialization & Reset............................................................................................19 Application Information .........................................................................................20 3.1 3.2 Power Requirements...........................................................................................20 3.1.1 Line Interface Requirements ..................................................................20 Line Protection ....................................................................................................21 3.2.1 1.544 Mbps T1 Applications ...................................................................21 3.2.2 2.048 Mbps E1 Coax Applications .........................................................21 3.2.3 2.048 Mbps E1 Twisted-Pair Applications..............................................22 4.0 Test Specifications ..................................................................................................25 5.0 Mechanical Specifications....................................................................................30 Datasheet 3 LXT331 — Dual T1/E1 Line Interface Unit Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 LXT331 Block Diagram ......................................................................................... 5 LXT331 44 Pin Assignments and Markings .......................................................... 6 50% AMI Coding ................................................................................................. 11 LXT331 Driver Performance Monitor .................................................................. 13 LXT331 SIO Write Operations ............................................................................ 15 LXT331 SIO Read Operation .............................................................................. 16 LXT331 Interrupt Handling .................................................................................. 17 Transmit All Ones Data Path............................................................................... 18 TAOS with Analog Loopback .............................................................................. 19 Analog Loopback ................................................................................................ 19 Line Interface for E1 Coax ................................................................................. 22 Typical LXT331 T1 Application (Host Control Mode, Bipolar I/O) ....................... 23 Typical LXT331 E1 120 W Twisted Pair Application (Hardware Control Mode) . 24 LXT331 Transmit Clock Timing........................................................................... 27 LXT331 Receive Timing...................................................................................... 28 LXT331 Serial Input Timing Diagram .................................................................. 29 LXT331 Serial Output Timing Diagram ............................................................... 29 LXT331 PLCC Package Specification................................................................. 30 LXT331 QFP Package Specification................................................................... 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Descriptions .................................................................................................... 7 Equalizer Control Inputs - Hardware Mode1 ....................................................... 12 SIO Input Bit Settings (See Figure 5) .................................................................. 14 LXT331 Serial Data Output Bit Coding ............................................................... 15 Hardware Mode Diagnostic Selection ................................................................. 18 Recommended Transmit Transformer Values .................................................... 20 Transmit Transformer Combinations................................................................... 20 Absolute Maximum Ratings ................................................................................ 25 Recommended Operating Conditions ................................................................. 25 Electrical Characteristics (Over Recommended Operating Range) .................... 25 Analog Specifications (Over Recommended Operating Range) ......................... 26 LXT331 Master Clock and Transmit Timing Characteristics (See Figure 14) ..... 27 LXT331 Receive Characteristics (See Figure 15) ............................................... 27 LXT331 Serial I/O Timing Characteristics (See Figure 16 and Figure 17) .......... 28 Tables 4 Datasheet Dual T1/E1 Line Interface Unit — LXT331 Figure 1. LXT331 Block Diagram DPM Line Driver TCLK TPOS TNEG INT PS CLKE SCLK SDI SDO Transmit & Timing Control Serial Port Equalizer TX - PLL LEN Select Monitor Serial Word To Transceiver 1 Data Slicers NMRK MTIP MRING TTIP TRING DFM TAOS Enable PMRK MCLK Transmit Monitor ALOOP Enable Peak Detector DFM Analog Loopback RTIP RRING Transceiver 0 Transceiver 1 Datasheet 5 LXT331 — Dual T1/E1 Line Interface Unit 1.0 Pin Assignments & Signal Descriptions 1 44 43 42 41 40 PMRK1 2 NMRK1 TRSTE 3 TNEG1 TCLK0 4 TPOS1 TPOS0 5 TCLK1 NMRK0 6 TNEG0 PMRK0 Figure 2. LXT331 44 Pin Assignments and Markings ALOOP1/SDI ALOOP0/CLKE 7 39 TAOS0/SCLK 8 38 TAOS1/SDO LEN20/PS0 9 37 LEN21/PS1 36 LEN11/INT1 Rev # 35 LEN01/SPE LEN10/INT0 10 LEN00/GND 11 MCLK 12 GND 13 TTIP0 14 TGND0 LXT331PE XX LXT331PH XXXXXX XXXXXXXX Part # Part # LOT # FPO # 34 DFM1 33 VCC 32 TTIP1 15 31 TGND1 TVCC0 16 30 TVCC1 TRING0 17 29 TRING1 RTIP0 RRING0 DFM0 RRING1 RTIP1 DPM1 MRING1 MTIP1 TCLK0 TRSTE TCLK1 TPOS1 TNEG1 NMRK1 PMRK1 DPM0 TNEG0 MTIP0 MRING0 PMRK0 NMRK0 18 19 20 TPOS0 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 ALOOP0/CLKE 1 33 TAOS0/SCLK 2 32 TAOS1/SDO LEN20/PS0 3 31 LEN21/PS1 30 LEN11/INT1 29 LEN01/SPE 28 DFM1 27 VCC ALOOP1/SDI LEN10/INT0 4 LEN00/GND 5 MCLK 6 GND 7 TTIP0 8 26 TTIP1 TGND0 9 25 TGND1 TVCC0 10 24 TVCC1 TRING0 11 23 TRING1 LXT331QE XX LXT331QH XXXXXX XXXXXXXX Part # Part # LOT # FPO # Rev # MTIP1 MRING1 DPM1 RTIP1 RRING1 DFM0 RTIP0 RRING0 DPM0 MTIP0 MRING0 12 13 14 15 16 17 18 19 20 21 22 Package Topside Markings Marking Part # Unique identifier for this product family. Rev # Identifies the particular silicon “stepping” — refer to the specification update for additional stepping information. Lot # Identifies the batch. FPO # 6 Definition Identifies the Finish Process Order. Datasheet Dual T1/E1 Line Interface Unit — LXT331 Table 1. Pin Descriptions Pin PLCC Pin QFP Symbol I/O1 Description 1 39 TRSTE DI Tristate Enable. Forces all output pins to tri-state when held High and forces chip into reset mode. Holds reset mode for 6 µs after TRSTE returns Low. 2 40 TCLK0 DI Transmit Clock — Port 0. 1.544 MHz for T1, 2.048 MHz for E1. The transmit data inputs are sampled on the falling edge of TCLK. If TCLK is pulled Low, the transmit drivers are powered down and TTIP and TRING transmit outputs go to a high impedance state. 3 41 TPOS0 DI 4 42 TNEG0 DI 5 43 NMRK0 DO 6 44 PMRK0 DO CLKE DI Clock Edge Select (Host mode). When CLKE is High, SDO is valid on the rising edge of SCLK.When CLKE is Low, SDO is valid on the falling edge of SCLK. ALOOP0 DI Analog Local Loopback Enable, Port 0 (Hardware mode). When ALOOP is High, the RTIP/RRING inputs from the port 0 twisted-pair line are disconnected and the transmit data outputs (TTIP/TRING) are routed back into the receiver. For normal operation, hold ALOOP Low. SCLK DI Serial Clock (Host mode). Shifts data into or out of the serial interface register of the selected port. TAOS0 DI Transmit All Ones Enable, Port 0 (Hardware mode). When TAOS is High, the TPOS/TNEG input is ignored and the selected port transmits a stream of ones at the TCLK frequency. With no TCLK, the MCLK input becomes the transmit reference. For normal operation, hold TAOS Low. Refer to page 18. PS0 DI Port Select, Port 0 (Host mode). Selects the serial interface registers of Port 0. For each read or write operation, PS0 must transition from High to Low, and remain Low. LEN20 DI Line Length Equalizer 2, Port 0 (Hardware mode). Determines the shape and amplitude of the transmit pulse. Refer to Table 2 on page 12 INT0 DO Interrupt, Port 0 (Host mode). Goes Low to flag the host processor that Port 0 has changed state. INT0 is an open drain output and must be tied to VCC through a resistor. LEN10 DI Line Length Equalizer 1, Port 0 (Hardware mode). Determines the shape and amplitude of the transmit pulse. Refer to Table 2 on page 12 GND DI Unused (Host mode). Must be tied to Ground. LEN00 DI Line Length Equalizer 0, Port 0 (Hardware mode). Determines the shape and amplitude of the transmit pulse. Refer to Table 2 on page 12 7 8 9 10 11 1 2 Transmit Positive and Negative Data, Port 0. These pins drive the positive and negative sides of the bipolar input pair for port 0. Data to be transmitted onto the line is input at these pins. Receive Negative and Positive Marks, Port 0. These pins are the data outputs from port 0. A signal on NMRK corresponds to receipt of a negative pulse on RTIP/RRING. A signal on PMRK corresponds to receipt of a positive pulse on RTIP/RRING. NMRK/ PMRK outputs are Return-to-Zero (RZ). 3 4 5 12 6 MCLK DI Master Clock. 1.544 MHz for T1, 2.048 MHz for E1. Can be held Low if TCLK is present. 13 7 GND S Ground. Ground return for VCC power supply. 14 8 TTIP0 AO 15 9 TGND0 S Transmit Tip, Port 0. The TTIP and TRING pins are differential driver outputs designed to drive a 35-200 Ω load. Line matching resistors and transformers can be selected to give the desired pulse height. Ground, Port 0 Transmit Driver. Ground return for TVCC0 power supply. 1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; S = Power Supply Datasheet 7 LXT331 — Dual T1/E1 Line Interface Unit Table 1. Pin Descriptions (Continued) Pin PLCC Pin QFP Symbol I/O1 Description 16 10 TVCC0 S + 5 VDC Power Supply, Port 0 Transmit Driver. TVCC0 must not vary from TVCC1 or VCC by more than ± 0.3 V. 17 11 TRING0 AO Transmit Ring, Port 0. The TTIP and TRING pins are differential driver outputs designed to drive a 35-200 Ω load. Line matching resistors and transformers can be selected to give the desired pulse height. 18 12 MTIP0 AI 19 13 MRING0 AI 20 14 DPM0 DO 21 15 RTIP0 AI 22 16 RRING0 AI Receive Tip and Ring, Port 0. RTIP and RRING comprise the receive line interface. This input pair should be connected to the line through a 1:1 transformer. 23 17 DFM0 DO Driver Fail Monitor, Port 0. Goes High to indicate a driver output short condition. 24 18 RRING1 AI 25 19 RTIP1 AI 26 20 DPM1 DO Driver Performance Monitor, Port 1. Refer to DPM0 pin. 27 21 MRING1 28 22 MTIP0 AI Monitor Tip and Ring, Port 1. Refer to MRING0 and MTIP0 pins. 29 23 TRING1 AO Transmit Ring, Port 1. Refer to TRING0 pin. 30 24 TVCC1 S + 5 VDC Power Supply, Port 1 Transmit Driver. TVCC1 must not deviate from TVCC0 or VCC by more than ± 0.3 V. 31 25 TGND1 S Ground, Port 1 Transmit Driver. Ground return for TVCC1 power supply. 32 26 TTIP1 AO 33 27 VCC S 34 28 DFM1 DO Driver Fail Monitor, Port 1. Refer to DFM0 pin. SPE DI Serial Port Enable (Host mode). SPE must be clocked with MCLK, TCLK0 or TCLK1 to enable Host mode control through the serial port. LEN01 DI Line Length Equalizer 0, Port 1 (Hardware mode). Determines the shape and amplitude of the transmit pulse. Refer to Table 2 on page 12 INT1 DO Interrupt, Port 1 (Host mode). Refer to INT0 pin. LEN11 DI Line Length Equalizer 1, Port 1 (Hardware mode). Determines the shape and amplitude of the transmit pulse. Refer to Table 2 on page 12 PS1 DI Port Select, Port 1 (Host mode). Refer to PS0 pin. LEN21 DI Line Length Equalizer 2, Port 1 (Hardware mode). Determines the shape and amplitude of the transmit pulse. Refer to Table 2 on page 12 SDO DO Serial Data Output (Host mode). Read data from the LXT331 registers are output on this pin. When CLKE is High, SDO is valid on the rising edge of SCLK. When CLKE is Low, SDO is valid on the falling edge of SCLK. TAOS1 DI Transmit All Ones Enable, Port 1 (Hardware mode). Refer to TAOS0 pin. 35 36 37 38 Monitor Tip and Ring, Port 0. These pins monitor tip and ring outputs of either its own, or those of an adjacent LXT331 on the same board. If the application does not use this feature, tie one of these pins to a clock source and the other to a mid-level (referenced to the clock signal) voltage. The clock frequency can range from 100 kHz to the TCLK frequency. Driver Performance Monitor, Port 0. Goes High to indicate the detection of 63 consecutive zeros. Goes Low upon the receipt of a one on the transmit monitor loop (MTIP/MRING). Receive Tip and Ring, Port 1. Refer to RRING0 and RTIP0 pins. Transmit Tip, Port 1. Refer to TTIP0 pin. + 5 VDC Power Supply Input for All Circuits Except Transmit Drivers. 29 30 31 32 1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; S = Power Supply 8 Datasheet Dual T1/E1 Line Interface Unit — LXT331 Table 1. Pin Descriptions (Continued) Pin PLCC Pin QFP 39 33 Symbol I/O1 Description SDI DI Serial Data Input (Host mode). Write data to the LXT331 registers are input on this pin. SDI is sampled on the rising edge of SCLK. ALOOP1 DI Analog Local Loopback Enable, Port 1 (Hardware mode). Refer to pin ALOOP0. 40 34 PMRK1 DO 41 35 NMRK1 DO 42 36 TNEG1 DI 43 37 TPOS1 DI 44 38 TCLK1 DI Receive Negative and Positive Marks, Port 1. Refer to PMRK0 and NMRK0 pins. Transmit Negative and Positive Data, Port 1. Refer to TNEG0 and TPOS0 pins. Transmit Clock, Port 1. Refer to TCLK0 pin. 1. DI = Digital Input; DO = Digital Output; DI/O = Digital Input/Output; AI = Analog Input; AO = Analog Output; S = Power Supply Datasheet 9 LXT331 — Dual T1/E1 Line Interface Unit 2.0 Functional Description The LXT331 is a Dual Line Interface Unit (DLIU), which contains two ports. Refer to the simplified block diagram on page 1. The DLIU is designed for both 1.544 Mbps (DSX-1) and 2.048 Mbps (E1) applications. Both ports operate at the same frequency, which is determined by the TCLK input. Each port’s front end interfaces with two lines, one line for transmit, one line for receive. These two lines comprise a digital data loop for full-duplex transmission. Each port’s back-end interfaces with a layer processor through bipolar data I/O channels. The DLIU may either be controlled by a microprocessor via the serial port (Host mode), or by hardwired pins for stand-alone operation (Hardware mode). 2.1 Receiver The two receivers in the LXT331 DLIU are identical. The following paragraphs describe the operation of a single receiver. The input signal is received via a 1:1 transformer. The receiver requires fully differential inputs which are internally self-biased into 2.5 V. Recovered data is output at PMRK and NMRK. Refer to Test Specifications for receiver timing. The receive signal is processed through an adaptive peak detector and data slicers. The peak detector samples the received signal and determines its maximum value. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For DSX-1 applications (line length inputs LEN0-LEN2 ≠ 000 or 001), the threshold is set to 70% (typical) of the peak value. This threshold is maintained above the specified level for up to 15 successive zeros over the range of specified operating conditions. For E1 applications (LEN0-LEN2 = 000 or 001) the threshold is 50% (typical). The receiver is capable of accurately recovering signals with up to +13.6 dB of attenuation (from 2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is 1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level, the peak detectors are held above a minimum level of 0.3 V (typical) to provide immunity from impulsive noise. Built in pulse stretching circuitry maintains a minimum positive and negative mark pulse width (see Table 13 and Figure 15 on page 28). 2.2 Transmitter The two transmitters in the LXT331 DLIU are identical. The following paragraphs describe the operation of a single transmitter. Transmit data is clocked serially into the device at TPOS/TNEG. Input synchronization is supplied by the transmit clock (TCLK). The TPOS/TNEG inputs are sampled on the falling edge of TCLK. If TCLK is held Low, the transmitter remains powered down and the TTIP/TRING outputs are held in a high-Z state (except in TAOS mode if MCLK is available). Each output driver is provided with 10 Datasheet Dual T1/E1 Line Interface Unit — LXT331 a separate power supply pin (TVCC0 or TVCC1). Current limiters on the output drivers provide short circuit protection. Refer to Test Specifications for TCLK timing characteristics. As shown in Figure 3, the LXT331 encodes transmit data using 50% Alternate Mark Inversion (AMI) line code. Figure 3. 50% AMI Coding TTIP BIT CELL TRING 2.2.1 1 0 1 Pulse Shape The transmitted pulse shape is determined by Line Length equalizer control signals LEN0 through LEN2. Equalizer codes are hard-wired in Hardware mode as shown in Table 2. In Host mode, the LEN control codes are input through the serial interface. Shaped pulses are applied to the AMI line driver for transmission onto the line at TTIP and TRING. The line driver provides a constant Low output impedance of < 3 Ω (typical) regardless of whether it is driving marks or spaces or during transitions. This well-controlled impedance provides excellent return loss when used with external precision resistors (±1% accuracy). See Table 9 and Table 10 for recommended transformer specifications, turns ratios, series resistor (Rt) values, and typical return losses for various LEN codes. To minimize power consumption the DC blocking capacitor and the LXT331 can be connected directly to a 1:1.15 transformer without series resistors. Pulses can be shaped for either 1.544 or 2.048 Mbps applications. 1.544 Mbps pulses for DSX-1 applications can be programmed to match line lengths from 0 to 655 feet of 22 AWG ABAM cable. A combination of 9.1 Ω resistors and a 1:2.3 transformer is recommended for maximum transmit return loss in DSX-1 applications. The LXT331 also matches FCC pulse mask specifications for CSU applications. The LXT331 produces 2.048 Mbps pulses for both 75 Ω coaxial (2.37 V) or 120 Ω shielded twisted-pair (3.0 V) lines through an output transformer with a 1:2 turns ratio. Refer to the “Application Information” on page 20 for details on interface circuitry. 2.2.2 Driver Performance Monitor The LXT331 incorporates a Driver Performance Monitor (DPM) as shown in Figure 4 on page 13. The DPM output goes High on receipt of 63 consecutive zeros (at MTIP and MRING) and returns Low on receipt of a transition. A reset command also drives the output signal Low. The LXT331 uses its MTIP and MRING pins to monitor its own TTIP and TRING outputs or those of an adjacent chip. Mark detection involves two criteria: 1. Voltage threshold: a pulse must trip a threshold voltage above or below (depending on its polarity) the input bias voltage level. The LXT331 bias voltage is 2.5 V and the threshold for a mark is 2.5 ± 0.79 V. Datasheet 11 LXT331 — Dual T1/E1 Line Interface Unit 2. Pulse width: the monitor distinguishes between marks and noise pulses by the pulse width. LXT331 requires a mark pulse to be at least 120 ns wide (typical). As shown in Figure 4 on page 13, there are two type of marks: “A” and “B”. C1 and C2 detect “A” marks while the AND gate (A1) ensures that both mark signals are present at the same time. If the pulse widths are adequate, i.e. both a positive mark on MTIP and a negative mark on MRING, the A1 output goes High. Likewise C3 and C4 detect “B” marks. If the pulse meets the minimum width requirement, the AND gate (A2) output goes High when there are both a negative mark on MTIP and a positive mark on MRING. The OR gate (O1) passes the mark, as the signal “zero”, on to the clock/counter circuit which controls the DPM output. A latch samples the counter and goes High if the DPM circuit sees 63 consecutive zeros. Any mark resets the counter. The DPM signal goes High after the 63rd zero. Table 2. Equalizer Control Inputs - Hardware Mode1 LEN2 LEN1 LEN0 Line Length2 Cable Loss3 Low High High 0 - 133 ft ABAM 0.6 dB High Low Low 133-266 ft ABAM 1.2 dB High Low High 266-399 ft ABAM 1.8 dB High High Low 399-533 ft ABAM 2.4 dB High High High 533-655 ft ABAM 3.0 dB Low Low Low Low Low High Low High Low Application Frequency DSX-1 1.544 MHz E1 - Coax (75 Ω) ITU Recommendation G.703 E1 - Twisted-pair (120 Ω) 2.048 MHz FCC Part 68, Option A CSU 1.544 MHz 1. LEN0-2 inputs are shown as High or Low for Hardware mode. For Host mode serial inputs, High = 1 and Low = 0. 2. Line length from LXT331 to DSX-1 cross-connect point. 3. Maximum cable loss at 772 kHz. 2.2.3 Driver Failure Monitor The transceiver incorporates an internal Driver Failure Monitor (DFM) that observes TTIP and TRING. Driver failure is detected with a capacitor that is charged as a function of driver output current, and discharged as a measure of the maximum allowable current. Shorted lines draw excess current, overcharging the cap. When the capacitor charge deviates outside the nominal charge window, a driver failure is reported. In Host mode the DFM bit is set in the serial word. In both Hardware and Host modes the DFM pin goes High. During a long string of spaces, a short-induced overcharge eventually bleeds off, clearing the DFM flag. 2.3 Control Modes The LXT331 transceiver operates in either standalone Hardware mode (default) or Host mode. In Host mode a microprocessor controls the LXT331 via the serial I/O port (SIO) which provides common access to both LIUs. In Hardware mode, the transceiver is controlled through individual pins; a microprocessor is not required. 12 Datasheet Dual T1/E1 Line Interface Unit — LXT331 2.3.1 Host Mode Control Host mode is selected when a clock is applied to the SPE pin. Each of the two LIUs contains a pair of data registers, one for command inputs and one for status outputs. An SIO transaction is initiated by a falling pulse on one of the two Port Select pins, PS0 or PS1. Only one LIU can be selected at a time. A High-to-Low transition on PSn is required for each subsequent access to the Host mode registers. If both PS0 and PS1 are active simultaneously, Port 0 has priority over Port1. The LIU addressed by the PSn pulse responds by writing the incoming serial word (at the SDI pin) into its command register. Figure 5 on page 15 shows an SIO write operation. The 16-bit serial word consists of an 8-bit Command/Address byte and an 8-bit Data byte. If the command word contains a read request, the addressed LIU subsequently outputs the contents of its status register onto the SDO pin. Figure 6 on page 16 shows an SIO read operation. The Clock Edge (CLKE) signal determines when the SDO output is valid (relative to SCLK) as follows: If CLKE = High, SDO is valid on the rising edge of SCLK. If CLKE = Low, SDO is valid on the falling edge of SCLK. Refer to Test Specifications for SIO timing. 2.3.1.1 Serial Input Word Figure 5 on page 15 shows the Serial Input data structure. The LXT331 is addressed by setting bit A4 in the Address/Command byte, corresponding to address 16. Bit 1 of the serial Address/ Command byte provides Read/Write (R/W) control when the chip is accessed. The R/W bit is set to logic 1 to read the data output byte from the chip, and set to logic 0 to write the input data byte to the chip. Figure 4. LXT331 Driver Performance Monitor MTIP +2.5 V +790 mV +2.5 V -790 mV MRING + - C1 Pulse Width Monitor A A1 CLK + - C2 CNTR63 Pulse Width Monitor C zero* I O S Q DPM O1 + - C3 B + - C4 R Pulse Width Monitor R A2 Pulse Width Monitor The second 8 bits of a write operation (the Data Input byte) clear the Driver Performance Monitor (DPM) and Driver Fail Monitor (DFM) interrupts, reset the chip, and control diagnostic modes. The first and second bits (D0-1) clear and/or mask the DPM and DFM interrupts, and the last 3 bits (D5-7) control operating modes (normal and diagnostic) and chip reset. Refer to Table 3 for details on bits D5-7. Datasheet 13 LXT331 — Dual T1/E1 Line Interface Unit Table 3. 2.3.1.2 SIO Input Bit Settings (See Figure 5) Mode TST bit D5 ALOOP bit D6 TAOS bit D7 Analog Loopback 0 1 0 Transmit All Ones 0 X 1 Reset/High Z 1 1 0 Serial Output Word Figure 6 shows the Serial Output data structure. SDO is high impedance when SDI receives an Address/Command byte. If SDI receives a write command (R/W = 0), SDO remains in high impedance. If the command is a read (R/W = 1), then SDO becomes active after the last Command/ Address bit (A6) and remains active for eight SCLK cycles. Typically the first bit out of SDO changes the state of SDO from high Z to a Low/High. This occurs approximately 100 ns after the eighth following edge of SCLK. The output data byte reports DPM and DFM conditions, equalizer settings, and operating modes (normal or diagnostic). The first 5 bits (D0-4) report DPM and DFM status and the Line Length Equalizer settings. The last 3 bits (D5-7) report operating modes and interrupt status as defined in Table 4. If the INT line for the respective port is High (no interrupt is pending), bits D5-7 report the operating modes listed in Table 4. If the INT line for the respective port is Low, the interrupt status overrides all other reports and bits D5-7 reflect the interrupt status as listed in Table 4. 2.3.1.3 Interrupt Handling The Host mode provides two latched Interrupt output pins, INT0 and INT1, one for each LIU. An interrupt is triggered by a change in the DPM or DFM bit (D0=DPM, D1=DFM). As shown in Figure 7 on page 17, either or both interrupt generators can be masked by writing a 1 to the corresponding bit (D0 or D1) of the input data byte. When an interrupt occurrs, the INT output pin is pulled Low. The output stage of each INT pin consists of a pull-down device; thus an external pull-up resistor is required. Clear the interrupts as follows: 1. If one or both interrupt bits (DPM or DFM of the output data byte) are High, write a 1 to the corresponding bit of the input data byte to clear the interrupt. Leave a 1 in either bit position to effectively mask that interrupt. To re-enable the interrupt capability, reset either D0 or D1 or both to 0. 2. If neither DPM nor DFM is high, reset the chip to clear the interrupt. To reset the chip, set data input bits D5 and D6 = 1, and D7 = 0. 2.3.2 Hardware Mode Control Hardware control is the default operating mode. The LXT331 operates in Hardware mode unless a clock is applied to the LEN21/SPE pin. In Hardware mode, the SIO pins are re-mapped to provide control functions. In Hardware mode, the PMRK/NMRK outputs are valid on the rising edge of RCLK. 14 Datasheet Dual T1/E1 Line Interface Unit — LXT331 Table 4. LXT331 Serial Data Output Bit Coding Bit D5 Bit D6 Bit D7 Operating Modes 0 0 0 Reset has occurred, or no program input (i.e. normal operation). 0 0 1 TAOS active 0 1 0 ALOOP active 0 1 1 TAOS and ALOOP active Bit D5 Bit D6 Bit D7 1 0 1 DFM has changed state since the last Clear DFM occurred 1 1 0 DPM has changed state since the last Clear DPM occurred 1 1 1 DPM and DFM have changed state since the last Clear DPM and DMF occurred Interrupt Status Figure 5. LXT331 SIO Write Operations PSn SCLK Address/Command Byte SDI R/W A0 A1 A2 A3 A4 Data Input/Output Byte A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 SDO* A6 A0 Address/ Command Byte 0 R/W 0 0 0 0 1 0 X X = Don’t Care R/W = 1 : Read R/W = 0 : Write Set Operation Mode or Reset Clear/Mask Interrupt * SDO - remains high impedence Datasheet Input Data Byte D7 (MSB) D0 (LSB) DPM DFM 1 = CLEAR 1 = CLEAR LEN0 LEN1 LEN2 TST ALOOP TAOS 0 = Normal Ops 1 = ENABLE 1 = ENABLE 15 LXT331 — Dual T1/E1 Line Interface Unit Figure 6. LXT331 SIO Read Operation PSn SCLK Address/Command Byte SDI 1 R/W 0 A1 0 0 0 1 A4 0 X A6 DON’T CARE X = DON’T CARE SDO D0 HIGH IMPEDANCE Performance Monitor Data Output Byte D1 D2 Line Length Equalizer Setting D3 D4 D5 Operating Modes or Interrupt Status D7 (MSB) D0 (LSB) Output Data Byte 16 D7 D6 DPM DFM 1 = TRUE 1 = TRUE LEN0 LEN1 LEN2 TST 0 = Normal ALOOP TAOS 1 = ENABLED 1 = ENABLED Datasheet Dual T1/E1 Line Interface Unit — LXT331 Figure 7. LXT331 Interrupt Handling Start-up or Restart Interrupts enabled Mask Interrupts ? Yes No DPM Int = High (No interrupt) No Does an Interrupt Condition Exist ? Int = Low (interrupt) Read Output Status Word* (Bits D5-D7=Operating Mode) *Regardless of Interrupt Status, bit D0 indicates DPM status, D1 indicates DPM status and D2 - D4 indicate LEN status Write "1" to D0 of Input Status Word to Re-enable DPM Interrupt Yes Write "1" to D0 of Input Status Word to Mask DPM Interrupt What Interrupt DFM Condition Exists ? DFM AND DPM Write "1 1" to D0-D1 of Input Status Word to Re-enable DPM & DFM Interrupt No Write "1" to D1 of Input Status Word to Re-enable DFM Interrupt Write "1 1" to D0-D1 of Input Status Word to Mask DPM & DFM Interrupt Write "1" to D1 of Input Status Word to Mask DFM Interrupt Are Both Interrupt Conditions Masked ? Yes Read Output Status Word* (Bits D5-D7=Operating Mode) INT goes HIGH Re-Enable Interrupts ? DFM DPM & DFM Read Output Status Word* (Bits D5-D7=interrupt status) DPM Mask Which Interrupts ? *Regardless of Interrupt Status, bit D0 indicates DPM status D1 indicates DPM status and D2 - D7 indicate LEN status No Yes DPM Write "0" to D0 of Input Status Word to Re-enable DPM Interrupt Datasheet Re-Enable DFM which Interrupts ? DFM AND DPM Write "0 0" to D0-D1 of Input Status Word to Re-enable DPM & DFM Interrupts Write "0" to D1 of Input Status Word to Re-enable DFM Interrupt 17 LXT331 — Dual T1/E1 Line Interface Unit 2.4 Diagnostic Mode Operation The LXT331 offers two diagnostic modes. Analog Loopback (ALOOP) and Transmit All Ones (TAOS) are available under both Host and Hardware control modes. In Host mode, diagnostic modes are selected by writing the appropriate SIO bits. In Hardware mode, diagnostic modes are selected by a combination of pin settings. The pins must be held at the specified levels for a minimum of 20 ns (typically). Table 5 lists Hardware Mode control settings for the various diagnostic modes. Table 5. Hardware Mode Diagnostic Selection LXT331 Pin Mode TRSTE ALOOP TAOS Analog Loopback L H L Transmit All Ones L X H Reset/High Z H X X Transmit All Ones. See Figure 8. Transmit All Ones (TAOS) is selected when TAOS = 1. In TAOS mode the TPOS and TNEG inputs are ignored, but the transmitter remains locked to the TCLK input. When TAOS is selected, the transceiver transmits a continuous stream of 1s at the TCLK frequency. If TCLK is not supplied, MCLK is used as the transmit reference. TAOS and Analog Loopback can be selected simultaneously as shown in Figure 9. Analog Loopback. See Figure 10. Analog Loopback (ALOOP) is selected when ALOOP = 1. In ALOOP mode the receive line input (RTIP/RRING) is blocked. The transmit outputs (TTIP and TRING) are looped back through the receiver input and output at PMRK and NMRK. The transmitter circuits are unaffected by ALOOP. Transmitting onto an improperly terminated line may produce unexpected pulse widths at PMRK and NMRK. Reset / Tri-State. By holding the TRSTE pin High for at least 200 ns, all output drivers (both digital and analog) go to the high Z state and the chip logic is reset. The reset/high Z state is maintained for 6 µs after TRSTE returns Low. Figure 8. Transmit All Ones Data Path Transmit All Ones = TAOS TCLK TPOS TNEG PMRK NMRK 18 ALOOP 0 Timing & TTIP Control TAOS 1 TTIP (All 1s) TRING RTIP RRING Datasheet Dual T1/E1 Line Interface Unit — LXT331 Figure 9. TAOS with Analog Loopback ALOOP Transmit All Ones = 1 with ALOOP TAOS TCLK Timing & TPOS Control TNEG TAOS 1 TTIP (All 1s) TRING RTIP RRING PMRK NMRK Figure 10. Analog Loopback Analog Loopback TCLK TPOS TNEG PMRK NMRK 2.5 ALOOP 1 Timing & Control TAOS 0 TTIP TRING RTIP RRING Initialization & Reset Upon initial power up, the transceiver is held static until the power supply reaches approximately 3 V. Upon crossing this threshold, the device clears all internal registers. TCLK is the transmit reference, and MCLK is the bias reference. The PLLs are continuously calibrated. The transceiver can be reset from the Host or Hardware mode. In Host mode, reset is commanded by writing 1s to TST and ALOOP, and a 0 to TAOS (bits D5, D6 and D7, respectively, of the SIO input data byte). In either mode, reset is commanded by holding the TRSTE pin High for approximately 200 ns. All output signals are tri-stated at this time. In Hardware mode, the falling edge of TRSTE initiates reset for the entire chip. Host mode resets the selected port SIO registers to 0. Reset is not generally required for the port to be operational. Datasheet 19 LXT331 — Dual T1/E1 Line Interface Unit 3.0 Application Information 3.1 Power Requirements The LXT331 is a low-power CMOS device. Three separate power pins are provided: one pin for each port’s transmitter circuits (TVCC0 and TVCC1) and a pin for all remaining circuits (VCC). The LXT331 typically operates from a single +5 V power supply that is tied to all three VCC inputs. Note that all power pins must be within ±0.3 V of each other, and decoupled to their respective grounds separately. Isolation between the transmit and receive circuits is provided internally. During normal operation or analog loopback, the transmitter powers down when TCLK is not supplied. 3.1.1 Line Interface Requirements Table 6 lists transformer values for 1.544 Mbps and 2.048 Mbps applications. Table 7 shows combinations of transformers, series resistors and the LEN control settings that produce a variety of return loss values. Table 6. Recommended Transmit Transformer Values Parameter Table 7. Value Turns Ratio (T1) 1:2/1:1.15/1:2.3 (Tx)/ 1:1 (Rx) Turns Ratio (E1) 1:2 (Tx) / 1: 1 (Rx) Primary Inductance 1.2 mH minimum Leakage Inductance 0.5 µΗ maximum Interwinding Capacitance 25 pF maximum DC Resistance (Primary) 1 Ω maximum ET (Breakdown Voltage) 1 kV minimum Transmit Transformer Combinations LEN Xfmr Ratio1 Rt Value2 Rtn Loss3 For T1/DSX-1 100 Ω Twisted-Pair Applications: 011-111 1:2 Rt = 9.1 Ω 14dB 011-111 1:2.3 Rt = 9.1 Ω 18dB 1:1.15 Rt = 0 Ω 1dB 011-011 For E1 120 Ω Twisted-Pair Applications: 001 1:2 Rt = 15 Ω 18dB 000 1:2 Rt = 9.1 Ω 10dB 1. Transformer turns ratio accuracy is ± 2%. 2. Rt values are ± 1%. 3. Typical return loss, 51kHz - 3.072 MHz band, with a capacitor in parallel with the primary side of the transformer. 20 Datasheet Dual T1/E1 Line Interface Unit — LXT331 Table 7. Transmit Transformer Combinations LEN Xfmr Ratio1 Rt Value2 Rtn Loss3 For T1/DSX-1 100 Ω Twisted-Pair Applications: For E1 75 Ω Coaxial Applications: 001 1:2 Rt = 14.3 Ω 10dB 000 1:2 Rt = 9.1 Ω 18dB 1. Transformer turns ratio accuracy is ± 2%. 2. Rt values are ± 1%. 3. Typical return loss, 51kHz - 3.072 MHz band, with a capacitor in parallel with the primary side of the transformer. 3.2 Line Protection On the receive side, 1 kΩ series resistors protect the receiver against current surges coupled into the device. Due to the high receiver impedance (40 kΩ typical) the resistors do not affect the receiver sensitivity. On the transmit side, Schottky diodes D1-D4 protect the output driver. While not mandatory for normal operation, these protection elements are strongly recommended to improve the design’s robustness. 3.2.1 1.544 Mbps T1 Applications Figure 12 on page 23 shows a typical host mode T1 application. The serial interface pins are grouped at the top. Host mode is selected by applying clock (MCLK or TCLK) to the SPE pin. When the TRSTE pin (shown at lower left) is pulled Low, the LXT331 operates normally. Pulling this pin High causes all outputs to go to a high impedance state. Figure 12 on page 23 also shows a dual framer that recovers the clock from PMRK and NMRK. The DFM and DPM monitor output signals are available to drive optional external circuits. The transmitter power supply pins are tied to the common +5 VDC bus. Note that 68 µF decoupling capacitors are installed. The power supply for the remaining (non-driver) circuitry includes 1.0 µF and 0.1 µF decoupling capacitors. Note that all VCC pins must be within ±0.3 V of each other. The line interface circuitry is identical for both LIU ports. The precision resistors, in line with the transmit transformer, provide optimal return loss. The recommended transformer/resistor combinations (on the transmit side) are listed in Table 7. 1:1 transformers are used on the receive side. 3.2.2 2.048 Mbps E1 Coax Applications Figure 11 shows the line interface for a typical 2.048 Mbps E1/CEPT coaxial (75 Ω) application. The LEN code should be set to 000 for coax. With 9.1 Ω Rt resistors in line with 1:2 output transformers, the LXT331 produces 2.37 V peak pulses as required for coax applications. Datasheet 21 LXT331 — Dual T1/E1 Line Interface Unit Figure 11. Line Interface for E1 Coax Vcc 2 D1 Rt D2 470pF 1:2 TTIPn LXT331 1 D3 TRINGn Rt D4 Vcc 1kΩ RTIPn RRINGn 1:1 75 Ω 1kΩ 3.2.3 1 Typical value, adjust for board parasitics to obtain optimum return loss. 2 D1, D2, D3 & D4 are protection diodes (Schottky) International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1. 2.048 Mbps E1 Twisted-Pair Applications Figure 13 shows a typical 2.048 Mbps E1 twisted-pair (120 Ω) application. The line length equalizers are controlled by the hardwired LEN inputs. With the LEN code set to 001 and 15 Ω Rt resistors in line with the 1:2 output transformers, the LXT331 produces the 3.0 V peak pulses required for twisted-pair applications. 22 Datasheet Dual T1/E1 Line Interface Unit — LXT331 Figure 12. Typical LXT331 T1 Application (Host Control Mode, Bipolar I/O) To/From µP / Controller 1.544 MHz Clock Soure DPM0 PS1 INT1 INT0 PS0 SDO SDI SPE CLKE MCLK SCLK +5 V MTIP0 MRING0 DFM0 2 Rt See INSET for circuit TTIP0 TCLK0 TRING0 TPOS0 470 pF 1 Rt 1kΩ TNEG0 LXT331 PMRK0 Dual Framer 1:n 1:1 RTIP0 100 Ω 1kΩ NMRK0 RRING0 +5V VCC 0.1 µF 1 µF TCLK1 GND 1kΩ TPOS1 1:1 RTIP1 TNEG1 1kΩ PMRK1 100 Ω RRING1 NMRK1 2 Rt DPM1 TTIP1 DFM1 TRING1 TGND1 TVCC1 TVCC0 High-Z TGND0 Normal TRSTE See INSET for circuit 1:n 470 pF 11 Rt MRING1 MTIP1 INSET +5 V VCC 68 µF 68 µF D1 TTIPx D2 Typical Value. Adjust capacitor value for board parasitics to obtain optimum return loss. 2 Refer to Table 6 for transformer specifications. 1 NOTES: 1. Transformer turns ratio accuracy is ± 2%. 2. Refer to Table 7 for Rt values. 3. Typical return loss, 51 kHz - 3.072 MHz band. 4. D1, D2, D3 & D4 are protection diodes (Schottky) International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1. Datasheet VCC TRINGx D3 D4 23 LXT331 — Dual T1/E1 Line Interface Unit Figure 13. Typical LXT331 E1 120 Ω Twisted Pair Application (Hardware Control Mode) +5V 68 µF TVCC0 TGND0 ALOOP0 TAOS0 LEN20 DPM0 LEN10 MCLK LEN00 2.048 MHz Clock Source MTIP0 MRING0 2 DFM0 Rt See INSET for circuit TTIP0 TCLK0 TRING0 TPOS0 11 470 pF Rt 1kΩ TNEG0 Dual Framer 1:n 1:1 RTIP0 LXT331 PMRK0 120 Ω 1kΩ RRING0 NMRK0 +5V VCC 0.1 µF 1 µF GND TCLK1 1kΩ TPOS1 1:1 RTIP1 TNEG1 1kΩ 120 Ω RRING1 PMRK1 NMRK1 2 Rt TRING1 TAOS1 LEN21 High-Z LEN11 TRSTE LEN01 Normal TGND1 DFM1 TVCC1 TTIP1 ALOOP1 DPM1 See INSET for circuit 1:n 470 pF 11 Rt MRING1 INSET MTIP1 VCC +5V D1 TTIPx D2 68 µF VCC Typical Value. Adjust capacitor value for board parasitics to obtain optimum return loss. 2 Refer to Table 6 for transformer specifications. 1 NOTES: TRINGx D3 D4 1. Transformer turns ratio accuracy is ± 2%. 2. Refer to Table 7 for Rt values. 3. Typical return loss, 51 kHz - 3.072 MHz band. 4. D1, D2, D3 & D4 are protection diodes (Schottky) International Rectifier: 11DQ04 or 10BQ060; Motorola: MBR0540T1. 24 Datasheet Dual T1/E1 Line Interface Unit — LXT331 4.0 Test Specifications Note: Table 8. The minimum and maximum values in Table 8 through Table 14 and Figure 14 through Figure 17 represent the performance specifications of the LXT331 and are guaranteed by test, except where noted by design. Absolute Maximum Ratings Parameter Sym DC supply (referenced to GND) Min Max Unit VCC, TVCC0, TVCC1 -0.3 6.0 V Input voltage, any pin 1 VIN GND - 0.3 Vcc + 0.3 V Input current, any pin 2 IIN -10 10 mA TST -65 150 °C Storage temperature Caution: Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed or implied at these extremes. 1. Excluding RTIP and RRING which must stay within - 6 V to VCC + 0.3 V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. TTIP0 & 1, TRING0 & 1, VCC, TVCC0 & 1 and TGND0 & 1 can withstand continuous current of 100 mA. Table 9. Recommended Operating Conditions Symbol Minimum Typical1 Maximum Unit VCC, TVCC0, TVCC1 4.75 5.0 5.25 V TA -40 25 85 °C TA -5 25 85 °C Parameter DC supply 2 LXT331PE & QE ambient operating temperature LXT331PH & QH ambient operating temperature 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Variation between TVCC0, TVCC1 and VCC must be less than 0.3 V. Table 10. Electrical Characteristics (Over Recommended Operating Range) Sym Min Typ1 Max Unit Total power dissipation - T1 2 PP - 550 680 mW -40 to +85 °C (Maximum line length, 75 Ω load) PD - 550 650 mW 0 to +85 °C Parameter Total power dissipation - T1 3 (Maximum line length, 43 Ω load) Total power dissipation - E1 2 Test Conditions PP - 775 1000 mW -40 to +85 °C PD - 775 980 mW 0 to +85 °C PD - 380 520 mW 100% ones density 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. 100% 1s density and maximum line length. Driving a line load over operating temperature range. Includes device and load. Digital input levels are within 10% of the supply rails. Digital outputs are driving a 50 pF capacitive load. 3. 100% 1s density and maximum line length. Driving a line load (corresponding to Rt value of 9.1 Ω and 1:2 transformer ratio) over operating range. include device and load. Digital input levels are within 10% of the supply rails. Digital outputs are driving a 50 pF capacitive load. 4. Functionality of pins depends on mode. 5. Output drivers will output CMOS logic levels into CMOS loads. 6. All digital input pins. 7. For MTIP0, MRING0, MTIP1 AND MRING1. Datasheet 25 LXT331 — Dual T1/E1 Line Interface Unit Table 10. Electrical Characteristics (Over Recommended Operating Range) Parameter Sym Min High level input voltage 4,5 VIH 2.0 Low level input voltage 4,5 VIL - High level output voltage 4,5 VOH 2.4 Low level output voltage 4,5 Typ1 Max Unit - - V - 0.8 V - - V IOUT = - 400 µΑ IOUT = 1.6 mA VoL - - 0.4 V 6 ILLD 0 - ± 10 µA Input leakage current 7 ILLM 0 - ± 50 µA ISL - - ± 10 µA ITR - - 1.2 mA Input leakage current Three-state leakage current 4 TTIP/TRING leakage current Test Conditions In power down and tri-state 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. 100% 1s density and maximum line length. Driving a line load over operating temperature range. Includes device and load. Digital input levels are within 10% of the supply rails. Digital outputs are driving a 50 pF capacitive load. 3. 100% 1s density and maximum line length. Driving a line load (corresponding to Rt value of 9.1 Ω and 1:2 transformer ratio) over operating range. include device and load. Digital input levels are within 10% of the supply rails. Digital outputs are driving a 50 pF capacitive load. 4. Functionality of pins depends on mode. 5. Output drivers will output CMOS logic levels into CMOS loads. 6. All digital input pins. 7. For MTIP0, MRING0, MTIP1 AND MRING1. Table 11. Analog Specifications (Over Recommended Operating Range) Min Typ1 Max Unit DSX-1 2.4 3.0 3.6 V measured at the DSX E1 (120 Ω) 2.7 3.0 3.3 V measured at line side E1 (75 Ω) 2.13 2.37 2.61 V measured at line side Parameter AMI output pulse amplitudes Transmit amplitude variation with supply 3 Recommended output load at TTIP and TRING Driver output impedance 3 10 Hz - 8kHz 3 3 - 1 2.5 % - 75 - Ω - 3 10 Ω @ 772 kHz - 0.005 0.01 UI T1 Jitter Bands - 0.015 0.025 UI 10 Hz - 40 Hz 3 - 0.02 0.025 UI Broad band - 0.03 0.05 UI 20 Hz - 100 kHz - - 0.05 UI @ 772 kHz 12.6 - 17.9 dBm @ 1544 kHz -29 - - dB Positive-to-negative pulse imbalance - - 0.5 dB Differential input impedance - 40 - kΩ Sensitivity below DSX (0 dB = 2.4 V) 13.6 - - dB (max 6 dB cable attenuation) 500 - - mV Jitter added by the transmitter 2 Jitter added by the transmitter Output power levels 2 3 DSI 2 kHz BW 8 kHz - 40 kHz Test Conditions E1 Jitter Band 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Input signal at TCLK is jitter-free. 3. Not production tested, but guaranteed by design and other correlation methods. 26 Datasheet Dual T1/E1 Line Interface Unit — LXT331 Table 11. Analog Specifications (Over Recommended Operating Range) (Continued) Parameter Peak detector squelch level Min Typ1 Max Unit - 226 - mV DSX-1 63 70 77 % peak E1 43 50 57 % peak Test Conditions Data decision threshold 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 2. Input signal at TCLK is jitter-free. 3. Not production tested, but guaranteed by design and other correlation methods. Table 12. LXT331 Master Clock and Transmit Timing Characteristics (See Figure 14) Sym Min Typ1 Max Unit MCLK - 1.544 - MHz Parameter DSX-1 Master clock frequency MCLK - 2.048 - MHz Master clock tolerance E1 MCLKt - ± 50 - ppm Master clock duty cycle MCLKd 10 - 90 % TCLK - 1.544 - MHz DSX-1 Transmit clock frequency TCLK - 2.048 - MHz Transmit clock tolerance E1 TCLKt - ± 50 - ppm Transmit clock duty cycle TCLKd 10 - 90 % TPOS/TNEG to TCLK setup time tSUT 25 - - ns TCLK to TPOS/TNEG Hold time tHT 25 - - ns 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Figure 14. LXT331 Transmit Clock Timing TCLK t SUT t HT TPOS TNEG Table 13. LXT331 Receive Characteristics (See Figure 15) Sym Min Typ1 Max Unit T1 tMPW - 324 - ns E1 tMPW - 244 - ns tRXD - 65 - ns Parameter Test Conditions PMRK/NMRK pulse width Receiver throughput delay 3.0 V pulse 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Datasheet 27 LXT331 — Dual T1/E1 Line Interface Unit Figure 15. LXT331 Receive Timing RTIP RRING tRXD tMPW PMARK tMPW tRXD NMARK Table 14. LXT331 Serial I/O Timing Characteristics (See Figure 16 and Figure 17) Sym Min Typ1 Max Unit Rise/fall time - any digital output tRF - - 100 ns SDI to SCLK setup time tDC 50 - - ns SCLK to SDI hold time Parameter tCDH 50 - - ns SCLK low time tCL 240 - - ns SCLK high time tCH 240 - - ns tR, tF - - 50 ns PS to SCLK setup time tPC 50 - - ns SCLK to PS hold time tCPH 50 - - ns PS inactive time tPWH 250 - - ns SCLK to SDO valid tCDV - - 200 ns 16th SCLK falling edge or PS rising edge to SDO high Z tCDZ - 100 - ns SCLK rise and fall time Test Conditions Load 1.6 mA, 50pF 1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. 28 Datasheet Dual T1/E1 Line Interface Unit — LXT331 Figure 16. LXT331 Serial Input Timing Diagram tPWH PS tPC tCH tCL tCPH SCLK tDC SDI tCDH LSB tCDH LSB CONTROL BYTE MSB DATA BYTE Figure 17. LXT331 Serial Output Timing Diagram PS tCDZ SCLK tCDV tCDZ High Z SDO CLKE=1 tCDV SDO High Z CLKE=0 Datasheet 29 LXT331 — Dual T1/E1 Line Interface Unit 5.0 Mechanical Specifications Figure 18. LXT331 PLCC Package Specification CL Plastic Lead Chip Carrier (PLCC) C B • • • • • Part Number LXT331PE Temperature Range -40°C to + 85°C Part Number LXT331PH Temperature Range -5°C to + 85°C 44-Pin PLCC Inches Millimeters Dim D1 D Min Max Min Max A 0.165 0.180 4.191 4.572 A1 0.090 0.120 2.286 3.048 A2 0.062 0.083 1.575 2.108 B 0.050 – 1.270 – C 0.026 0.032 0.660 0.813 D 0.685 0.695 17.399 17.653 D1 0.650 0.656 16.510 16.662 F 0.013 0.021 0.330 0.533 D A2 A A1 F 30 Datasheet Dual T1/E1 Line Interface Unit — LXT331 Figure 19. LXT331 QFP Package Specification Quad Flat Pack • • • • • Part Number LXT331QE Temperature Range -40°C to + 85°C Part Number LXT331QH Temperature Range -5°C to + 85°C 44-Pin QFP D e/ D1 for sides with even number of pins D3 2 e E1 E3 for sides with odd number of pins E θ3 L1 A2 A θ A1 θ3 B L Inches Millimeters Dim Min Max Min Max A – 0.096 – 2.45 A1 0.010 – 0.25 – A2 0.077 0.083 1.95 2.10 B 0.012 0.018 0.30 0.45 D 0.510 0.530 12.95 13.45 D1 0.390 0.398 9.90 10.10 D3 0.315 BSC1 (nominal) 8.00 BSC1 (nominal) E 0.510 0.530 12.95 E1 0.390 0.398 9.90 13.45 10.10 E3 1 0.315 BSC (nominal) 8.00 BSC (nominal) e 0.031 BSC1 (nominal) 0.80 BSC1 (nominal) L 0.029 0.73 L1 0.063 REF (nominal) 0.041 1 1.03 1.60 REF (nominal) q3 5° 16° 5° 16° q 0° 7° 0° 7° 1. BSC—Basic Spacing between Centers Datasheet 31