NEC UPD16716N-XXX

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16716
384-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64-GRAY SCALES)
DESCRIPTION
The µ PD16716 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input
is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000
colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because
the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line
inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit
whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a
maximum clock frequency of 70 MHz when driving at 3.0 V, 45 MHz when driving at 2.5 V, this driver is applicable to
XGA/SXGA-standard TFT-LCD panels.
FEATURES
• CMOS level input (2.5 to 3.6 V)
• 384 Outputs
• Input of 6 bits (gray scale data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (RDAC)
• Logic power supply voltage (VDD1) : 2.5 to 3.6 V
• Driver power supply voltage (VDD2) : 15.0 V ± 0.5 V
• Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V
• High-speed data transfer: fCLK = 70 MHz (internal data transfer speed when operating at VDD1 = 3.0 V),
45 MHz (internal data transfer speed when operating at VDD1 = 2.5 V)
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output Voltage polarity inversion function (POL)
• Display data inversion function (capable of controlling by each input port) (POL21, POL22)
• Low power control function (LPC)
ORDERING INFORMATION
Part Number
µ PD16716N-×××
Package
TCP (TAB package)
Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact one of our
sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14417EJ1V1DS00 (1st edition)
Date Published June 2001 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
©
2000
µ PD16716
1. BLOCK DIAGRAM
STHR
R,/L
CLK
STB
STHL
VDD1
VSS1
64-bit bidirectional shift register
C1
C2
C63
D00 - D05
D10 - D15
D20 - D25
D30 - D35
D40 - D45
D50 - D55
POL21
POL22
C64
Data register
Latch
POL
VDD2
Level shifter
VSS2
V0 - V9
D/A converter
Voltage follower output
LPC
S1
S2
S3
S384
Remark /xxx indicates active low signal.
2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER
S1
V5
S383
5
V0
V4
S2
Multiplexer
6-bit D/A converter
5
V9
POL
2
Data Sheet S14417EJ1V1DS
S384
µ PD16716
3. PIN CONFIGURATION (µ PD16716N-xxx) (Copper Foil Surface, Face-up)
S384
S383
STHL
D55
D54
D53
D52
D51
D50
D45
D44
D43
D42
D41
D40
D35
D34
D33
D32
D31
D30
VDD1
R,/L
V9
V8
V7
V6
V5
VDD2
VSS2
V4
V3
V2
V1
V0
VSS1
LPC
CLK
STB
POL
POL21
POL22
D25
D24
D23
D22
D21
D20
D15
D14
D13
D12
D11
D10
D05
D04
D03
D02
D01
D00
STHR
Copper Foil
Surface
S3
S2
S1
Remark This figure does not specify the TCP package.
Data Sheet S14417EJ1V1DS
3
µ PD16716
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
I/O
Description
S1 to S384
Driver
O
The D/A converted 64-gray-scale analog voltage is output.
D00 to D05
Display data
I
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits)
D10 to D15
by 6 dots (2 pixels).
D20 to D25
DX0: LSB, DX5: MSB
D30 to D35
D40 to D45
D50 to D55
R,/L
Shift direction
I
Refers to the shift direction control. The shift directions of the shift registers are
control
as follows.
R,/L = H : STHR input, S1 → S384, STHL output
R,/L = L : STHL input, S384 → S1, STHR output

STHR
Right shift start
I/O
These refer to the start pulse I/O pins when driver ICs are connected in cascade.
Loading of display data starts when H is read at the rising edge of CLK.
pulse
R,/L = H (right shift): STHR input, STHL output

STHL
Left shift start pulse
I/O
R,/L = L (left shift): STHL input, STHR output
A high level should be input as the pulse of one cycle of the clock signal.
If the start pulse input is more than 2CLK, the first 1CLK of the high-level input is
valid.
CLK
Shift clock
I
Refers to the shift register’s shift clock input. The display data is loaded into the
data register at the rising edge.
At the rising edge of the 64th clock after the start pulse input, the start pulse
output reaches the high level, thus becoming the start pulse of the next-level

driver. If 66-clock pulses are input after input of the start pulse, input of display
data is halted automatically. The contents of the shift register are cleared at the
STB’s rising edge.
STB
Latch
I
The contents of the data register are transferred to the latch circuit at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It
is necessary to ensure input of one pulse per horizontal period.
POL
Polarity
I
POL = L : The S2n–1 output uses V0 to V4 as the reference supply. The S2n output
uses V5 to V9 as the reference supply.
POL = H : The S2n–1 output uses V5 to V9 as the reference supply. The S2n output
uses V0 to V4 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL
signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.

POL21, POL22
Data inversion
I
Data inversion can invert when display data is loaded.
POL21: Invert/not invert of display data D00 to D05, D10 to D15, D20 to D25.
POL22: Invert/not invert of display data D30 to D35, D40 to D45, D50 to D55.
POL21, POL22 = H : Display data is inverted.
POL21, POL22 = L : Display data is not inverted.
LPC
Low power control
I
The current consumption is lowered by controlling the constant current source of
the output amplifier. This pin is pulled up to the VDD1 power supply inside the IC.
In low power mode (LPC = L), the static current consumption of VDD2 reduced to
about 2/3 of the normal current consumption.
LPC = H or Open : Normal power mode
LPC = L : Low power mode
4
Data Sheet S14417EJ1V1DS
µ PD16716
(2/2)
Pin Symbol
V0 to V9
Pin Name
γ -corrected power
I/O
−
supplies
Description
Input the γ -corrected power supplies from outside by using operational amplifier.
Make sure to maintain the following relationships. During the gray scale voltage
output, be sure to keep the gray scale level power supply at a constant level.
VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +
0.1 V
VDD1
Logic power supply
−
2.5 V to 3.6 V
VDD2
Driver power supply
−
15.0 V ± 0.5 V
VSS1
Logic ground
−
Grounding
VSS2
Driver ground
−
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order.
Reverse this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is
possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a
bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply
terminals (V0, V1, V2, ···, V9) and VSS2.
Data Sheet S14417EJ1V1DS
5
µ PD16716
5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
This product incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively
gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The
D/A converter consists of ladder resistors and switches.
The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’
and V0’’ to V63’’ is almost equivalent. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9,
respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale
voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power
supplies V1 to V3 and V6 to V8.
Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and
VSS2, common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain
the voltage relationships as follows:
VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V.
Figures 5−2 and 5−3 show the relationship between input data and output voltage. This driver IC is designed for
only single-sided mounting
Figure 5−
−1. Relationship between Input Data and γ - corrected Power Supply
VDD2
0.1 V
V0
16
V1
16
V2
16
V3
15
V4
0.5 VDD2
Split interval
V5
15
V6
16
V7
16
V8
16
V9
0.1 V
VSS2
00
10
20
Input data (HEX)
6
Data Sheet S14417EJ1V1DS
30
3F
µ PD16716
Figure 5−
−2. Relationship between Input Data and Output voltage
VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2, POL21, POL22 = L
V63'
V0
r62
V62'
r61
V61'
r60
V60'
r59
r49
V49'
r48
V1
V48'
r47
V47'
r46
r17
V17'
r16
V16'
V3
r15
V15'
r14
r2
V2'
r1
V1'
r0
V4
V0'
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DX6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V0'
V1'
V2'
V3'
V4'
V5'
V6'
V7'
V8'
V9'
V10'
V11'
V12'
V13'
V14'
V15'
V16'
V17'
V18'
V19'
V20'
V21'
V22'
V23'
V24'
V25'
V26'
V27'
V28'
V29'
V30'
V31'
V32'
V33'
V34'
V35'
V36'
V37'
V38'
V39'
V40'
V41'
V42'
V43'
V44'
V45'
V46'
V47'
V48'
V49'
V50'
V51'
V52'
V53'
V54'
V55'
V56'
V57'
V58'
V59'
V60'
V61'
V62'
V63'
Output Voltage
V4
V4+(V3-V4) X
570
V4+(V3-V4) X
1190
V4+(V3-V4) X
1810
V4+(V3-V4) X
2410
V4+(V3-V4) X
2980
V4+(V3-V4) X
3320
V4+(V3-V4) X
3560
V4+(V3-V4) X
3800
V4+(V3-V4) X
4010
V4+(V3-V4) X
4220
V4+(V3-V4) X
4430
V4+(V3-V4) X
4670
V4+(V3-V4) X
4880
V4+(V3-V4) X
5090
V4+(V3-V4) X
5290
V3
V3+(V2-V3) X
170
V3+(V2-V3) X
340
V3+(V2-V3) X
490
V3+(V2-V3) X
640
V3+(V2-V3) X
790
V3+(V2-V3) X
940
V3+(V2-V3) X
1070
V3+(V2-V3) X
1190
V3+(V2-V3) X
1320
V3+(V2-V3) X
1450
V3+(V2-V3) X
1570
V3+(V2-V3) X
1700
V3+(V2-V3) X
1820
V3+(V2-V3) X
1940
V3+(V2-V3) X
2070
V2
V2+(V1-V2) X
120
V2+(V1-V2) X
240
V2+(V1-V2) X
360
V2+(V1-V2) X
490
V2+(V1-V2) X
610
V2+(V1-V2) X
730
V2+(V1-V2) X
850
V2+(V1-V2) X
970
V2+(V1-V2) X
1100
V2+(V1-V2) X
1220
V2+(V1-V2) X
1350
V2+(V1-V2) X
1480
V2+(V1-V2) X
1610
V2+(V1-V2) X
1760
V2+(V1-V2) X
1890
V1
V1+(V0-V1) X
170
V1+(V0-V1) X
340
V1+(V0-V1) X
490
V1+(V0-V1) X
670
V1+(V0-V1) X
850
V1+(V0-V1) X
1030
V1+(V0-V1) X
1240
V1+(V0-V1) X
1500
V1+(V0-V1) X
1820
V1+(V0-V1) X
2130
V1+(V0-V1) X
2450
V1+(V0-V1) X
2830
V1+(V0-V1) X
3310
V1+(V0-V1) X
3880
V0
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
/
/
/
/
/
/
/
/
/
/
/
/
/
/
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
rn
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
r32
r33
r34
r35
r36
r37
r38
r39
r40
r41
r42
r43
r44
r45
r46
r47
r48
r49
r50
r51
r52
r53
r54
r55
r56
r57
r58
r59
r60
r61
r62
rtotal
(Ω)
570
620
620
600
570
340
240
240
210
210
210
240
210
210
200
230
170
170
150
150
150
150
130
120
130
130
120
130
120
120
130
150
120
120
120
130
120
120
120
120
130
120
130
130
130
150
130
210
170
170
150
180
180
180
210
260
320
310
320
380
480
570
930
14650
Caution There is no connection between V4 and V5 terminal in the chip.
Data Sheet S14417EJ1V1DS
7
µ PD16716
Figure 5−
−3. Relationship between Input Data and Output voltage
0.5 VDD2 ≥V4 > V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V, POL21, POL22 = L
V5
V0''
r0
V1''
r1
V2''
r2
V3''
r3
r14
V15''
r15
V6
V16''
r16
V17''
r17
r46
r47
V47''
V48''
V8
r48
V49''
r49
r60
V61''
r61
V62''
r62
V9
V63''
Data
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
DX5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DX3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DX2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DX1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DX0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V0''
V1''
V2''
V3''
V4''
V5''
V6''
V7''
V8''
V9''
V10''
V11''
V12''
V13''
V14''
V15''
V16''
V17''
V18''
V19''
V20''
V21''
V22''
V23''
V24''
V25''
V26''
V27''
V28''
V29''
V30''
V31''
V32''
V33''
V34''
V35''
V36''
V37''
V38''
V39''
V40''
V41''
V42''
V43''
V44''
V45''
V46''
V47''
V48''
V49''
V50''
V51''
V52''
V53''
V54''
V55''
V56''
V57''
V58''
V59''
V60''
V61''
V62''
V63''
Output Voltage
V5
V6+(V5-V6) X
4950
V6+(V5-V6) X
4330
V6+(V5-V6) X
3710
V6+(V5-V6) X
3110
V6+(V5-V6) X
2540
V6+(V5-V6) X
2200
V6+(V5-V6) X
1960
V6+(V5-V6) X
1720
V6+(V5-V6) X
1510
V6+(V5-V6) X
1300
V6+(V5-V6) X
1090
V6+(V5-V6) X
850
V6+(V5-V6) X
640
V6+(V5-V6) X
430
V6+(V5-V6) X
230
V6
V7+(V6-V7) X
2050
V7+(V6-V7) X
1880
V7+(V6-V7) X
1730
V7+(V6-V7) X
1580
V7+(V6-V7) X
1430
V7+(V6-V7) X
1280
V7+(V6-V7) X
1150
V7+(V6-V7) X
1030
V7+(V6-V7) X
900
V7+(V6-V7) X
770
V7+(V6-V7) X
650
V7+(V6-V7) X
520
V7+(V6-V7) X
400
V7+(V6-V7) X
280
V7+(V6-V7) X
150
V7
V8+(V7-V8) X
1980
V8+(V7-V8) X
1860
V8+(V7-V8) X
1740
V8+(V7-V8) X
1610
V8+(V7-V8) X
1490
V8+(V7-V8) X
1370
V8+(V7-V8) X
1250
V8+(V7-V8) X
1130
V8+(V7-V8) X
1000
V8+(V7-V8) X
880
V8+(V7-V8) X
750
V8+(V7-V8) X
620
V8+(V7-V8) X
490
V8+(V7-V8) X
340
V8+(V7-V8) X
210
V8
V9+(V8-V9) X
4640
V9+(V8-V9) X
4470
V9+(V8-V9) X
4320
V9+(V8-V9) X
4140
V9+(V8-V9) X
3960
V9+(V8-V9) X
3780
V9+(V8-V9) X
3570
V9+(V8-V9) X
3310
V9+(V8-V9) X
2990
V9+(V8-V9) X
2680
V9+(V8-V9) X
2360
V9+(V8-V9) X
1980
V9+(V8-V9) X
1500
V9+(V8-V9) X
930
V9
Caution There is no connection between V4 and V5 terminal in the chip.
8
Data Sheet S14417EJ1V1DS
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
5520
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
2220
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
2100
/
/
/
/
/
/
/
/
/
/
/
/
/
/
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
4810
(Ω)
rn
r0
570
r1
620
r2
620
r3
600
r4
570
r5
340
r6
240
r7
240
r8
210
r9
210
r10
210
r11
240
r12
210
r13
210
r14
200
r15
230
r16
170
r17
170
r18
150
r19
150
r20
150
r21
150
r22
130
r23
120
r24
130
r25
130
r26
120
r27
130
r28
120
r29
120
r30
130
r31
150
r32
120
r33
120
r34
120
r35
130
r36
120
r37
120
r38
120
r39
120
r40
130
r41
120
r42
130
r43
130
r44
130
r45
150
r46
130
r47
210
r48
170
r49
170
r50
150
r51
180
r52
180
r53
180
r54
210
r55
260
r56
320
r57
310
r58
320
r59
380
r60
480
r61
570
r62
930
rtotal 14650
µ PD16716
6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN
Data format: 6 bits × 2 RGBs (6 dots)
Input width : 36 bits (2-pixel data)
R,/L = H (Right shift)
Output
S1
S2
S3
S4
xxx
S383
S384
Data
D00 to D05
D10 to D15
D20 to D25
D30 to D35
xxx
D40 to D45
D50 to D55
R,/L = L (Left shift)
Output
S1
S2
S3
S4
xxx
S383
S384
Data
D00 to D05
D10 to D15
D20 to D25
D30 to D35
xxx
D40 to D45
D50 to D55
Note
POL
Note
S2n–1
S2n
L
V0 to V4
V5 to V9
H
V5 to V9
V0 to V4
Note S2n-1 (Odd output), S2n (Even output)
7. RELATIONSHIP BETWEEN STB, POL, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
STB
POL
S2n-1
Selected voltage V0 - V4
Selected voltage V0 - V4
Selected voltage V5 - V9
S2n
Selected voltage V0 - V4
Selected voltage V5 - V9
Hi-Z
Hi-Z
Data Sheet S14417EJ1V1DS
Selected voltage V5 - V9
Hi-Z
9
µ PD16716
8.
RELATIONSHIP BETWEEN STB, CLK, AND OUTPUT WAVEFORM
The output voltage is written to the LCD panel synchronized with the STB falling edge.
Figure 8−
−1. Output Circuit Block Diagram
Output AMP
DAC
+
SW1
Sn
(VOUT)
VAMP(IN)
Figure 8−
−2. Output Circuit Timing Waveform
[1]
[2]
CLK
(External Input)
STB
(External Input)
SW1 : ON
SW1 : OFF
Output
Hi-Z
SW1 : ON
VAMP(IN)
Sn
(VOUT:External Output)
Output
Remarks 1. STB = L : SW1 = ON
STB = H : SW1 = OFF
2. STB = “H” is acknowledged at timing [1].
3. The display data latch is completed at timing [2] and the input voltage
(VAMP(IN) : gray-scale level voltage) of the output amplifier changes.
10
Data Sheet S14417EJ1V1DS
µ PD16716
9. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C, VSS1 = VSS2 = 0 V)
Symbol
Rating
Unit
Logic Part Supply Voltage
Parameter
VDD1
–0.5 to +4.0
V
Driver Part Supply Voltage
VDD2
–0.5 to +17.0
V
VI1
–0.5 to VDD1 + 0.5
V
Driver Part Input Voltage
VI2
–0.5 to VDD2 + 0.5
V
Logic Part Output Voltage
VO1
–0.5 to VDD1 + 0.5
V
Driver Part Output Voltage
VO2
–0.5 to VDD2 + 0.5
V
Logic Part Input Voltage
Operating Ambient Temperature
TA
–10 to +75
°C
Storage Temperature
Tstg
–55 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
3.6
V
15.0
15.5
V
Logic Part Supply Voltage
VDD1
2.5
Driver Part Supply Voltage
VDD2
14.5
High-Level Input Voltage
VIH
0.7 VDD1
VDD1
V
Low-Level Input Voltage
VIL
0
0.3 VDD1
V
γ -Corrected Voltage
V0 to V9
VSS2 + 0.1
VDD2 − 0.1
V
Driver Part Output Voltage
VO
VSS2 + 0.1
VDD2 − 0.1
V
Clock Frequency
fCLK
VDD1 = 3.0 V
70
MHz
VDD1 = 2.5 V
45
MHz
Data Sheet S14417EJ1V1DS
11
µ PD16716
★ Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.5 to 3.6 V, VDD2 = 15.0 V ± 0.5 V, VSS1 = VSS2 = 0 V,
Unless otherwise specified, power mode = normal, Bcont = open)
Parameter
Input Leak Current
Symbol
Conditions
VOH
STHR (STHL), IOH = 0 mA
Low-Level Output Voltage
VOL
STHR (STHL), IOL = 0 mA
Iγ
Current
VDD2 = 15.0 V
V0 to V4 = V5 to V9
= 7.5 V
Driver Output Current
TYP.
IIL
High-Level Output Voltage
γ -Corrected Supply
MIN.
MAX.
Unit
±1.0
µA
VDD1 − 0.1
V
0.1
V
V0 pin, V5 pin
200
800
µA
V4 pin, V9 pin
–800
–200
µA
–30
µA
IVOH
Vx = 14.0 V, VOUT = 13.5 V
IVOL
Vx = 1.0 V, VOUT = 1.5 V
∆VO
–75
30
µA
90
TA = +25°C, VOUT = 3.0 V, 7.5 V, 12.0 V
±10
±20
mV
Output swing difference
∆VP–P1
VDD1 = 3.3 V,
VOUT = 7.0 to 8.0 V
±5
±10
mV
deviation
∆VP–P2
VDD2 = 15.0 V,
VOUT = 1.6 to 12.8 V
±7
±13
mV
∆VP–P3
TA = +25°C
VOUT = 1.0 to 14.0 V
Output Voltage Deviation
Logic Part Dynamic
±10
±20
mV
IDD1
VDD1
5
12
mA
IDD2
VDD2 , with no load
8
16
mA
Current Consumption
Driver Part Dynamic
Current Consumption
Cautions 1. fSTB = 64 kHz, fCLK = 54 MHz.
2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the
measured values in the dot checkerboard input pattern.
3. Refers to the current consumption per driver when cascades are connected under the
assumption of XGA single-sided mounting (8 units).
12
Data Sheet S14417EJ1V1DS
µ PD16716
★ Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.5 to 3.6 V, VDD2 = 15.0 V ± 0.5 V, VSS1 = VSS2 = 0 V ,
Unless otherwise specified, power mode = normal, Bcont = open)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Start Pulse Delay Time
tPLH1
CL = 15 pF
12
ns
Driver Output Delay Time
tPLH2
CL = 83 pF, RL = 40 kΩ
6
µs
12
µs
tPHL2
7
µs
tPHL3 Note
12
µs
5
10
pF
10
15
pF
tPLH3 Note
Input Capacitance
CI1
STHR (STHL) excluded,
TA = +25°C
CI2
STHR (STHL),TA = +25°C
Note tPLH3/tPHL3 are specified as the time it takes to reach the target voltage ±2%.
<Measurement Condition>
RL
RL
RL
RL
RL
RL= 8 kΩ
Output
CL= 16.6 pF
CL
CL
CL
Data Sheet S14417EJ1V1DS
CL
CL
13
µ PD16716
Timing Requirement (TA = –10 to +75°C, VDD1 = 2.5 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns)
Parameter
Clock Pulse Width
Symbol
PW CLK
Condition
MIN.
TYP.
MAX.
Unit
VDD1 = 3.3 V ± 0.3 V
14
ns
VDD1 = 2.5 to 3.0 V
22
ns
Clock Pulse High Period
PW CLK(H)
4
ns
Clock Pulse Low Period
PW CLK(L)
4
ns
tSETUP1
2
ns
Data Hold Time
tHOLD1
2
ns
Start Pulse Setup Time
tSETUP2
2
ns
Start Pulse Hold Time
tHOLD2
2
ns
POL21, POL22 Setup Time
tSETUP3
2
ns
Data Setup Time
POL21, POL22 Hold Time
tHOLD3
2
ns
STB Pulse Width
PW STB
1.5
µs
Last Data Timing
tLDT
2
CLK
CLK-STB Time
tCLK-STB
CLK ↑ → STB ↑
4
ns
STB-CLK Time
tSTB-CLK
STB ↑ → CLK ↑
4
ns
Time between STB and Start Pulse
tSTB-STH
STB ↑ → STHR (STHL) ↑
2
CLK
POL-STB Time
tPOL-STB
POL ↑ or ↓ → STB ↑
–5
ns
STB-POL Time
tSTB-POL
STB ↓ → POL ↓ or ↑
4
ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
14
Data Sheet S14417EJ1V1DS
INVALID
POL21,
POL22
Data Sheet S14417EJ1V1DS
Sn (VOUT)
POL
STB
STHL
(1st Dr.)
INVALID
tSETUP2
Dn0 - Dn5
STHR
(1st Dr.)
CLK
tHOLD1
3
PWCLK(H)
tSETUP3
tHOLD3
D7 - D12
tSETUP1
2
D1 - D 6
tHOLD2
1
PWCLK(L) PWCLK
tPLH1
D373 D378
64
D379 D384
65
D385 D390
66
D3067 D3072
513
Hi-z
PWSTB
tCLK-STB tSTB-CLK
tPOL-STB
tLDT
514
tPHL2
tPHL3
tPLH3
tPLH2
tSTB-POL
INVALID
INVALID
tSTB-STH
D1-D6
2
10%
tr
D7-D12
90%
tf
Target Voltage −
+ 0.1 VDD2
6-bit accuracy
1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
µ PD16716
Switching Characteristics Waveform
Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1.
15
µ PD16716
10. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met for soldering conditions of the µ PD16716.
For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E).
Please consult with our sales offices in case other soldering process is used, or in case the soldering is done
under different conditions.
××× : TCP (TAB package)
µ PD16716N-×××
Mounting Condition
Thermocompression
Mounting Method
Soldering
Condition
Heating tool 300 to 350°C: heating for 2 to 3 seconds: pressure 100g (per
solder)
ACF
Temporary bonding 70 to 100°C: pressure 3 to 8 kg/cm2 : time 3 to 5
(Adhesive
seconds.
Conductive Film)
Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2 : time 30 to 40
seconds. (When using the anisotropy conductive film SUMIZAC1003 of
Sumitomo Bakelite, Ltd.)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing
company. Be sure to avoid using two or more packaging methods at a time.
16
Data Sheet S14417EJ1V1DS
µ PD16716
[MEMO]
Data Sheet S14417EJ1V1DS
17
µ PD16716
[MEMO]
18
Data Sheet S14417EJ1V1DS
µ PD16716
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14417EJ1V1DS
19
µ PD16716
Reference Documents
NEC Semiconductor Device Reliability / Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
• The information in this document is current as of May, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4